include/configs/atc.h

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU               */
  21 #define CONFIG_ATC              1       /* ...on a ATC board    */
  22 #define CONFIG_CPM2             1       /* Has a CPM2 */
  23
  24 #define CONFIG_SYS_TEXT_BASE    0xFF000000
  25
  26 /*
  27  * select serial console configuration
  28  *
  29  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  30  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  31  * for SCC).
  32  *
  33  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  34  * defined elsewhere (for example, on the cogent platform, there are serial
  35  * ports on the motherboard which are used for the serial console - see
  36  * cogent/cma101/serial.[ch]).
  37  */
  38 #define  CONFIG_CONS_ON_SMC             /* define if console on SMC */
  39 #undef CONFIG_CONS_ON_SCC               /* define if console on SCC */
  40 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
  41 #define CONFIG_CONS_INDEX       2       /* which serial channel for console */
  42
  43 #define CONFIG_BAUDRATE         115200
  44
  45 /*
  46  * select ethernet configuration
  47  *
  48  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  49  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  50  * for FCC)
  51  *
  52  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  53  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  54  */
  55 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
  56 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  57 #define CONFIG_ETHER_ON_FCC
  58
  59 #define CONFIG_ETHER_ON_FCC2
  60
  61 /*
  62  * - Rx-CLK is CLK13
  63  * - Tx-CLK is CLK14
  64  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  65  * - Enable Full Duplex in FSMR
  66  */
  67 # define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
  68 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
  69 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  70 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
  71
  72 #define CONFIG_ETHER_ON_FCC3
  73
  74 /*
  75  * - Rx-CLK is CLK15
  76  * - Tx-CLK is CLK16
  77  * - RAM for BD/Buffers is on the local Bus (see 28-13)
  78  * - Enable Half Duplex in FSMR
  79  */
  80 # define CONFIG_SYS_CMXFCR_MASK3        (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
  81 # define CONFIG_SYS_CMXFCR_VALUE3       (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
  82
  83 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
  84 #define CONFIG_8260_CLKIN       64000000        /* in Hz */
  85
  86 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  87
  88 #undef  CONFIG_CLOCKS_IN_MHZ            /* clocks passsed to Linux in Hz */
  89
  90 #define CONFIG_PREBOOT                                                  \
  91         "echo;"                                                         \
  92         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;"\
  93         "echo"
  94
  95 #undef  CONFIG_BOOTARGS
  96 #define CONFIG_BOOTCOMMAND                                              \
  97         "bootp;"                                                        \
  98         "setenv bootargs root=/dev/nfs rw "                             \
  99         "nfsroot=${serverip}:${rootpath} "                              \
 100         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\
 101         "bootm"
 102
 103 /*-----------------------------------------------------------------------
 104  * Miscellaneous configuration options
 105  */
 106
 107 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 108 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 109
 110
 111 /*
 112  * BOOTP options
 113  */
 114 #define CONFIG_BOOTP_SUBNETMASK
 115 #define CONFIG_BOOTP_GATEWAY
 116 #define CONFIG_BOOTP_HOSTNAME
 117 #define CONFIG_BOOTP_BOOTPATH
 118 #define CONFIG_BOOTP_BOOTFILESIZE
 119
 120
 121 /*
 122  * Command line configuration.
 123  */
 124 #include <config_cmd_default.h>
 125
 126 #define CONFIG_CMD_EEPROM
 127 #define CONFIG_CMD_PCI
 128 #define CONFIG_CMD_PCMCIA
 129 #define CONFIG_CMD_DATE
 130 #define CONFIG_CMD_IDE
 131
 132
 133 #define CONFIG_DOS_PARTITION
 134
 135 /*
 136  * Miscellaneous configurable options
 137  */
 138 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 139 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 140 #if defined(CONFIG_CMD_KGDB)
 141 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 142 #else
 143 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 144 #endif
 145 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 146 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 147 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 148
 149 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 150 #define CONFIG_SYS_MEMTEST_END  0x0C00000       /* 4 ... 12 MB in DRAM  */
 151
 152 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 153
 154 #define CONFIG_SYS_PIO_MODE             0       /* IDE interface in PIO Mode 0  */
 155
 156 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 157
 158 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100     /* "bad" address                */
 159
 160 #define CONFIG_SYS_ALLOC_DPRAM
 161
 162 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 163
 164 #define CONFIG_SPI
 165
 166 #define CONFIG_RTC_DS12887
 167
 168 #define RTC_BASE_ADDR           0xF5000000
 169 #define RTC_PORT_ADDR           RTC_BASE_ADDR + 0x800
 170 #define RTC_PORT_DATA           RTC_BASE_ADDR + 0x808
 171
 172 #define CONFIG_MISC_INIT_R
 173
 174 /*
 175  * For booting Linux, the board info and command line data
 176  * have to be in the first 8 MB of memory, since this is
 177  * the maximum mapped by the Linux kernel during initialization.
 178  */
 179 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 180
 181 /*-----------------------------------------------------------------------
 182  * Flash configuration
 183  */
 184
 185 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 186 #define CONFIG_SYS_FLASH_SIZE           0x00800000
 187
 188 /*-----------------------------------------------------------------------
 189  * FLASH organization
 190  */
 191 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 192 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 193
 194 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 195 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 196
 197 #define CONFIG_FLASH_16BIT
 198
 199 /*-----------------------------------------------------------------------
 200  * Hard Reset Configuration Words
 201  *
 202  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 203  * defines for the various registers affected by the HRCW e.g. changing
 204  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 205  */
 206 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
 207                                  HRCW_BPS10 |\
 208                                  HRCW_APPC10)
 209
 210 /* no slaves so just fill with zeros */
 211 #define CONFIG_SYS_HRCW_SLAVE1          0
 212 #define CONFIG_SYS_HRCW_SLAVE2          0
 213 #define CONFIG_SYS_HRCW_SLAVE3          0
 214 #define CONFIG_SYS_HRCW_SLAVE4          0
 215 #define CONFIG_SYS_HRCW_SLAVE5          0
 216 #define CONFIG_SYS_HRCW_SLAVE6          0
 217 #define CONFIG_SYS_HRCW_SLAVE7          0
 218
 219 /*-----------------------------------------------------------------------
 220  * Internal Memory Mapped Register
 221  */
 222 #define CONFIG_SYS_IMMR         0xF0000000
 223
 224 /*-----------------------------------------------------------------------
 225  * Definitions for initial stack pointer and data area (in DPRAM)
 226  */
 227 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 228 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM    */
 229 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 230 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 231
 232 /*-----------------------------------------------------------------------
 233  * Start addresses for the final memory configuration
 234  * (Set up by the startup code)
 235  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 236  *
 237  * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
 238  */
 239 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 240 #define CONFIG_SYS_SDRAM_MAX_SIZE       0x08000000      /* max. 128 MB          */
 241 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 242 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor */
 243 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
 244
 245 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 246 # define CONFIG_SYS_RAMBOOT
 247 #endif
 248
 249 #define CONFIG_PCI
 250 #define CONFIG_PCI_INDIRECT_BRIDGE
 251 #define CONFIG_PCI_PNP
 252 #define CONFIG_SYS_PCI_MSTR_IO_BUS      0x00000000      /* PCI base   */
 253
 254 #if 1
 255 /* environment is in Flash */
 256 #define CONFIG_ENV_IS_IN_FLASH  1
 257 # define CONFIG_ENV_ADDR                (CONFIG_SYS_FLASH_BASE+0x30000)
 258 # define CONFIG_ENV_SIZE                0x10000
 259 # define CONFIG_ENV_SECT_SIZE   0x10000
 260 #else
 261 #define CONFIG_ENV_IS_IN_EEPROM 1
 262 #define CONFIG_ENV_OFFSET               0
 263 #define CONFIG_ENV_SIZE         2048
 264 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4       /* 16-byte page size    */
 265 #endif
 266
 267 /*-----------------------------------------------------------------------
 268  * Cache Configuration
 269  */
 270 #define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 271 #if defined(CONFIG_CMD_KGDB)
 272 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 273 #endif
 274
 275 /*-----------------------------------------------------------------------
 276  * HIDx - Hardware Implementation-dependent Registers                    2-11
 277  *-----------------------------------------------------------------------
 278  * HID0 also contains cache control - initially enable both caches and
 279  * invalidate contents, then the final state leaves only the instruction
 280  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 281  * but Soft reset does not.
 282  *
 283  * HID1 has only read-only information - nothing to set.
 284  */
 285 #define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
 286                          HID0_DCI|HID0_IFEM|HID0_ABE)
 287 #define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 288 #define CONFIG_SYS_HID2        0
 289
 290 /*-----------------------------------------------------------------------
 291  * RMR - Reset Mode Register                                     5-5
 292  *-----------------------------------------------------------------------
 293  * turn on Checkstop Reset Enable
 294  */
 295 #define CONFIG_SYS_RMR         RMR_CSRE
 296
 297 /*-----------------------------------------------------------------------
 298  * BCR - Bus Configuration                                       4-25
 299  *-----------------------------------------------------------------------
 300  */
 301 #define BCR_APD01       0x10000000
 302 #define CONFIG_SYS_BCR          (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 303
 304 /*-----------------------------------------------------------------------
 305  * SIUMCR - SIU Module Configuration                             4-31
 306  *-----------------------------------------------------------------------
 307  */
 308 #define CONFIG_SYS_SIUMCR      (SIUMCR_BBD|SIUMCR_APPC10|\
 309                          SIUMCR_CS10PC00|SIUMCR_BCTLC10)
 310
 311 /*-----------------------------------------------------------------------
 312  * SYPCR - System Protection Control                             4-35
 313  * SYPCR can only be written once after reset!
 314  *-----------------------------------------------------------------------
 315  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 316  */
 317 #if defined(CONFIG_WATCHDOG)
 318 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 319                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 320 #else
 321 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 322                          SYPCR_SWRI|SYPCR_SWP)
 323 #endif /* CONFIG_WATCHDOG */
 324
 325 /*-----------------------------------------------------------------------
 326  * TMCNTSC - Time Counter Status and Control                     4-40
 327  *-----------------------------------------------------------------------
 328  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 329  * and enable Time Counter
 330  */
 331 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 332
 333 /*-----------------------------------------------------------------------
 334  * PISCR - Periodic Interrupt Status and Control                 4-42
 335  *-----------------------------------------------------------------------
 336  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 337  * Periodic timer
 338  */
 339 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 340
 341 /*-----------------------------------------------------------------------
 342  * SCCR - System Clock Control                                   9-8
 343  *-----------------------------------------------------------------------
 344  * Ensure DFBRG is Divide by 16
 345  */
 346 #define CONFIG_SYS_SCCR        SCCR_DFBRG01
 347
 348 /*-----------------------------------------------------------------------
 349  * RCCR - RISC Controller Configuration                         13-7
 350  *-----------------------------------------------------------------------
 351  */
 352 #define CONFIG_SYS_RCCR        0
 353
 354 #define CONFIG_SYS_MIN_AM_MASK  0xC0000000
 355 /*-----------------------------------------------------------------------
 356  * MPTPR - Memory Refresh Timer Prescaler Register              10-18
 357  *-----------------------------------------------------------------------
 358  */
 359 #define CONFIG_SYS_MPTPR       0x1F00
 360
 361 /*-----------------------------------------------------------------------
 362  * PSRT - Refresh Timer Register                                10-16
 363  *-----------------------------------------------------------------------
 364  */
 365 #define CONFIG_SYS_PSRT        0x0f
 366
 367 /*-----------------------------------------------------------------------
 368  * PSRT - SDRAM Mode Register                                   10-10
 369  *-----------------------------------------------------------------------
 370  */
 371
 372         /* SDRAM initialization values for 8-column chips
 373          */
 374 #define CONFIG_SYS_OR2_8COL     (CONFIG_SYS_MIN_AM_MASK         |\
 375                          ORxS_BPD_4                     |\
 376                          ORxS_ROWST_PBI1_A7             |\
 377                          ORxS_NUMR_12)
 378
 379 #define CONFIG_SYS_PSDMR_8COL   (PSDMR_PBI                      |\
 380                          PSDMR_SDAM_A15_IS_A5           |\
 381                          PSDMR_BSMA_A15_A17             |\
 382                          PSDMR_SDA10_PBI1_A7            |\
 383                          PSDMR_RFRC_7_CLK               |\
 384                          PSDMR_PRETOACT_3W              |\
 385                          PSDMR_ACTTORW_2W               |\
 386                          PSDMR_LDOTOPRE_1C              |\
 387                          PSDMR_WRC_1C                   |\
 388                          PSDMR_CL_2)
 389
 390         /* SDRAM initialization values for 9-column chips
 391          */
 392 #define CONFIG_SYS_OR2_9COL     (CONFIG_SYS_MIN_AM_MASK         |\
 393                          ORxS_BPD_4                     |\
 394                          ORxS_ROWST_PBI1_A6             |\
 395                          ORxS_NUMR_12)
 396
 397 #define CONFIG_SYS_PSDMR_9COL   (PSDMR_PBI                      |\
 398                          PSDMR_SDAM_A16_IS_A5           |\
 399                          PSDMR_BSMA_A15_A17             |\
 400                          PSDMR_SDA10_PBI1_A6            |\
 401                          PSDMR_RFRC_7_CLK               |\
 402                          PSDMR_PRETOACT_3W              |\
 403                          PSDMR_ACTTORW_2W               |\
 404                          PSDMR_LDOTOPRE_1C              |\
 405                          PSDMR_WRC_1C                   |\
 406                          PSDMR_CL_2)
 407
 408 /*
 409  * Init Memory Controller:
 410  *
 411  * Bank Bus     Machine PortSz  Device
 412  * ---- ---     ------- ------  ------
 413  *  0   60x     GPCM    8  bit  Boot ROM
 414  *  1   60x     GPCM    64 bit  FLASH
 415  *  2   60x     SDRAM   64 bit  SDRAM
 416  *
 417  */
 418
 419 #define CONFIG_SYS_MRS_OFFS     0x00000000
 420
 421 /* Bank 0 - FLASH
 422  */
 423 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 424                          BRx_PS_16                      |\
 425                          BRx_MS_GPCM_P                  |\
 426                          BRx_V)
 427
 428 #define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
 429                          ORxG_CSNT                      |\
 430                          ORxG_ACS_DIV1                  |\
 431                          ORxG_SCY_3_CLK                 |\
 432                          ORxU_EHTR_8IDLE)
 433
 434
 435 /* Bank 2 - 60x bus SDRAM
 436  */
 437 #ifndef CONFIG_SYS_RAMBOOT
 438 #define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 439                          BRx_PS_64                      |\
 440                          BRx_MS_SDRAM_P                 |\
 441                          BRx_V)
 442
 443 #define CONFIG_SYS_OR2_PRELIM    CONFIG_SYS_OR2_8COL
 444
 445 #define CONFIG_SYS_PSDMR         CONFIG_SYS_PSDMR_8COL
 446 #endif /* CONFIG_SYS_RAMBOOT */
 447
 448 #define CONFIG_SYS_BR4_PRELIM  ((RTC_BASE_ADDR & BRx_BA_MSK)   |\
 449                          BRx_PS_8                       |\
 450                          BRx_MS_UPMA                    |\
 451                          BRx_V)
 452
 453 #define CONFIG_SYS_OR4_PRELIM  (ORxU_AM_MSK | ORxU_BI)
 454
 455 /*-----------------------------------------------------------------------
 456  * PCMCIA stuff
 457  *-----------------------------------------------------------------------
 458  *
 459  */
 460 #define CONFIG_I82365
 461
 462 #define CONFIG_SYS_PCMCIA_MEM_ADDR      0x81000000
 463 #define CONFIG_SYS_PCMCIA_MEM_SIZE      0x1000
 464
 465 /*-----------------------------------------------------------------------
 466  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 467  *-----------------------------------------------------------------------
 468  */
 469
 470 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 471 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 472
 473 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 474 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 475 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 476
 477 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 478 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 479
 480 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 481
 482 #define CONFIG_SYS_ATA_BASE_ADDR        0xa0000000
 483
 484 /* Offset for data I/O                  */
 485 #define CONFIG_SYS_ATA_DATA_OFFSET      0x100
 486
 487 /* Offset for normal register accesses  */
 488 #define CONFIG_SYS_ATA_REG_OFFSET       0x100
 489
 490 /* Offset for alternate registers       */
 491 #define CONFIG_SYS_ATA_ALT_OFFSET       0x108
 492
 493 #endif  /* __CONFIG_H */