include/configs/atngw100mkii.h

   1 /*
   2  * Copyright (C) 2006 Atmel Corporation
   3  *
   4  * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
   5  *
   6  * Configuration settings for the AVR32 Network Gateway
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 #include <asm/arch/hardware.h>
  30
  31 #define CONFIG_AVR32
  32 #define CONFIG_AT32AP
  33 #define CONFIG_AT32AP7000
  34 #define CONFIG_ATNGW100MKII
  35
  36 /*
  37  * Timer clock frequency. We're using the CPU-internal COUNT register
  38  * for this, so this is equivalent to the CPU core clock frequency
  39  */
  40 #define CONFIG_SYS_HZ                   1000
  41
  42 /*
  43  * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
  44  * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
  45  * and the PBA bus to run at 1/4 the PLL frequency.
  46  */
  47 #define CONFIG_PLL
  48 #define CONFIG_SYS_POWER_MANAGER
  49 #define CONFIG_SYS_OSC0_HZ              20000000
  50 #define CONFIG_SYS_PLL0_DIV             1
  51 #define CONFIG_SYS_PLL0_MUL             7
  52 #define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
  53 /*
  54  * Set the CPU running at:
  55  * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
  56  */
  57 #define CONFIG_SYS_CLKDIV_CPU           0
  58 /*
  59  * Set the HSB running at:
  60  * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
  61  */
  62 #define CONFIG_SYS_CLKDIV_HSB           1
  63 /*
  64  * Set the PBA running at:
  65  * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
  66  */
  67 #define CONFIG_SYS_CLKDIV_PBA           2
  68 /*
  69  * Set the PBB running at:
  70  * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
  71  */
  72 #define CONFIG_SYS_CLKDIV_PBB           1
  73
  74 /* Reserve VM regions for NOR flash, NAND flash and SDRAM */
  75 #define CONFIG_SYS_NR_VM_REGIONS        3
  76
  77 /*
  78  * The PLLOPT register controls the PLL like this:
  79  *   icp = PLLOPT<2>
  80  *   ivco = PLLOPT<1:0>
  81  *
  82  * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
  83  */
  84 #define CONFIG_SYS_PLL0_OPT             0x04
  85
  86 #define CONFIG_USART_BASE               ATMEL_BASE_USART1
  87 #define CONFIG_USART_ID                 1
  88
  89 /* User serviceable stuff */
  90 #define CONFIG_DOS_PARTITION
  91
  92 #define CONFIG_CMDLINE_TAG
  93 #define CONFIG_SETUP_MEMORY_TAGS
  94 #define CONFIG_INITRD_TAG
  95
  96 #define CONFIG_STACKSIZE                (2048)
  97
  98 #define CONFIG_BAUDRATE                 115200
  99 #define CONFIG_BOOTARGS                                                 \
 100         "root=mtd:main rootfstype=jffs2"
 101 #define CONFIG_BOOTCOMMAND                                              \
 102         "fsload 0x10400000 /uImage; bootm"
 103
 104 /*
 105  * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
 106  * data on the serial line may interrupt the boot sequence.
 107  */
 108 #define CONFIG_BOOTDELAY                1
 109 #define CONFIG_AUTOBOOT
 110 #define CONFIG_AUTOBOOT_KEYED
 111 #define CONFIG_AUTOBOOT_PROMPT          \
 112         "Press SPACE to abort autoboot in %d seconds\n", bootdelay
 113 #define CONFIG_AUTOBOOT_DELAY_STR       "d"
 114 #define CONFIG_AUTOBOOT_STOP_STR        " "
 115
 116 /*
 117  * After booting the board for the first time, new ethernet addresses
 118  * should be generated and assigned to the environment variables
 119  * "ethaddr" and "eth1addr". This is normally done during production.
 120  */
 121 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 122 #define CONFIG_NET_MULTI
 123
 124 /*
 125  * BOOTP/DHCP options
 126  */
 127 #define CONFIG_BOOTP_SUBNETMASK
 128 #define CONFIG_BOOTP_GATEWAY
 129
 130 /*
 131  * Command line configuration.
 132  */
 133 #include <config_cmd_default.h>
 134
 135 #define CONFIG_CMD_ASKENV
 136 #define CONFIG_CMD_DHCP
 137 #define CONFIG_CMD_EXT2
 138 #define CONFIG_CMD_FAT
 139 #define CONFIG_CMD_JFFS2
 140 #define CONFIG_CMD_MMC
 141 #define CONFIG_CMD_SF
 142 #define CONFIG_CMD_SPI
 143 #define CONFIG_CMD_MII
 144
 145 #undef CONFIG_CMD_FPGA
 146 #undef CONFIG_CMD_SETGETDCR
 147 #undef CONFIG_CMD_XIMG
 148
 149 #define CONFIG_ATMEL_USART
 150 #define CONFIG_MACB
 151 #define CONFIG_PORTMUX_PIO
 152 #define CONFIG_SYS_NR_PIOS              5
 153 #define CONFIG_SYS_HSDRAMC
 154 #define CONFIG_MMC
 155 #define CONFIG_GENERIC_ATMEL_MCI
 156 #define CONFIG_GENERIC_MMC
 157 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 1
 158 #define CONFIG_ATMEL_SPI
 159
 160 #define CONFIG_SPI_FLASH
 161 #define CONFIG_SPI_FLASH_ATMEL
 162
 163 #define CONFIG_SYS_DCACHE_LINESZ        32
 164 #define CONFIG_SYS_ICACHE_LINESZ        32
 165
 166 #define CONFIG_NR_DRAM_BANKS            1
 167
 168 #define CONFIG_SYS_FLASH_CFI
 169 #define CONFIG_FLASH_CFI_DRIVER
 170 #define CONFIG_SYS_FLASH_PROTECTION
 171
 172 #define CONFIG_SYS_FLASH_BASE           0x00000000
 173 #define CONFIG_SYS_FLASH_SIZE           0x800000
 174 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 175 #define CONFIG_SYS_MAX_FLASH_SECT       135
 176
 177 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 178
 179 #define CONFIG_SYS_INTRAM_BASE          INTERNAL_SRAM_BASE
 180 #define CONFIG_SYS_INTRAM_SIZE          INTERNAL_SRAM_SIZE
 181 #define CONFIG_SYS_SDRAM_BASE           EBI_SDRAM_BASE
 182
 183 #define CONFIG_ENV_IS_IN_FLASH
 184 #define CONFIG_ENV_SIZE                 65536
 185 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
 186
 187 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
 188
 189 #define CONFIG_SYS_MALLOC_LEN           (256*1024)
 190 #define CONFIG_SYS_DMA_ALLOC_LEN        (16384)
 191
 192 /* Allow 4MB for the kernel run-time image */
 193 #define CONFIG_SYS_LOAD_ADDR            (EBI_SDRAM_BASE + 0x00400000)
 194 #define CONFIG_SYS_BOOTPARAMS_LEN       (16 * 1024)
 195
 196 /* Other configuration settings that shouldn't have to change all that often */
 197 #define CONFIG_SYS_PROMPT               "U-Boot> "
 198 #define CONFIG_SYS_CBSIZE               256
 199 #define CONFIG_SYS_MAXARGS              16
 200 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 201 #define CONFIG_SYS_LONGHELP
 202
 203 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
 204 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + 0x1f00000)
 205
 206 #define CONFIG_MTD_DEVICE
 207 #define CONFIG_MTD_PARTITIONS
 208
 209 #endif /* __CONFIG_H */