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git.ipfire.org Git - thirdparty/u-boot.git/blob - include/configs/ax25-ae350.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2017 Andes Technology Corporation
4 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
11 #define CONFIG_SPL_MAX_SIZE 0x00100000
12 #define CONFIG_SPL_BSS_START_ADDR 0x04000000
13 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
16 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb"
20 #define RISCV_MMODE_TIMERBASE 0xe6000000
21 #define RISCV_MMODE_TIMER_FREQ 60000000
23 #define RISCV_SMODE_TIMER_FREQ 60000000
26 * CPU and Board Configuration Options
30 * Miscellaneous configurable options
32 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
37 #define CONFIG_SYS_PBSIZE \
38 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
41 * Boot Argument Buffer Size
43 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
45 /* DT blob (fdt) address */
46 #define CONFIG_SYS_FDT_BASE 0x800f0000
51 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
52 #define PHYS_SDRAM_1 \
53 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
54 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
55 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
56 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
59 * Serial console configuration
61 #define CONFIG_SYS_NS16550_SERIAL
62 #ifndef CONFIG_DM_SERIAL
63 #define CONFIG_SYS_NS16550_REG_SIZE -4
65 #define CONFIG_SYS_NS16550_CLK 19660800
67 /* Init Stack Pointer */
68 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \
69 GENERATED_GBL_DATA_SIZE)
71 /* use CFI framework */
73 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
74 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
77 #define PHYS_FLASH_1 0x88000000 /* BANK 0 */
78 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
79 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
81 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
82 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
84 /* max number of memory banks */
86 * There are 4 banks supported for this Controller,
87 * but we have only 1 bank connected to flash on board
89 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
91 /* max number of sectors on one chip */
92 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
93 #define CONFIG_SYS_MAX_FLASH_SECT 512
100 * For booting Linux, the board info and command line data
101 * have to be in the first 16 MB of memory, since this is
102 * the maximum mapped by the Linux kernel during initialization.
105 /* Initial Memory map for Linux*/
106 #define CONFIG_SYS_BOOTMAPSZ (64 << 20)
107 /* Increase max gunzip size */
108 #define CONFIG_SYS_BOOTM_LEN (64 << 20)
110 /* Support autoboot from RAM (kernel image is loaded via debug port) */
111 #define KERNEL_IMAGE_ADDR "0x2000000 "
112 #define BOOTENV_DEV_NAME_RAM(devtypeu, devtypel, instance) \
114 #define BOOTENV_DEV_RAM(devtypeu, devtypel, instance) \
118 "- $fdtcontroladdr\0"
120 /* When we use RAM as ENV */
122 /* Enable distro boot */
123 #define BOOT_TARGET_DEVICES(func) \
125 func(DHCP, dhcp, na) \
127 #include <config_distro_bootcmd.h>
129 #define CONFIG_EXTRA_ENV_SETTINGS \
130 "kernel_addr_r=0x00080000\0" \
131 "pxefile_addr_r=0x01f00000\0" \
132 "scriptaddr=0x01f00000\0" \
133 "fdt_addr_r=0x02000000\0" \
134 "ramdisk_addr_r=0x02800000\0" \
137 #endif /* __CONFIG_H */