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[people/ms/u-boot.git] / include / configs / bf533-ezkit.h
1 /*
2 * U-boot - Configuration file for BF533 EZKIT board
3 */
4
5 #ifndef __CONFIG_BF533_EZKIT_H__
6 #define __CONFIG_BF533_EZKIT_H__
7
8 #include <asm/config-pre.h>
9
10
11 /*
12 * Processor Settings
13 */
14 #define CONFIG_BFIN_CPU bf533-0.3
15 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
16
17
18 /*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23 /* CONFIG_CLKIN_HZ is any value in Hz */
24 #define CONFIG_CLKIN_HZ 27000000
25 /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26 /* 1 = CLKIN / 2 */
27 #define CONFIG_CLKIN_HALF 0
28 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29 /* 1 = bypass PLL */
30 #define CONFIG_PLL_BYPASS 0
31 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32 /* Values can range from 0-63 (where 0 means 64) */
33 #define CONFIG_VCO_MULT 22
34 /* CCLK_DIV controls the core clock divider */
35 /* Values can be 1, 2, 4, or 8 ONLY */
36 #define CONFIG_CCLK_DIV 1
37 /* SCLK_DIV controls the system clock divider */
38 /* Values can range from 1-15 */
39 #define CONFIG_SCLK_DIV 5
40
41
42 /*
43 * Memory Settings
44 */
45 #define CONFIG_MEM_SIZE 32
46 /* Early EZKITs had 32megs, but later have 64megs */
47 #if (CONFIG_MEM_SIZE == 64)
48 # define CONFIG_MEM_ADD_WDTH 10
49 #else
50 # define CONFIG_MEM_ADD_WDTH 9
51 #endif
52
53 #define CONFIG_EBIU_SDRRC_VAL 0x398
54 #define CONFIG_EBIU_SDGCTL_VAL 0x91118d
55
56 #define CONFIG_EBIU_AMGCTL_VAL 0xFF
57 #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
58 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
59
60 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
61 #define CONFIG_SYS_MALLOC_LEN (128 * 1024)
62
63
64 /*
65 * Network Settings
66 */
67 #define ADI_CMDS_NETWORK 1
68 #define CONFIG_NET_MULTI
69 #define CONFIG_SMC91111 1
70 #define CONFIG_SMC91111_BASE 0x20310300
71 #define SMC91111_EEPROM_INIT() \
72 do { \
73 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
74 bfin_write_FIO_FLAG_C(PF1); \
75 bfin_write_FIO_FLAG_S(PF0); \
76 SSYNC(); \
77 } while (0)
78 #define CONFIG_HOSTNAME bf533-ezkit
79 /* Uncomment next line to use fixed MAC address */
80 /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
81
82
83 /*
84 * Flash Settings
85 */
86 #define CONFIG_SYS_FLASH_BASE 0x20000000
87 #define CONFIG_SYS_MAX_FLASH_BANKS 3
88 #define CONFIG_SYS_MAX_FLASH_SECT 40
89 #define CONFIG_ENV_IS_IN_FLASH
90 #define CONFIG_ENV_ADDR 0x20030000
91 #define CONFIG_ENV_SECT_SIZE 0x10000
92 #define FLASH_TOT_SECT 40
93
94
95 /*
96 * I2C Settings
97 * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
98 */
99 #define CONFIG_SOFT_I2C
100 #ifdef CONFIG_SOFT_I2C
101 #define PF_SCL PF0
102 #define PF_SDA PF1
103 #define I2C_INIT \
104 do { \
105 *pFIO_DIR |= PF_SCL; \
106 SSYNC(); \
107 } while (0)
108 #define I2C_ACTIVE \
109 do { \
110 *pFIO_DIR |= PF_SDA; \
111 *pFIO_INEN &= ~PF_SDA; \
112 SSYNC(); \
113 } while (0)
114 #define I2C_TRISTATE \
115 do { \
116 *pFIO_DIR &= ~PF_SDA; \
117 *pFIO_INEN |= PF_SDA; \
118 SSYNC(); \
119 } while (0)
120 #define I2C_READ ((*pFIO_FLAG_D & PF_SDA) != 0)
121 #define I2C_SDA(bit) \
122 do { \
123 if (bit) \
124 *pFIO_FLAG_S = PF_SDA; \
125 else \
126 *pFIO_FLAG_C = PF_SDA; \
127 SSYNC(); \
128 } while (0)
129 #define I2C_SCL(bit) \
130 do { \
131 if (bit) \
132 *pFIO_FLAG_S = PF_SCL; \
133 else \
134 *pFIO_FLAG_C = PF_SCL; \
135 SSYNC(); \
136 } while (0)
137 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
138
139 #endif
140
141
142 /*
143 * Misc Settings
144 */
145 #define CONFIG_MISC_INIT_R
146 #define CONFIG_RTC_BFIN
147 #define CONFIG_UART_CONSOLE 0
148
149
150 /*
151 * Pull in common ADI header for remaining command/environment setup
152 */
153 #include <configs/bfin_adi_common.h>
154
155 #endif