include/configs/bf533-ezkit.h

   1 /*
   2  * U-boot - Configuration file for BF533 EZKIT board
   3  */
   4
   5 #ifndef __CONFIG_EZKIT533_H__
   6 #define __CONFIG_EZKIT533_H__
   7
   8 #define CONFIG_BAUDRATE         57600
   9 #define CONFIG_STAMP            1
  10
  11 #define CONFIG_BOOTDELAY        5
  12 #define CFG_AUTOLOAD            "no"    /*rarpb, bootp or dhcp commands will perform only a */
  13
  14 #define CFG_LONGHELP            1
  15 #define CONFIG_CMDLINE_EDITING  1
  16 #define CONFIG_LOADADDR         0x01000000      /* default load address */
  17 #define CONFIG_BOOTCOMMAND      "tftp $(loadaddr) linux"
  18 /* #define CONFIG_BOOTARGS              "root=/dev/mtdblock0 rw" */
  19
  20 #define CONFIG_DRIVER_SMC91111  1
  21 #define CONFIG_SMC91111_BASE    0x20310300
  22
  23 #if 0
  24 #define CONFIG_MII
  25 #define CFG_DISCOVER_PHY
  26 #endif
  27
  28 #define CONFIG_RTC_BFIN         1
  29 #define CONFIG_BOOT_RETRY_TIME  -1      /* Enable this if bootretry required, currently its disabled */
  30
  31 /*
  32  * Boot Mode Set
  33  * Blackfin can support several boot modes
  34  */
  35 #define BF533_BYPASS_BOOT       0x0001  /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
  36 #define BF533_PARA_BOOT         0x0002  /* Bootmode 1: Boot from 8-bit or 16-bit flash */
  37 #define BF533_SPI_BOOT          0x0004  /* Bootmode 3: Boot from SPI flash */
  38 /* Define the boot mode */
  39 #define BFIN_BOOT_MODE          BF533_BYPASS_BOOT
  40 /* #define BFIN_BOOT_MODE       BF533_SPI_BOOT */
  41
  42 #define CONFIG_PANIC_HANG 1
  43
  44 #define ADSP_BF531              0x31
  45 #define ADSP_BF532              0x32
  46 #define ADSP_BF533              0x33
  47 #define BFIN_CPU                ADSP_BF533
  48
  49 /* This sets the default state of the cache on U-Boot's boot */
  50 #define CONFIG_ICACHE_ON
  51 #define CONFIG_DCACHE_ON
  52
  53 /* Define where the uboot will be loaded by on-chip boot rom */
  54 #define APP_ENTRY 0x00001000
  55
  56 /* CONFIG_CLKIN_HZ is any value in Hz                           */
  57 #define CONFIG_CLKIN_HZ         27000000
  58 /* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN     */
  59 /*                                                  1=CLKIN/2   */
  60 #define CONFIG_CLKIN_HALF       0
  61 /* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
  62 /*                                               1=bypass PLL   */
  63 #define CONFIG_PLL_BYPASS       0
  64 /* CONFIG_VCO_MULT controls what the multiplier of the PLL is.  */
  65 /* Values can range from 1-64                                   */
  66 #define CONFIG_VCO_MULT         22
  67 /* CONFIG_CCLK_DIV controls what the core clock divider is      */
  68 /* Values can be 1, 2, 4, or 8 ONLY                             */
  69 #define CONFIG_CCLK_DIV         1
  70 /* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
  71 /* Values can range from 1-15                                   */
  72 #define CONFIG_SCLK_DIV         5
  73 /* CONFIG_SPI_BAUD controls the SPI peripheral clock divider    */
  74 /* Values can range from 2-65535                                */
  75 /* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)                 */
  76 #define CONFIG_SPI_BAUD         2
  77 #define CONFIG_SPI_BAUD_INITBLOCK       4
  78
  79 #if ( CONFIG_CLKIN_HALF == 0 )
  80 #define CONFIG_VCO_HZ           ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
  81 #else
  82 #define CONFIG_VCO_HZ           (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
  83 #endif
  84
  85 #if (CONFIG_PLL_BYPASS == 0)
  86 #define CONFIG_CCLK_HZ          ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
  87 #define CONFIG_SCLK_HZ          ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
  88 #else
  89 #define CONFIG_CCLK_HZ          CONFIG_CLKIN_HZ
  90 #define CONFIG_SCLK_HZ          CONFIG_CLKIN_HZ
  91 #endif
  92
  93 #define CONFIG_MEM_SIZE         32      /* 128, 64, 32, 16 */
  94 #define CONFIG_MEM_ADD_WDTH     9       /* 8, 9, 10, 11    */
  95 #define CONFIG_MEM_MT48LC16M16A2TG_75   1
  96
  97 #define CONFIG_LOADS_ECHO       1
  98
  99
 100 /*
 101  * Command line configuration.
 102  */
 103 #include <config_cmd_default.h>
 104
 105 #define CONFIG_CMD_PING
 106 #define CONFIG_CMD_ELF
 107 #define CONFIG_CMD_I2C
 108 #define CONFIG_CMD_JFFS2
 109 #define CONFIG_CMD_DATE
 110
 111
 112 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600"
 113
 114 #define CFG_PROMPT              "ezkit> "       /* Monitor Command Prompt */
 115 #if defined(CONFIG_CMD_KGDB)
 116 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size */
 117 #else
 118 #define CFG_CBSIZE              256     /* Console I/O Buffer Size */
 119 #endif
 120 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)      /* Print Buffer Size */
 121 #define CFG_MAXARGS             16      /* max number of command args */
 122 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size */
 123 #define CFG_MEMTEST_START       0x00000000      /* memtest works on */
 124 #define CFG_MEMTEST_END         ( (CONFIG_MEM_SIZE - 1) * 1024 * 1024)  /* 1 ... 31 MB in DRAM */
 125 #define CFG_LOAD_ADDR           0x01000000      /* default load address */
 126 #define CFG_HZ                  1000    /* decrementer freq: 10 ms ticks */
 127 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 128 #define CFG_SDRAM_BASE          0x00000000
 129 #define CFG_MAX_RAM_SIZE        (CONFIG_MEM_SIZE * 1024 * 1024)
 130 #define CFG_FLASH_BASE          0x20000000
 131
 132 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 133 #define CFG_MONITOR_BASE        (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
 134 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 135 #define CFG_MALLOC_BASE         (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
 136 #define CFG_GBL_DATA_SIZE       0x4000
 137 #define CFG_GBL_DATA_ADDR       (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
 138 #define CONFIG_STACKBASE        (CFG_GBL_DATA_ADDR  - 4)
 139
 140 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 141 #define CFG_FLASH0_BASE         0x20000000
 142 #define CFG_FLASH1_BASE         0x20200000
 143 #define CFG_FLASH2_BASE         0x20280000
 144 #define CFG_MAX_FLASH_BANKS     3       /* max number of memory banks */
 145 #define CFG_MAX_FLASH_SECT      40      /* max number of sectors on one chip */
 146
 147 #define CFG_ENV_IS_IN_FLASH     1
 148 #define CFG_ENV_ADDR            0x20020000
 149 #define CFG_ENV_SECT_SIZE       0x10000 /* Total Size of Environment Sector */
 150
 151 /* JFFS Partition offset set  */
 152 #define CFG_JFFS2_FIRST_BANK    0
 153 #define CFG_JFFS2_NUM_BANKS     1
 154 /* 512k reserved for u-boot */
 155 #define CFG_JFFS2_FIRST_SECTOR  11
 156
 157
 158 /*
 159  * Stack sizes
 160  */
 161 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 162
 163 #define POLL_MODE               1
 164 #define FLASH_TOT_SECT          40
 165 #define FLASH_SIZE              0x220000
 166 #define CFG_FLASH_SIZE          0x220000
 167
 168 /*
 169  * Initialize PSD4256 registers for using I2C
 170  */
 171 #define CONFIG_MISC_INIT_R
 172
 173 /*
 174  * I2C settings
 175  * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
 176  */
 177 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged */
 178 /*
 179  * Software (bit-bang) I2C driver configuration
 180  */
 181 #define PF_SCL                  PF0
 182 #define PF_SDA                  PF1
 183
 184 #define I2C_INIT                (*pFIO_DIR |=  PF_SCL); asm("ssync;")
 185 #define I2C_ACTIVE              (*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
 186 #define I2C_TRISTATE            (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
 187 #define I2C_READ                ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
 188 #define I2C_SDA(bit)    if(bit) { \
 189                                 *pFIO_FLAG_S = PF_SDA; \
 190                                 asm("ssync;"); \
 191                                 } \
 192                         else    { \
 193                                 *pFIO_FLAG_C = PF_SDA; \
 194                                 asm("ssync;"); \
 195                                 }
 196 #define I2C_SCL(bit)    if(bit) { \
 197                                 *pFIO_FLAG_S = PF_SCL; \
 198                                 asm("ssync;"); \
 199                                 } \
 200                         else    { \
 201                                 *pFIO_FLAG_C = PF_SCL; \
 202                                 asm("ssync;"); \
 203                                 }
 204 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 205
 206 #define CFG_I2C_SPEED           50000
 207 #define CFG_I2C_SLAVE           0xFE
 208
 209 #define CFG_BOOTM_LEN           0x4000000       /* Large Image Length, set to 64 Meg */
 210
 211 /* 0xFF, 0x7BB07BB0, 0x22547BB0 */
 212 /* #define AMGCTLVAL            (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
 213 #define AMBCTL0VAL              (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
 214                                 ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
 215 #define AMBCTL1VAL              (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
 216                                 B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
 217 */
 218 #define AMGCTLVAL               0xFF
 219 #define AMBCTL0VAL              0x7BB07BB0
 220 #define AMBCTL1VAL              0xFFC27BB0
 221
 222 #define CONFIG_VDSP             1
 223
 224 #ifdef CONFIG_VDSP
 225 #define ET_EXEC_VDSP            0x8
 226 #define SHT_STRTAB_VDSP         0x1
 227 #define ELFSHDRSIZE_VDSP        0x2C
 228 #define VDSP_ENTRY_ADDR         0xFFA00000
 229 #endif
 230
 231 #endif