include/configs/bf537-pnav.h

   1 /*
   2  * U-Boot - Configuration file for BF537 PNAV board
   3  */
   4
   5 #ifndef __CONFIG_BF537_PNAV_H__
   6 #define __CONFIG_BF537_PNAV_H__
   7
   8 #include <asm/config-pre.h>
   9
  10
  11 /*
  12  * Processor Settings
  13  */
  14 #define CONFIG_BFIN_CPU             bf537-0.2
  15 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
  16
  17
  18 /*
  19  * Clock Settings
  20  *      CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
  21  *      SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
  22  */
  23 /* CONFIG_CLKIN_HZ is any value in Hz                                   */
  24 #define CONFIG_CLKIN_HZ                 24576000
  25 /* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN             */
  26 /*                                                1 = CLKIN / 2         */
  27 #define CONFIG_CLKIN_HALF               0
  28 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass     */
  29 /*                                                1 = bypass PLL        */
  30 #define CONFIG_PLL_BYPASS               0
  31 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL              */
  32 /* Values can range from 0-63 (where 0 means 64)                        */
  33 #define CONFIG_VCO_MULT                 20
  34 /* CCLK_DIV controls the core clock divider                             */
  35 /* Values can be 1, 2, 4, or 8 ONLY                                     */
  36 #define CONFIG_CCLK_DIV                 1
  37 /* SCLK_DIV controls the system clock divider                           */
  38 /* Values can range from 1-15                                           */
  39 #define CONFIG_SCLK_DIV                 4
  40
  41
  42 /*
  43  * Memory Settings
  44  */
  45 #define CONFIG_MEM_ADD_WDTH     10
  46 #define CONFIG_MEM_SIZE         64
  47
  48 #define CONFIG_EBIU_SDRRC_VAL   0x3b7
  49 #define CONFIG_EBIU_SDGCTL_VAL  0x9111cd
  50
  51 #define CONFIG_EBIU_AMGCTL_VAL  0xFF
  52 #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB033B0
  53 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
  54
  55 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
  56 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)
  57
  58
  59 /*
  60  * Network Settings
  61  */
  62 #ifndef __ADSPBF534__
  63 #define ADI_CMDS_NETWORK        1
  64 #define CONFIG_BFIN_MAC
  65 #define CONFIG_RMII
  66 #endif
  67 #define CONFIG_HOSTNAME         bf537-pnav
  68
  69 /*
  70  * Flash Settings
  71  */
  72 #define CONFIG_FLASH_CFI_DRIVER
  73 #define CONFIG_SYS_FLASH_BASE           0x20000000
  74 #define CONFIG_SYS_FLASH_CFI
  75 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  76 #define CONFIG_SYS_MAX_FLASH_SECT       71
  77
  78
  79 /*
  80  * SPI Settings
  81  */
  82 #define CONFIG_BFIN_SPI
  83 #define CONFIG_ENV_SPI_MAX_HZ   30000000
  84 #define CONFIG_SF_DEFAULT_SPEED 30000000
  85
  86
  87 /*
  88  * Env Storage Settings
  89  */
  90 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
  91 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
  92 #define CONFIG_ENV_IS_IN_SPI_FLASH
  93 #define CONFIG_ENV_OFFSET       0x4000
  94 #else
  95 #define ENV_IS_EMBEDDED
  96 #define CONFIG_ENV_IS_IN_FLASH  1
  97 #define CONFIG_ENV_ADDR         0x20004000
  98 #define CONFIG_ENV_OFFSET       0x4000
  99 #endif
 100 #define CONFIG_ENV_SIZE         0x1000
 101 #define CONFIG_ENV_SECT_SIZE    0x2000
 102 #ifdef ENV_IS_EMBEDDED
 103 /* WARNING - the following is hand-optimized to fit within
 104  * the sector before the environment sector. If it throws
 105  * an error during compilation remove an object here to get
 106  * it linked after the configuration sector.
 107  */
 108 # define LDS_BOARD_TEXT \
 109         arch/blackfin/lib/built-in.o (.text*); \
 110         arch/blackfin/cpu/built-in.o (.text*); \
 111         . = DEFINED(env_offset) ? env_offset : .; \
 112         common/env_embedded.o (.text*);
 113 #endif
 114
 115
 116 /*
 117  * NAND Settings
 118  */
 119 #define CONFIG_NAND_PLAT
 120
 121 #define CONFIG_SYS_NAND_BASE            0x20100000
 122 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 123
 124 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
 125 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
 126 #define BFIN_NAND_WRITE(addr, cmd) \
 127         do { \
 128                 bfin_write8(addr, cmd); \
 129                 SSYNC(); \
 130         } while (0)
 131
 132 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 133 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
 134 #define NAND_PLAT_GPIO_DEV_READY       GPIO_PF12
 135
 136
 137 /*
 138  * I2C settings
 139  */
 140 #define CONFIG_SYS_I2C
 141 #define CONFIG_SYS_I2C_ADI
 142
 143
 144 /*
 145  * Misc Settings
 146  */
 147 #define CONFIG_BAUDRATE         115200
 148 #define CONFIG_RTC_BFIN
 149 #define CONFIG_UART_CONSOLE     0
 150
 151 /* JFFS Partition offset set  */
 152 #define CONFIG_SYS_JFFS2_FIRST_BANK     0
 153 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 154 /* 512k reserved for u-boot */
 155 #define CONFIG_SYS_JFFS2_FIRST_SECTOR   15
 156
 157 #define CONFIG_BOOTCOMMAND      "run nandboot"
 158 #define CONFIG_BOOTARGS_ROOT    "/dev/mtdblock1 rw rootfstype=yaffs"
 159
 160
 161 /*
 162  * Pull in common ADI header for remaining command/environment setup
 163  */
 164 #include <configs/bfin_adi_common.h>
 165
 166 #endif