include/configs/bf537-pnav.h

   1 /*
   2  * U-boot - Configuration file for BF537 PNAV board
   3  */
   4
   5 #ifndef __CONFIG_BF537_PNAV_H__
   6 #define __CONFIG_BF537_PNAV_H__
   7
   8 #include <asm/config-pre.h>
   9
  10
  11 /*
  12  * Processor Settings
  13  */
  14 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
  15
  16
  17 /*
  18  * Clock Settings
  19  *      CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
  20  *      SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
  21  */
  22 /* CONFIG_CLKIN_HZ is any value in Hz                                   */
  23 #define CONFIG_CLKIN_HZ                 24576000
  24 /* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN             */
  25 /*                                                1 = CLKIN / 2         */
  26 #define CONFIG_CLKIN_HALF               0
  27 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass     */
  28 /*                                                1 = bypass PLL        */
  29 #define CONFIG_PLL_BYPASS               0
  30 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL              */
  31 /* Values can range from 0-63 (where 0 means 64)                        */
  32 #define CONFIG_VCO_MULT                 20
  33 /* CCLK_DIV controls the core clock divider                             */
  34 /* Values can be 1, 2, 4, or 8 ONLY                                     */
  35 #define CONFIG_CCLK_DIV                 1
  36 /* SCLK_DIV controls the system clock divider                           */
  37 /* Values can range from 1-15                                           */
  38 #define CONFIG_SCLK_DIV                 4
  39
  40
  41 /*
  42  * Memory Settings
  43  */
  44 #define CONFIG_MEM_ADD_WDTH     10
  45 #define CONFIG_MEM_SIZE         64
  46
  47 #define CONFIG_EBIU_SDRRC_VAL   0x3b7
  48 #define CONFIG_EBIU_SDGCTL_VAL  0x9111cd
  49
  50 #define CONFIG_EBIU_AMGCTL_VAL  0xFF
  51 #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB033B0
  52 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
  53
  54 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
  55 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)
  56
  57
  58 /*
  59  * Network Settings
  60  */
  61 #ifndef __ADSPBF534__
  62 #define ADI_CMDS_NETWORK        1
  63 #define CONFIG_BFIN_MAC
  64 #define CONFIG_RMII
  65 #define CONFIG_NET_MULTI        1
  66 #endif
  67 #define CONFIG_HOSTNAME         bf537-pnav
  68 /* Uncomment next line to use fixed MAC address */
  69 /* #define CONFIG_ETHADDR       02:80:ad:24:21:18 */
  70
  71
  72 /*
  73  * Flash Settings
  74  */
  75 #define CONFIG_FLASH_CFI_DRIVER
  76 #define CONFIG_SYS_FLASH_BASE           0x20000000
  77 #define CONFIG_SYS_FLASH_CFI
  78 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  79 #define CONFIG_SYS_MAX_FLASH_SECT       71
  80
  81
  82 /*
  83  * SPI Settings
  84  */
  85 #define CONFIG_BFIN_SPI
  86 #define CONFIG_ENV_SPI_MAX_HZ   30000000
  87 #define CONFIG_SF_DEFAULT_SPEED 30000000
  88 #define CONFIG_SPI_FLASH
  89 #define CONFIG_SPI_FLASH_STMICRO
  90
  91
  92 /*
  93  * Env Storage Settings
  94  */
  95 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
  96 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
  97 #define CONFIG_ENV_IS_IN_SPI_FLASH
  98 #define CONFIG_ENV_OFFSET       0x4000
  99 #else
 100 #define ENV_IS_EMBEDDED
 101 #define CONFIG_ENV_IS_IN_FLASH  1
 102 #define CONFIG_ENV_ADDR         0x20004000
 103 #define CONFIG_ENV_OFFSET       0x4000
 104 #endif
 105 #define CONFIG_ENV_SIZE         0x1000
 106 #define CONFIG_ENV_SECT_SIZE    0x2000
 107 #ifdef ENV_IS_EMBEDDED
 108 /* WARNING - the following is hand-optimized to fit within
 109  * the sector before the environment sector. If it throws
 110  * an error during compilation remove an object here to get
 111  * it linked after the configuration sector.
 112  */
 113 # define LDS_BOARD_TEXT \
 114         arch/blackfin/cpu/traps.o               (.text .text.*); \
 115         arch/blackfin/cpu/interrupt.o   (.text .text.*); \
 116         arch/blackfin/cpu/serial.o              (.text .text.*); \
 117         common/dlmalloc.o               (.text .text.*); \
 118         lib/crc32.o             (.text .text.*); \
 119         . = DEFINED(env_offset) ? env_offset : .; \
 120         common/env_embedded.o           (.text .text.*);
 121 #endif
 122
 123
 124 /*
 125  * NAND Settings
 126  */
 127 #define CONFIG_NAND_PLAT
 128
 129 #define CONFIG_SYS_NAND_BASE            0x20100000
 130 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 131
 132 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
 133 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
 134 #define BFIN_NAND_WRITE(addr, cmd) \
 135         do { \
 136                 bfin_write8(addr, cmd); \
 137                 SSYNC(); \
 138         } while (0)
 139
 140 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 141 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
 142 #define NAND_PLAT_GPIO_DEV_READY       GPIO_PF12
 143
 144
 145 /*
 146  * I2C settings
 147  */
 148 #define CONFIG_BFIN_TWI_I2C     1
 149 #define CONFIG_HARD_I2C         1
 150
 151
 152 /*
 153  * Misc Settings
 154  */
 155 #define CONFIG_BAUDRATE         115200
 156 #define CONFIG_MISC_INIT_R
 157 #define CONFIG_RTC_BFIN
 158 #define CONFIG_UART_CONSOLE     0
 159
 160 /* JFFS Partition offset set  */
 161 #define CONFIG_SYS_JFFS2_FIRST_BANK     0
 162 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 163 /* 512k reserved for u-boot */
 164 #define CONFIG_SYS_JFFS2_FIRST_SECTOR   15
 165
 166 #define CONFIG_BOOTCOMMAND      "run nandboot"
 167 #define CONFIG_BOOTARGS_ROOT    "/dev/mtdblock1 rw rootfstype=yaffs"
 168
 169
 170 /*
 171  * Pull in common ADI header for remaining command/environment setup
 172  */
 173 #include <configs/bfin_adi_common.h>
 174
 175 #endif