include/configs/bf537-stamp.h

   1 /*
   2  * U-boot - Configuration file for BF537 STAMP board
   3  */
   4
   5 #ifndef __CONFIG_BF537_STAMP_H__
   6 #define __CONFIG_BF537_STAMP_H__
   7
   8 #include <asm/config-pre.h>
   9
  10
  11 /*
  12  * Processor Settings
  13  */
  14 #define CONFIG_BFIN_CPU             bf537-0.2
  15 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
  16
  17
  18 /*
  19  * Clock Settings
  20  *      CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
  21  *      SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
  22  */
  23 /* CONFIG_CLKIN_HZ is any value in Hz                                   */
  24 #define CONFIG_CLKIN_HZ                 25000000
  25 /* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN             */
  26 /*                                                1 = CLKIN / 2         */
  27 #define CONFIG_CLKIN_HALF               0
  28 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass     */
  29 /*                                                1 = bypass PLL        */
  30 #define CONFIG_PLL_BYPASS               0
  31 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL              */
  32 /* Values can range from 0-63 (where 0 means 64)                        */
  33 #define CONFIG_VCO_MULT                 20
  34 /* CCLK_DIV controls the core clock divider                             */
  35 /* Values can be 1, 2, 4, or 8 ONLY                                     */
  36 #define CONFIG_CCLK_DIV                 1
  37 /* SCLK_DIV controls the system clock divider                           */
  38 /* Values can range from 1-15                                           */
  39 #define CONFIG_SCLK_DIV                 4
  40
  41
  42 /*
  43  * Memory Settings
  44  */
  45 #define CONFIG_MEM_ADD_WDTH     10
  46 #define CONFIG_MEM_SIZE         64
  47
  48 #define CONFIG_EBIU_SDRRC_VAL   0x306
  49 #define CONFIG_EBIU_SDGCTL_VAL  0x91114d
  50
  51 #define CONFIG_EBIU_AMGCTL_VAL  0xFF
  52 #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
  53 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
  54
  55 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  56 #define CONFIG_SYS_MALLOC_LEN           (384 * 1024)
  57
  58
  59 /*
  60  * Network Settings
  61  */
  62 #ifndef __ADSPBF534__
  63 #define ADI_CMDS_NETWORK        1
  64 #define CONFIG_BFIN_MAC
  65 #define CONFIG_NETCONSOLE       1
  66 #endif
  67 #define CONFIG_HOSTNAME         bf537-stamp
  68 /* Uncomment next line to use fixed MAC address */
  69 /* #define CONFIG_ETHADDR       02:80:ad:20:31:e8 */
  70
  71
  72 /*
  73  * Flash Settings
  74  */
  75 #define CONFIG_FLASH_CFI_DRIVER
  76 #define CONFIG_SYS_FLASH_BASE           0x20000000
  77 #define CONFIG_SYS_FLASH_CFI
  78 #define CONFIG_SYS_FLASH_PROTECTION
  79 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  80 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
  81 #define CONFIG_SYS_MAX_FLASH_SECT       71
  82
  83
  84 /*
  85  * SPI Settings
  86  */
  87 #define CONFIG_BFIN_SPI
  88 #define CONFIG_ENV_SPI_MAX_HZ   30000000
  89 #define CONFIG_SF_DEFAULT_SPEED 30000000
  90 #define CONFIG_SPI_FLASH
  91 #define CONFIG_SPI_FLASH_ALL
  92
  93
  94 /*
  95  * Env Storage Settings
  96  */
  97 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
  98 #define CONFIG_ENV_IS_IN_SPI_FLASH
  99 #define CONFIG_ENV_OFFSET       0x10000
 100 #define CONFIG_ENV_SIZE         0x2000
 101 #define CONFIG_ENV_SECT_SIZE    0x10000
 102 #else
 103 #define CONFIG_ENV_IS_IN_FLASH
 104 #define CONFIG_ENV_OFFSET       0x4000
 105 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 106 #define CONFIG_ENV_SIZE         0x2000
 107 #define CONFIG_ENV_SECT_SIZE    0x2000
 108 #endif
 109 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
 110 #define ENV_IS_EMBEDDED
 111 #else
 112 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 113 #endif
 114 #ifdef ENV_IS_EMBEDDED
 115 /* WARNING - the following is hand-optimized to fit within
 116  * the sector before the environment sector. If it throws
 117  * an error during compilation remove an object here to get
 118  * it linked after the configuration sector.
 119  */
 120 # define LDS_BOARD_TEXT \
 121         arch/blackfin/lib/built-in.o (.text*); \
 122         arch/blackfin/cpu/built-in.o (.text*); \
 123         . = DEFINED(env_offset) ? env_offset : .; \
 124         common/env_embedded.o (.text*);
 125 #endif
 126
 127
 128 /*
 129  * I2C Settings
 130  */
 131 #define CONFIG_BFIN_TWI_I2C     1
 132 #define CONFIG_HARD_I2C         1
 133
 134
 135 /*
 136  * SPI_MMC Settings
 137  */
 138 #define CONFIG_MMC_SPI
 139 #ifdef CONFIG_MMC_SPI
 140 #define CONFIG_MMC
 141 #define CONFIG_GENERIC_MMC
 142 #endif
 143
 144 /*
 145  * NAND Settings
 146  */
 147 /* #define CONFIG_NAND_PLAT */
 148 #ifdef CONFIG_NAND_PLAT
 149 #define CONFIG_SYS_NAND_BASE            0x20212000
 150 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 151
 152 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
 153 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
 154 #define BFIN_NAND_WRITE(addr, cmd) \
 155         do { \
 156                 bfin_write8(addr, cmd); \
 157                 SSYNC(); \
 158         } while (0)
 159
 160 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 161 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
 162 #define NAND_PLAT_GPIO_DEV_READY       GPIO_PF3
 163 #endif /* CONFIG_NAND_PLAT */
 164
 165 /*
 166  * CF-CARD IDE-HDD Support
 167  */
 168
 169 /*
 170  * Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card)
 171  * Strange address mapping Blackfin A13 connects to CF_A0
 172  */
 173
 174 /* #define CONFIG_BFIN_TRUE_IDE */
 175
 176 /*
 177  * Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card)
 178  * This should be the preferred mode
 179  */
 180
 181 /* #define CONFIG_BFIN_CF_IDE */
 182
 183 /*
 184  * Add IDE Disk Drive (HDD) support
 185  * See example interface here:
 186  * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin
 187  */
 188
 189 /* #define CONFIG_BFIN_HDD_IDE */
 190
 191 #if defined(CONFIG_BFIN_CF_IDE) || \
 192     defined(CONFIG_BFIN_HDD_IDE) || \
 193     defined(CONFIG_BFIN_TRUE_IDE)
 194 # define CONFIG_BFIN_IDE        1
 195 # define CONFIG_CMD_IDE
 196 #endif
 197
 198 #if defined(CONFIG_BFIN_IDE)
 199
 200 #define CONFIG_DOS_PARTITION    1
 201 /*
 202  * IDE/ATA stuff
 203  */
 204 #undef  CONFIG_IDE_8xx_DIRECT   /* no pcmcia interface required */
 205 #undef  CONFIG_IDE_LED          /* no led for ide supported */
 206 #undef  CONFIG_IDE_RESET        /* no reset for ide supported */
 207
 208 #define CONFIG_SYS_IDE_MAXBUS           1
 209 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS * 1)
 210
 211 #undef  CONFIG_EBIU_AMBCTL1_VAL
 212 #define CONFIG_EBIU_AMBCTL1_VAL         0xFFC3FFC3
 213
 214 #define CONFIG_CF_ATASEL_DIS    0x20311800
 215 #define CONFIG_CF_ATASEL_ENA    0x20311802
 216
 217 #if defined(CONFIG_BFIN_TRUE_IDE)
 218 /*
 219  * Note that these settings aren't for the most part used in include/ata.h
 220  * when all of the ATA registers are setup
 221  */
 222 #define CONFIG_SYS_ATA_BASE_ADDR        0x2031C000
 223 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 224 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0020  /* data I/O */
 225 #define CONFIG_SYS_ATA_REG_OFFSET       0x0020  /* normal register accesses */
 226 #define CONFIG_SYS_ATA_ALT_OFFSET       0x001C  /* alternate registers */
 227 #define CONFIG_SYS_ATA_STRIDE           2       /* CF.A0 --> Blackfin.A13 */
 228
 229 #elif defined(CONFIG_BFIN_CF_IDE)
 230 #define CONFIG_SYS_ATA_BASE_ADDR        0x20211800
 231 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 232 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* data I/O */
 233 #define CONFIG_SYS_ATA_REG_OFFSET       0x0000  /* normal register accesses */
 234 #define CONFIG_SYS_ATA_ALT_OFFSET       0x000E  /* alternate registers */
 235 #define CONFIG_SYS_ATA_STRIDE           1       /* CF_A0=0, with /CE1 /CE2 odd/even byte selects */
 236
 237 #elif defined(CONFIG_BFIN_HDD_IDE)
 238 #define CONFIG_SYS_ATA_BASE_ADDR        0x20314000
 239 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 240 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0020  /* data I/O */
 241 #define CONFIG_SYS_ATA_REG_OFFSET       0x0020  /* normal register accesses */
 242 #define CONFIG_SYS_ATA_ALT_OFFSET       0x001C  /* alternate registers */
 243 #define CONFIG_SYS_ATA_STRIDE           2       /* CF.A0 --> Blackfin.A1 */
 244 #undef  CONFIG_SCLK_DIV
 245 #define CONFIG_SCLK_DIV         8
 246 #endif
 247
 248 #endif
 249
 250
 251 /*
 252  * Misc Settings
 253  */
 254 #define CONFIG_MISC_INIT_R
 255 #define CONFIG_RTC_BFIN
 256 #define CONFIG_UART_CONSOLE     0
 257 #define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 258
 259 /* Define if want to do post memory test */
 260 #undef CONFIG_POST
 261 #ifdef CONFIG_POST
 262 #define CONFIG_SYS_POST_HOTKEYS_GPIO    GPIO_PF5
 263 #define CONFIG_POST_BSPEC1_GPIO_LEDS \
 264         GPIO_PF6, GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11,
 265 #define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
 266         GPIO_PF5, GPIO_PF4, GPIO_PF3, GPIO_PF2,
 267 #define CONFIG_POST_BSPEC2_GPIO_NAMES \
 268         10, 11, 12, 13,
 269 #define CONFIG_SYS_POST_FLASH_START     11
 270 #define CONFIG_SYS_POST_FLASH_END       71
 271 #endif
 272
 273 /* These are for board tests */
 274 #if 0
 275 #define CONFIG_BOOTCOMMAND       "bootldr 0x203f0100"
 276 #define CONFIG_AUTOBOOT_KEYED
 277 #define CONFIG_AUTOBOOT_PROMPT \
 278         "autoboot in %d seconds: press space to stop\n", bootdelay
 279 #define CONFIG_AUTOBOOT_STOP_STR " "
 280 #endif
 281
 282
 283 /*
 284  * Pull in common ADI header for remaining command/environment setup
 285  */
 286 #include <configs/bfin_adi_common.h>
 287
 288 #endif