include/configs/bf537-stamp.h

   1 /*
   2  * U-boot - Configuration file for BF537 STAMP board
   3  */
   4
   5 #ifndef __CONFIG_BF537_H__
   6 #define __CONFIG_BF537_H__
   7
   8 #include <asm/blackfin-config-pre.h>
   9
  10 #define CFG_LONGHELP            1
  11 #define CONFIG_CMDLINE_EDITING  1
  12 #define CONFIG_BAUDRATE         57600
  13 /* Set default serial console for bf537 */
  14 #define CONFIG_UART_CONSOLE     0
  15 #define CONFIG_BF537            1
  16 #define CONFIG_BOOTDELAY        5
  17 /* define CONFIG_BF537_STAMP_LEDCMD to enable LED command*/
  18 /*#define CONFIG_BF537_STAMP_LEDCMD     1*/
  19
  20 /*
  21  * Boot Mode Set
  22  * Blackfin can support several boot modes
  23  */
  24 #define BF537_BYPASS_BOOT       0x0011  /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM)  */
  25 #define BF537_PARA_BOOT         0x0012  /* Bootmode 1: Boot from 8-bit or 16-bit flash                          */
  26 #define BF537_SPI_MASTER_BOOT   0x0014  /* Bootmode 3: SPI master mode boot from SPI flash                      */
  27 #define BF537_SPI_SLAVE_BOOT    0x0015  /* Bootmode 4: SPI slave mode boot from SPI flash                       */
  28 #define BF537_TWI_MASTER_BOOT   0x0016  /* Bootmode 5: TWI master mode boot from EEPROM                         */
  29 #define BF537_TWI_SLAVE_BOOT    0x0017  /* Bootmode 6: TWI slave mode boot from EEPROM                          */
  30 #define BF537_UART_BOOT         0x0018  /* Bootmode 7: UART slave mdoe boot via UART host                       */
  31 /* Define the boot mode */
  32 #define BFIN_BOOT_MODE          BF537_BYPASS_BOOT
  33
  34 #define CONFIG_PANIC_HANG 1
  35
  36 #define CONFIG_BFIN_CPU bf537-0.2
  37 #define CONFIG_BFIN_MAC
  38
  39 /* This sets the default state of the cache on U-Boot's boot */
  40 #define CONFIG_ICACHE_ON
  41 #define CONFIG_DCACHE_ON
  42
  43 /* Define if want to do post memory test */
  44 #undef CONFIG_POST_TEST
  45
  46 /* Define where the uboot will be loaded by on-chip boot rom */
  47 #define APP_ENTRY 0x00001000
  48
  49 #define CONFIG_RTC_BFIN         1
  50 #define CONFIG_BOOT_RETRY_TIME  -1      /* Enable this if bootretry required, currently its disabled */
  51
  52 /* CONFIG_CLKIN_HZ is any value in Hz                           */
  53 #define CONFIG_CLKIN_HZ         25000000
  54 /* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN     */
  55 /*                                                  1=CLKIN/2   */
  56 #define CONFIG_CLKIN_HALF       0
  57 /* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
  58 /*                                                  1=bypass PLL*/
  59 #define CONFIG_PLL_BYPASS       0
  60 /* CONFIG_VCO_MULT controls what the multiplier of the PLL is.  */
  61 /* Values can range from 1-64                                   */
  62 #define CONFIG_VCO_MULT                 20
  63 /* CONFIG_CCLK_DIV controls what the core clock divider is      */
  64 /* Values can be 1, 2, 4, or 8 ONLY                             */
  65 #define CONFIG_CCLK_DIV                 1
  66 /* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
  67 /* Values can range from 1-15                                   */
  68 #define CONFIG_SCLK_DIV                 5
  69 /* CONFIG_SPI_BAUD controls the SPI peripheral clock divider    */
  70 /* Values can range from 2-65535                                */
  71 /* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)                 */
  72 #define CONFIG_SPI_BAUD                 2
  73 #if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
  74 #define CONFIG_SPI_BAUD_INITBLOCK       4
  75 #endif
  76
  77 #if ( CONFIG_CLKIN_HALF == 0 )
  78 #define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
  79 #else
  80 #define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
  81 #endif
  82
  83 #if (CONFIG_PLL_BYPASS == 0)
  84 #define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
  85 #define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
  86 #else
  87 #define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
  88 #define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
  89 #endif
  90
  91 #if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
  92 #if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
  93 #define CONFIG_SPI_FLASH_FAST_READ 1    /* Needed if SPI_CLK > 20 MHz */
  94 #else
  95 #undef CONFIG_SPI_FLASH_FAST_READ
  96 #endif
  97 #endif
  98
  99 #define CONFIG_MEM_SIZE                 64      /* 128, 64, 32, 16 */
 100 #define CONFIG_MEM_ADD_WDTH             10      /* 8, 9, 10, 11 */
 101 #define CONFIG_MEM_MT48LC32M8A2_75      1
 102
 103 #define CONFIG_LOADS_ECHO               1
 104
 105 /*
 106  * rarpb, bootp or dhcp commands will perform only a
 107  * configuration lookup from the BOOTP/DHCP server
 108  * but not try to load any image using TFTP
 109  */
 110 #define CFG_AUTOLOAD                    "no"
 111
 112 /*
 113  * Network Settings
 114  */
 115 /* network support */
 116 #ifdef CONFIG_BFIN_MAC
 117 #define CONFIG_IPADDR           192.168.0.15
 118 #define CONFIG_NETMASK          255.255.255.0
 119 #define CONFIG_GATEWAYIP        192.168.0.1
 120 #define CONFIG_SERVERIP         192.168.0.2
 121 #define CONFIG_HOSTNAME         BF537
 122 #endif
 123
 124 #define CONFIG_ROOTPATH         /romfs
 125 /* Uncomment next line to use fixed MAC address */
 126 /* #define CONFIG_ETHADDR       02:80:ad:20:31:e8 */
 127 /* This is the routine that copies the MAC in Flash to the 'ethaddr' setting */
 128
 129 #define CFG_LONGHELP            1
 130 #define CONFIG_BOOTDELAY        5
 131 #define CONFIG_BOOT_RETRY_TIME  -1      /* Enable this if bootretry required, currently its disabled */
 132 #define CONFIG_BOOTCOMMAND      "run ramboot"
 133
 134 #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) && defined(CONFIG_POST_TEST)
 135 /* POST support */
 136 #define CONFIG_POST             ( CFG_POST_MEMORY | \
 137                                   CFG_POST_UART   | \
 138                                   CFG_POST_FLASH  | \
 139                                   CFG_POST_ETHER  | \
 140                                   CFG_POST_LED    | \
 141                                   CFG_POST_BUTTON)
 142 #else
 143 #undef CONFIG_POST
 144 #endif
 145
 146 #ifdef CONFIG_POST
 147 #define FLASH_START_POST_BLOCK  11      /* Should > = 11 */
 148 #define FLASH_END_POST_BLOCK    71      /* Should < = 71 */
 149 #endif
 150
 151 /* CF-CARD IDE-HDD Support */
 152
 153 /* #define CONFIG_BFIN_TRUE_IDE */      /* Add CF flash card support */
 154 /* #define CONFIG_BFIN_CF_IDE */        /* Add CF flash card support */
 155 /* #define CONFIG_BFIN_HDD_IDE */       /* Add IDE Disk Drive (HDD) support */
 156
 157 #if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
 158 # define CONFIG_BFIN_IDE        1
 159 #endif
 160
 161 /*#define CONFIG_BF537_NAND */          /* Add nand flash support */
 162
 163 #define CONFIG_NETCONSOLE       1
 164 #define CONFIG_NET_MULTI        1
 165
 166 /*
 167  * BOOTP options
 168  */
 169 #define CONFIG_BOOTP_BOOTFILESIZE
 170 #define CONFIG_BOOTP_BOOTPATH
 171 #define CONFIG_BOOTP_GATEWAY
 172 #define CONFIG_BOOTP_HOSTNAME
 173
 174
 175 /*
 176  * Command line configuration.
 177  */
 178 #include <config_cmd_default.h>
 179
 180 #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
 181
 182 #define CONFIG_CMD_ELF
 183 #define CONFIG_CMD_I2C
 184 #define CONFIG_CMD_CACHE
 185 #define CONFIG_CMD_JFFS2
 186 #define CONFIG_CMD_EEPROM
 187 #define CONFIG_CMD_DATE
 188
 189 #ifndef CONFIG_BFIN_MAC
 190 #undef CONFIG_CMD_NET
 191 #else
 192 #define CONFIG_CMD_PING
 193 #endif
 194
 195 #if defined(CONFIG_BFIN_CF_IDE) \
 196         || defined(CONFIG_BFIN_HDD_IDE) \
 197         || defined(CONFIG_BFIN_TRUE_IDE)
 198 #define CONFIG_CMD_IDE
 199 #endif
 200
 201 #endif
 202
 203 #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
 204
 205 #define CONFIG_CMD_DHCP
 206
 207 #if defined(CONFIG_POST)
 208 #define CONFIG_CMD_DIAG
 209 #endif
 210
 211 #ifdef CONFIG_BF537_NAND
 212 #define CONFIG_CMD_NAND
 213 #endif
 214
 215 #endif
 216
 217
 218 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
 219 #define CONFIG_LOADADDR 0x1000000
 220
 221 #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
 222 #ifdef CONFIG_BFIN_MAC
 223 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 224         "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
 225         "nfsargs=setenv bootargs root=/dev/nfs rw "             \
 226         "nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
 227         "addip=setenv bootargs $(bootargs) "                    \
 228         "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
 229         ":$(hostname):eth0:off\0"                               \
 230         "ramboot=tftpboot $(loadaddr) linux;"                   \
 231         "run ramargs;run addip;bootelf\0"                       \
 232         "nfsboot=tftpboot $(loadaddr) linux;"                   \
 233         "run nfsargs;run addip;bootelf\0"                       \
 234         "flashboot=bootm 0x20100000\0"                          \
 235         "update=tftpboot $(loadaddr) u-boot.bin;"               \
 236         "protect off 0x20000000 0x2007FFFF;"                    \
 237         "erase 0x20000000 0x2007FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0"   \
 238         ""
 239 #else
 240 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 241         "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
 242         "flashboot=bootm 0x20100000\0"                          \
 243         ""
 244 #endif
 245 #elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
 246 #ifdef CONFIG_BFIN_MAC
 247 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 248         "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
 249         "nfsargs=setenv bootargs root=/dev/nfs rw "             \
 250         "nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
 251         "addip=setenv bootargs $(bootargs) "                    \
 252         "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
 253         ":$(hostname):eth0:off\0"                               \
 254         "ramboot=tftpboot $(loadaddr) linux;"                   \
 255         "run ramargs;run addip;bootelf\0"                       \
 256         "nfsboot=tftpboot $(loadaddr) linux;"                   \
 257         "run nfsargs;run addip;bootelf\0"                       \
 258         "flashboot=bootm 0x20100000\0"                          \
 259         "update=tftpboot $(loadaddr) u-boot.ldr;"               \
 260         "eeprom write $(loadaddr) 0x0 $(filesize);\0"           \
 261         ""
 262 #else
 263 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 264         "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
 265         "flashboot=bootm 0x20100000\0"                          \
 266         ""
 267 #endif
 268 #endif
 269
 270 #define CFG_PROMPT              "bfin> "        /* Monitor Command Prompt */
 271
 272 #if defined(CONFIG_CMD_KGDB)
 273 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size */
 274 #else
 275 #define CFG_CBSIZE              256     /* Console I/O Buffer Size */
 276 #endif
 277 #define CFG_MAX_RAM_SIZE        (CONFIG_MEM_SIZE * 1024*1024)
 278 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)      /* Print Buffer Size */
 279 #define CFG_MAXARGS             16      /* max number of command args */
 280 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size */
 281 #define CFG_MEMTEST_START       0x0     /* memtest works on */
 282 #define CFG_MEMTEST_END         ( (CONFIG_MEM_SIZE - 1) * 1024*1024)    /* 1 ... 63 MB in DRAM */
 283 #define CFG_LOAD_ADDR           CONFIG_LOADADDR /* default load address */
 284 #define CFG_HZ                  1000    /* decrementer freq: 10 ms ticks */
 285 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 286 #define CFG_SDRAM_BASE          0x00000000
 287
 288 #define CFG_FLASH_BASE          0x20000000
 289 #define CFG_FLASH_CFI           /* The flash is CFI compatible */
 290 #define CFG_FLASH_CFI_DRIVER    /* Use common CFI driver */
 291 #define CFG_FLASH_PROTECTION
 292 #define CFG_MAX_FLASH_BANKS     1
 293 #define CFG_MAX_FLASH_SECT      71      /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
 294
 295 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 296 #define CFG_MONITOR_BASE        (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
 297 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 298 #define CFG_MALLOC_BASE         (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
 299 #define CFG_GBL_DATA_SIZE       0x4000
 300 #define CFG_GBL_DATA_ADDR       (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
 301 #define CONFIG_STACKBASE        (CFG_GBL_DATA_ADDR  - 4)
 302
 303 #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_UART_BOOT)
 304 /* for bf537-stamp, usrt boot mode still store env in flash */
 305 #define CFG_ENV_IS_IN_FLASH     1
 306 #define CFG_ENV_ADDR            0x20004000
 307 #define CFG_ENV_OFFSET          (CFG_ENV_ADDR - CFG_FLASH_BASE)
 308 #elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
 309 #define CFG_ENV_IS_IN_EEPROM    1
 310 #define CFG_ENV_OFFSET          0x4000
 311 #define CFG_ENV_HEADER          (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
 312 #endif
 313 #define CFG_ENV_SIZE            0x2000
 314 #define CFG_ENV_SECT_SIZE       0x2000  /* Total Size of Environment Sector */
 315 /* #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) */
 316 #define ENV_IS_EMBEDDED
 317 /* #endif */
 318
 319 /* JFFS Partition offset set  */
 320 #define CFG_JFFS2_FIRST_BANK    0
 321 #define CFG_JFFS2_NUM_BANKS     1
 322 /* 512k reserved for u-boot */
 323 #define CFG_JFFS2_FIRST_SECTOR  15
 324
 325 #define CONFIG_SPI
 326
 327 /*
 328  * Stack sizes
 329  */
 330 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 331
 332 #define POLL_MODE               1
 333 #define FLASH_TOT_SECT          71
 334 #define FLASH_SIZE              0x400000
 335 #define CFG_FLASH_SIZE          0x400000
 336
 337 /*
 338  * Board NAND Infomation
 339  */
 340
 341 #define CFG_NAND_ADDR           0x20212000
 342 #define CFG_NAND_BASE           CFG_NAND_ADDR
 343 #define CFG_MAX_NAND_DEVICE     1
 344 #define SECTORSIZE              512
 345 #define ADDR_COLUMN             1
 346 #define ADDR_PAGE               2
 347 #define ADDR_COLUMN_PAGE        3
 348 #define NAND_ChipID_UNKNOWN     0x00
 349 #define NAND_MAX_FLOORS         1
 350 #define NAND_MAX_CHIPS          1
 351 #define BFIN_NAND_READY         PF3
 352
 353 #define NAND_WAIT_READY(nand)                   \
 354         do {                                    \
 355                 int timeout = 0;                \
 356                 while(!(*pPORTFIO & PF3))       \
 357                         if (timeout++ > 100000) \
 358                                 break;          \
 359         } while (0)
 360
 361 #define BFIN_NAND_CLE           (1<<2)  /* A2 -> Command Enable */
 362 #define BFIN_NAND_ALE           (1<<1)  /* A1 -> Address Enable */
 363
 364 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)
 365 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)
 366 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
 367 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
 368
 369 /*
 370  * Initialize PSD4256 registers for using I2C
 371  */
 372 #define CONFIG_MISC_INIT_R
 373
 374 #define CFG_BOOTM_LEN           0x4000000       /* Large Image Length, set to 64 Meg */
 375
 376 /*
 377  * I2C settings
 378  * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
 379  */
 380 /* #define CONFIG_SOFT_I2C      1*/     /* I2C bit-banged */
 381 #define CONFIG_HARD_I2C         1       /* I2C TWI */
 382 #if defined CONFIG_HARD_I2C
 383 #define CONFIG_TWICLK_KHZ       50
 384 #endif
 385
 386 #if defined CONFIG_SOFT_I2C
 387 /*
 388  * Software (bit-bang) I2C driver configuration
 389  */
 390 #define PF_SCL                  PF0
 391 #define PF_SDA                  PF1
 392
 393 #define I2C_INIT                (*pFIO_DIR |=  PF_SCL); asm("ssync;")
 394 #define I2C_ACTIVE              (*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
 395 #define I2C_TRISTATE            (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
 396 #define I2C_READ                ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
 397 #define I2C_SDA(bit)            if(bit) { \
 398                                         *pFIO_FLAG_S = PF_SDA; \
 399                                         asm("ssync;"); \
 400                                         } \
 401                                 else    { \
 402                                         *pFIO_FLAG_C = PF_SDA; \
 403                                         asm("ssync;"); \
 404                                         }
 405 #define I2C_SCL(bit)            if(bit) { \
 406                                         *pFIO_FLAG_S = PF_SCL; \
 407                                         asm("ssync;"); \
 408                                         } \
 409                                 else    { \
 410                                         *pFIO_FLAG_C = PF_SCL; \
 411                                         asm("ssync;"); \
 412                                         }
 413 #define I2C_DELAY               udelay(5)       /* 1/4 I2C clock duration */
 414 #endif
 415
 416 #define CFG_I2C_SPEED           50000
 417 #define CFG_I2C_SLAVE           0xFE
 418
 419 /* 0xFF, 0x7BB07BB0, 0x22547BB0 */
 420 /* #define AMGCTLVAL            (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
 421 #define AMBCTL0VAL              (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
 422                                 ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
 423 #define AMBCTL1VAL              (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
 424                                 B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
 425 */
 426
 427 #define AMGCTLVAL               0xFF
 428 #define AMBCTL0VAL              0x7BB07BB0
 429 #define AMBCTL1VAL              0xFFC27BB0
 430
 431 #define CONFIG_VDSP             1
 432
 433 #ifdef CONFIG_VDSP
 434 #define ET_EXEC_VDSP            0x8
 435 #define SHT_STRTAB_VDSP         0x1
 436 #define ELFSHDRSIZE_VDSP        0x2C
 437 #define VDSP_ENTRY_ADDR         0xFFA00000
 438 #endif
 439
 440 #if defined(CONFIG_BFIN_IDE)
 441
 442 #define CONFIG_DOS_PARTITION    1
 443 /*
 444  * IDE/ATA stuff
 445  */
 446 #undef  CONFIG_IDE_8xx_DIRECT   /* no pcmcia interface required */
 447 #undef  CONFIG_IDE_LED          /* no led for ide supported */
 448 #undef  CONFIG_IDE_RESET        /* no reset for ide supported */
 449
 450 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE busses */
 451 #define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*1)      /* max. 1 drives per IDE bus */
 452
 453 #undef  AMBCTL1VAL
 454 #define AMBCTL1VAL              0xFFC3FFC3
 455
 456 #define CONFIG_CF_ATASEL_DIS    0x20311800
 457 #define CONFIG_CF_ATASEL_ENA    0x20311802
 458
 459 #if defined(CONFIG_BFIN_TRUE_IDE)
 460 /*
 461  * Note that these settings aren't for the most part used in include/ata.h
 462  * when all of the ATA registers are setup
 463  */
 464 #define CFG_ATA_BASE_ADDR       0x2031C000
 465 #define CFG_ATA_IDE0_OFFSET     0x0000
 466 #define CFG_ATA_DATA_OFFSET     0x0020  /* Offset for data I/O */
 467 #define CFG_ATA_REG_OFFSET      0x0020  /* Offset for normal register accesses */
 468 #define CFG_ATA_ALT_OFFSET      0x001C  /* Offset for alternate registers */
 469 #define CFG_ATA_STRIDE          2       /* CF.A0 --> Blackfin.Ax */
 470 #endif                          /* CONFIG_BFIN_TRUE_IDE */
 471
 472 #if defined(CONFIG_BFIN_CF_IDE) /* USE CompactFlash Storage Card in the common memory space */
 473 #define CFG_ATA_BASE_ADDR       0x20211800
 474 #define CFG_ATA_IDE0_OFFSET     0x0000
 475 #define CFG_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O */
 476 #define CFG_ATA_REG_OFFSET      0x0000  /* Offset for normal register accesses */
 477 #define CFG_ATA_ALT_OFFSET      0x000E  /* Offset for alternate registers */
 478 #define CFG_ATA_STRIDE          1       /* CF.A0 --> Blackfin.Ax */
 479 #endif                          /* CONFIG_BFIN_CF_IDE */
 480
 481 #if defined(CONFIG_BFIN_HDD_IDE)        /* USE TRUE IDE */
 482 #define CFG_ATA_BASE_ADDR       0x20314000
 483 #define CFG_ATA_IDE0_OFFSET     0x0000
 484 #define CFG_ATA_DATA_OFFSET     0x0020  /* Offset for data I/O */
 485 #define CFG_ATA_REG_OFFSET      0x0020  /* Offset for normal register accesses */
 486 #define CFG_ATA_ALT_OFFSET      0x001C  /* Offset for alternate registers */
 487 #define CFG_ATA_STRIDE          2       /* CF.A0 --> Blackfin.A1 */
 488
 489 #undef  CONFIG_SCLK_DIV
 490 #define CONFIG_SCLK_DIV         8
 491 #endif                          /* CONFIG_BFIN_HDD_IDE */
 492
 493 #endif                          /*CONFIG_BFIN_IDE */
 494
 495 #endif