include/configs/bf537-stamp.h

   1 /*
   2  * U-boot - Configuration file for BF537 STAMP board
   3  */
   4
   5 #ifndef __CONFIG_BF537_H__
   6 #define __CONFIG_BF537_H__
   7
   8 #define CFG_LONGHELP            1
   9 #define CONFIG_CMDLINE_EDITING  1
  10 #define CONFIG_BAUDRATE         57600
  11 /* Set default serial console for bf537 */
  12 #define CONFIG_UART_CONSOLE     0
  13 #define CONFIG_BF537            1
  14 #define CONFIG_BOOTDELAY        5
  15 /* define CONFIG_BF537_STAMP_LEDCMD to enable LED command*/
  16 /*#define CONFIG_BF537_STAMP_LEDCMD     1*/
  17
  18 /*
  19  * Boot Mode Set
  20  * Blackfin can support several boot modes
  21  */
  22 #define BF537_BYPASS_BOOT       0x0011  /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM)  */
  23 #define BF537_PARA_BOOT         0x0012  /* Bootmode 1: Boot from 8-bit or 16-bit flash                          */
  24 #define BF537_SPI_MASTER_BOOT   0x0014  /* Bootmode 3: SPI master mode boot from SPI flash                      */
  25 #define BF537_SPI_SLAVE_BOOT    0x0015  /* Bootmode 4: SPI slave mode boot from SPI flash                       */
  26 #define BF537_TWI_MASTER_BOOT   0x0016  /* Bootmode 5: TWI master mode boot from EEPROM                         */
  27 #define BF537_TWI_SLAVE_BOOT    0x0017  /* Bootmode 6: TWI slave mode boot from EEPROM                          */
  28 #define BF537_UART_BOOT         0x0018  /* Bootmode 7: UART slave mdoe boot via UART host                       */
  29 /* Define the boot mode */
  30 #define BFIN_BOOT_MODE          BF537_BYPASS_BOOT
  31
  32 #define CONFIG_PANIC_HANG 1
  33
  34 #define ADSP_BF534              0x34
  35 #define ADSP_BF536              0x36
  36 #define ADSP_BF537              0x37
  37 #define BFIN_CPU                ADSP_BF537
  38
  39 /* This sets the default state of the cache on U-Boot's boot */
  40 #define CONFIG_ICACHE_ON
  41 #define CONFIG_DCACHE_ON
  42
  43 /* Define if want to do post memory test */
  44 #undef CONFIG_POST_TEST
  45
  46 /* Define where the uboot will be loaded by on-chip boot rom */
  47 #define APP_ENTRY 0x00001000
  48
  49 #define CONFIG_RTC_BFIN         1
  50 #define CONFIG_BOOT_RETRY_TIME  -1      /* Enable this if bootretry required, currently its disabled */
  51
  52 /* CONFIG_CLKIN_HZ is any value in Hz                           */
  53 #define CONFIG_CLKIN_HZ         25000000
  54 /* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN     */
  55 /*                                                  1=CLKIN/2   */
  56 #define CONFIG_CLKIN_HALF       0
  57 /* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
  58 /*                                                  1=bypass PLL*/
  59 #define CONFIG_PLL_BYPASS       0
  60 /* CONFIG_VCO_MULT controls what the multiplier of the PLL is.  */
  61 /* Values can range from 1-64                                   */
  62 #define CONFIG_VCO_MULT                 20
  63 /* CONFIG_CCLK_DIV controls what the core clock divider is      */
  64 /* Values can be 1, 2, 4, or 8 ONLY                             */
  65 #define CONFIG_CCLK_DIV                 1
  66 /* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
  67 /* Values can range from 1-15                                   */
  68 #define CONFIG_SCLK_DIV                 5
  69 /* CONFIG_SPI_BAUD controls the SPI peripheral clock divider    */
  70 /* Values can range from 2-65535                                */
  71 /* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)                 */
  72 #define CONFIG_SPI_BAUD                 2
  73 #if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
  74 #define CONFIG_SPI_BAUD_INITBLOCK       4
  75 #endif
  76
  77 #if ( CONFIG_CLKIN_HALF == 0 )
  78 #define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
  79 #else
  80 #define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
  81 #endif
  82
  83 #if (CONFIG_PLL_BYPASS == 0)
  84 #define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
  85 #define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
  86 #else
  87 #define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
  88 #define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
  89 #endif
  90
  91 #if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
  92 #if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
  93 #define CONFIG_SPI_FLASH_FAST_READ 1    /* Needed if SPI_CLK > 20 MHz */
  94 #else
  95 #undef CONFIG_SPI_FLASH_FAST_READ
  96 #endif
  97 #endif
  98
  99 #define CONFIG_MEM_SIZE                 64      /* 128, 64, 32, 16 */
 100 #define CONFIG_MEM_ADD_WDTH             10      /* 8, 9, 10, 11 */
 101 #define CONFIG_MEM_MT48LC32M8A2_75      1
 102
 103 #define CONFIG_LOADS_ECHO               1
 104
 105 /*
 106  * rarpb, bootp or dhcp commands will perform only a
 107  * configuration lookup from the BOOTP/DHCP server
 108  * but not try to load any image using TFTP
 109  */
 110 #define CFG_AUTOLOAD                    "no"
 111
 112 /*
 113  * Network Settings
 114  */
 115 /* network support */
 116 #if (BFIN_CPU != ADSP_BF534)
 117 #define CONFIG_IPADDR           192.168.0.15
 118 #define CONFIG_NETMASK          255.255.255.0
 119 #define CONFIG_GATEWAYIP        192.168.0.1
 120 #define CONFIG_SERVERIP         192.168.0.2
 121 #define CONFIG_HOSTNAME         BF537
 122 #endif
 123
 124 #define CONFIG_ROOTPATH         /romfs
 125 /* Uncomment next line to use fixed MAC address */
 126 /* #define CONFIG_ETHADDR       02:80:ad:20:31:e8 */
 127 /* This is the routine that copies the MAC in Flash to the 'ethaddr' setting */
 128
 129 #define CFG_LONGHELP            1
 130 #define CONFIG_BOOTDELAY        5
 131 #define CONFIG_BOOT_RETRY_TIME  -1      /* Enable this if bootretry required, currently its disabled */
 132 #define CONFIG_BOOTCOMMAND      "run ramboot"
 133
 134 #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) && defined(CONFIG_POST_TEST)
 135 /* POST support */
 136 #define CONFIG_POST             ( CFG_POST_MEMORY | \
 137                                   CFG_POST_UART   | \
 138                                   CFG_POST_FLASH  | \
 139                                   CFG_POST_ETHER  | \
 140                                   CFG_POST_LED    | \
 141                                   CFG_POST_BUTTON)
 142 #else
 143 #undef CONFIG_POST
 144 #endif
 145
 146 #ifdef CONFIG_POST
 147 #define CFG_CMD_POST_DIAG       CFG_CMD_DIAG
 148 #define FLASH_START_POST_BLOCK  11      /* Should > = 11 */
 149 #define FLASH_END_POST_BLOCK    71      /* Should < = 71 */
 150 #else
 151 #define CFG_CMD_POST_DIAG       0
 152 #endif
 153
 154 /* CF-CARD IDE-HDD Support */
 155
 156 /* #define CONFIG_BFIN_TRUE_IDE */      /* Add CF flash card support */
 157 /* #define CONFIG_BFIN_CF_IDE */        /* Add CF flash card support */
 158 /* #define CONFIG_BFIN_HDD_IDE */       /* Add IDE Disk Drive (HDD) support */
 159
 160 #if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
 161 # define CONFIG_BFIN_IDE        1
 162 # define ADD_IDE_CMD            CFG_CMD_IDE
 163 #else
 164 # define ADD_IDE_CMD            0
 165 #endif
 166
 167 /*#define CONFIG_BF537_NAND */          /* Add nand flash support */
 168
 169 #ifdef CONFIG_BF537_NAND
 170 # define ADD_NAND_CMD           CFG_CMD_NAND
 171 #else
 172 # define ADD_NAND_CMD           0
 173 #endif
 174
 175 #define CONFIG_NETCONSOLE       1
 176 #define CONFIG_NET_MULTI        1
 177
 178 #if (BFIN_CPU == ADSP_BF534)
 179 #define CONFIG_BFIN_CMD         (CONFIG_CMD_DFL & ~CFG_CMD_NET)
 180 #else
 181 #define CONFIG_BFIN_CMD         (CONFIG_CMD_DFL | CFG_CMD_PING)
 182 #endif
 183
 184 #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
 185 #define CONFIG_COMMANDS         (CONFIG_BFIN_CMD| \
 186                                  CFG_CMD_ELF    | \
 187                                  CFG_CMD_I2C    | \
 188                                  CFG_CMD_CACHE  | \
 189                                  CFG_CMD_JFFS2  | \
 190                                  CFG_CMD_EEPROM | \
 191                                  CFG_CMD_DHCP   | \
 192                                  ADD_IDE_CMD    | \
 193                                  ADD_NAND_CMD   | \
 194                                  CFG_CMD_POST_DIAG | \
 195                                  CFG_CMD_DATE)
 196 #elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
 197 #define CONFIG_COMMANDS         (CONFIG_BFIN_CMD| \
 198                                  CFG_CMD_ELF    | \
 199                                  CFG_CMD_I2C    | \
 200                                  CFG_CMD_CACHE  | \
 201                                  CFG_CMD_JFFS2  | \
 202                                  CFG_CMD_EEPROM | \
 203                                  ADD_IDE_CMD    | \
 204                                  CFG_CMD_DATE)
 205 #endif
 206
 207 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
 208 #define CONFIG_LOADADDR 0x1000000
 209
 210 #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
 211 #if (BFIN_CPU != ADSP_BF534)
 212 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 213         "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
 214         "nfsargs=setenv bootargs root=/dev/nfs rw "             \
 215         "nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
 216         "addip=setenv bootargs $(bootargs) "                    \
 217         "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
 218         ":$(hostname):eth0:off\0"                               \
 219         "ramboot=tftpboot $(loadaddr) linux;"                   \
 220         "run ramargs;run addip;bootelf\0"                       \
 221         "nfsboot=tftpboot $(loadaddr) linux;"                   \
 222         "run nfsargs;run addip;bootelf\0"                       \
 223         "flashboot=bootm 0x20100000\0"                          \
 224         "update=tftpboot $(loadaddr) u-boot.bin;"               \
 225         "protect off 0x20000000 0x2007FFFF;"                    \
 226         "erase 0x20000000 0x2007FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0"   \
 227         ""
 228 #else
 229 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 230         "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
 231         "flashboot=bootm 0x20100000\0"                          \
 232         ""
 233 #endif
 234 #elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
 235 #if (BFIN_CPU != ADSP_BF534)
 236 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 237         "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
 238         "nfsargs=setenv bootargs root=/dev/nfs rw "             \
 239         "nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
 240         "addip=setenv bootargs $(bootargs) "                    \
 241         "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
 242         ":$(hostname):eth0:off\0"                               \
 243         "ramboot=tftpboot $(loadaddr) linux;"                   \
 244         "run ramargs;run addip;bootelf\0"                       \
 245         "nfsboot=tftpboot $(loadaddr) linux;"                   \
 246         "run nfsargs;run addip;bootelf\0"                       \
 247         "flashboot=bootm 0x20100000\0"                          \
 248         "update=tftpboot $(loadaddr) u-boot.ldr;"               \
 249         "eeprom write $(loadaddr) 0x0 $(filesize);\0"           \
 250         ""
 251 #else
 252 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 253         "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
 254         "flashboot=bootm 0x20100000\0"                          \
 255         ""
 256 #endif
 257 #endif
 258
 259 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 260 #include <cmd_confdefs.h>
 261
 262 #if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
 263 #if (BFIN_CPU == ADSP_BF534)
 264 #define CFG_PROMPT              "serial_bf534> "        /* Monitor Command Prompt */
 265 #elif (BFIN_CPU == ADSP_BF536)
 266 #define CFG_PROMPT              "serial_bf536> "        /* Monitor Command Prompt */
 267 #else
 268 #define CFG_PROMPT              "serial_bf537> "        /* Monitor Command Prompt */
 269 #endif
 270 #else
 271 #if (BFIN_CPU == ADSP_BF534)
 272 #define CFG_PROMPT              "bf534> "       /* Monitor Command Prompt */
 273 #elif (BFIN_CPU == ADSP_BF536)
 274 #define CFG_PROMPT              "bf536> "       /* Monitor Command Prompt */
 275 #else
 276 #define CFG_PROMPT              "bf537> "       /* Monitor Command Prompt */
 277 #endif
 278 #endif
 279
 280 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 281 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size */
 282 #else
 283 #define CFG_CBSIZE              256     /* Console I/O Buffer Size */
 284 #endif
 285 #define CFG_MAX_RAM_SIZE        (CONFIG_MEM_SIZE * 1024*1024)
 286 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)      /* Print Buffer Size */
 287 #define CFG_MAXARGS             16      /* max number of command args */
 288 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size */
 289 #define CFG_MEMTEST_START       0x0     /* memtest works on */
 290 #define CFG_MEMTEST_END         ( (CONFIG_MEM_SIZE - 1) * 1024*1024)    /* 1 ... 63 MB in DRAM */
 291 #define CFG_LOAD_ADDR           CONFIG_LOADADDR /* default load address */
 292 #define CFG_HZ                  1000    /* decrementer freq: 10 ms ticks */
 293 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 294 #define CFG_SDRAM_BASE          0x00000000
 295
 296 #define CFG_FLASH_BASE          0x20000000
 297
 298 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 299 #define CFG_MONITOR_BASE        (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
 300 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 301 #define CFG_MALLOC_BASE         (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
 302 #define CFG_GBL_DATA_SIZE       0x4000
 303 #define CFG_GBL_DATA_ADDR       (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
 304 #define CONFIG_STACKBASE        (CFG_GBL_DATA_ADDR  - 4)
 305
 306 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 307 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks */
 308 #define CFG_MAX_FLASH_SECT      71      /* max number of sectors on one chip */
 309
 310 #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_UART_BOOT)
 311 /* for bf537-stamp, usrt boot mode still store env in flash */
 312 #define CFG_ENV_IS_IN_FLASH     1
 313 #define CFG_ENV_ADDR            0x20004000
 314 #define CFG_ENV_OFFSET          (CFG_ENV_ADDR - CFG_FLASH_BASE)
 315 #elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
 316 #define CFG_ENV_IS_IN_EEPROM    1
 317 #define CFG_ENV_OFFSET          0x4000
 318 #define CFG_ENV_HEADER          (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
 319 #endif
 320 #define CFG_ENV_SIZE            0x2000
 321 #define CFG_ENV_SECT_SIZE       0x2000  /* Total Size of Environment Sector */
 322 /* #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) */
 323 #define ENV_IS_EMBEDDED
 324 /* #endif */
 325
 326 /* JFFS Partition offset set  */
 327 #define CFG_JFFS2_FIRST_BANK    0
 328 #define CFG_JFFS2_NUM_BANKS     1
 329 /* 512k reserved for u-boot */
 330 #define CFG_JFFS2_FIRST_SECTOR  15
 331
 332 #define CONFIG_SPI
 333
 334 /*
 335  * Stack sizes
 336  */
 337 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 338
 339 #define POLL_MODE               1
 340 #define FLASH_TOT_SECT          71
 341 #define FLASH_SIZE              0x400000
 342 #define CFG_FLASH_SIZE          0x400000
 343
 344 /*
 345  * Board NAND Infomation
 346  */
 347
 348 #define CFG_NAND_ADDR           0x20212000
 349 #define CFG_NAND_BASE           CFG_NAND_ADDR
 350 #define CFG_MAX_NAND_DEVICE     1
 351 #define SECTORSIZE              512
 352 #define ADDR_COLUMN             1
 353 #define ADDR_PAGE               2
 354 #define ADDR_COLUMN_PAGE        3
 355 #define NAND_ChipID_UNKNOWN     0x00
 356 #define NAND_MAX_FLOORS         1
 357 #define NAND_MAX_CHIPS          1
 358 #define BFIN_NAND_READY         PF3
 359
 360 #define NAND_WAIT_READY(nand)                   \
 361         do {                                    \
 362                 int timeout = 0;                \
 363                 while(!(*pPORTFIO & PF3))       \
 364                         if (timeout++ > 100000) \
 365                                 break;          \
 366         } while (0)
 367
 368 #define BFIN_NAND_CLE           (1<<2)  /* A2 -> Command Enable */
 369 #define BFIN_NAND_ALE           (1<<1)  /* A1 -> Address Enable */
 370
 371 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)
 372 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)
 373 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
 374 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
 375
 376 /*
 377  * Initialize PSD4256 registers for using I2C
 378  */
 379 #define CONFIG_MISC_INIT_R
 380
 381 #define CFG_BOOTM_LEN           0x4000000       /* Large Image Length, set to 64 Meg */
 382
 383 /*
 384  * I2C settings
 385  * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
 386  */
 387 /* #define CONFIG_SOFT_I2C      1*/     /* I2C bit-banged */
 388 #define CONFIG_HARD_I2C         1       /* I2C TWI */
 389 #if defined CONFIG_HARD_I2C
 390 #define CONFIG_TWICLK_KHZ       50
 391 #endif
 392
 393 #if defined CONFIG_SOFT_I2C
 394 /*
 395  * Software (bit-bang) I2C driver configuration
 396  */
 397 #define PF_SCL                  PF0
 398 #define PF_SDA                  PF1
 399
 400 #define I2C_INIT                (*pFIO_DIR |=  PF_SCL); asm("ssync;")
 401 #define I2C_ACTIVE              (*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
 402 #define I2C_TRISTATE            (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
 403 #define I2C_READ                ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
 404 #define I2C_SDA(bit)            if(bit) { \
 405                                         *pFIO_FLAG_S = PF_SDA; \
 406                                         asm("ssync;"); \
 407                                         } \
 408                                 else    { \
 409                                         *pFIO_FLAG_C = PF_SDA; \
 410                                         asm("ssync;"); \
 411                                         }
 412 #define I2C_SCL(bit)            if(bit) { \
 413                                         *pFIO_FLAG_S = PF_SCL; \
 414                                         asm("ssync;"); \
 415                                         } \
 416                                 else    { \
 417                                         *pFIO_FLAG_C = PF_SCL; \
 418                                         asm("ssync;"); \
 419                                         }
 420 #define I2C_DELAY               udelay(5)       /* 1/4 I2C clock duration */
 421 #endif
 422
 423 #define CFG_I2C_SPEED           50000
 424 #define CFG_I2C_SLAVE           0xFE
 425
 426 /* 0xFF, 0x7BB07BB0, 0x22547BB0 */
 427 /* #define AMGCTLVAL            (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
 428 #define AMBCTL0VAL              (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
 429                                 ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
 430 #define AMBCTL1VAL              (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
 431                                 B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
 432 */
 433
 434 #define AMGCTLVAL               0xFF
 435 #define AMBCTL0VAL              0x7BB07BB0
 436 #define AMBCTL1VAL              0xFFC27BB0
 437
 438 #define CONFIG_VDSP             1
 439
 440 #ifdef CONFIG_VDSP
 441 #define ET_EXEC_VDSP            0x8
 442 #define SHT_STRTAB_VDSP         0x1
 443 #define ELFSHDRSIZE_VDSP        0x2C
 444 #define VDSP_ENTRY_ADDR         0xFFA00000
 445 #endif
 446
 447 #if defined(CONFIG_BFIN_IDE)
 448
 449 #define CONFIG_DOS_PARTITION    1
 450 /*
 451  * IDE/ATA stuff
 452  */
 453 #undef  CONFIG_IDE_8xx_DIRECT   /* no pcmcia interface required */
 454 #undef  CONFIG_IDE_LED          /* no led for ide supported */
 455 #undef  CONFIG_IDE_RESET        /* no reset for ide supported */
 456
 457 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE busses */
 458 #define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*1)      /* max. 1 drives per IDE bus */
 459
 460 #undef  AMBCTL1VAL
 461 #define AMBCTL1VAL              0xFFC3FFC3
 462
 463 #define CONFIG_CF_ATASEL_DIS    0x20311800
 464 #define CONFIG_CF_ATASEL_ENA    0x20311802
 465
 466 #if defined(CONFIG_BFIN_TRUE_IDE)
 467 /*
 468  * Note that these settings aren't for the most part used in include/ata.h
 469  * when all of the ATA registers are setup
 470  */
 471 #define CFG_ATA_BASE_ADDR       0x2031C000
 472 #define CFG_ATA_IDE0_OFFSET     0x0000
 473 #define CFG_ATA_DATA_OFFSET     0x0020  /* Offset for data I/O */
 474 #define CFG_ATA_REG_OFFSET      0x0020  /* Offset for normal register accesses */
 475 #define CFG_ATA_ALT_OFFSET      0x001C  /* Offset for alternate registers */
 476 #define CFG_ATA_STRIDE          2       /* CF.A0 --> Blackfin.Ax */
 477 #endif                          /* CONFIG_BFIN_TRUE_IDE */
 478
 479 #if defined(CONFIG_BFIN_CF_IDE) /* USE CompactFlash Storage Card in the common memory space */
 480 #define CFG_ATA_BASE_ADDR       0x20211800
 481 #define CFG_ATA_IDE0_OFFSET     0x0000
 482 #define CFG_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O */
 483 #define CFG_ATA_REG_OFFSET      0x0000  /* Offset for normal register accesses */
 484 #define CFG_ATA_ALT_OFFSET      0x000E  /* Offset for alternate registers */
 485 #define CFG_ATA_STRIDE          1       /* CF.A0 --> Blackfin.Ax */
 486 #endif                          /* CONFIG_BFIN_CF_IDE */
 487
 488 #if defined(CONFIG_BFIN_HDD_IDE)        /* USE TRUE IDE */
 489 #define CFG_ATA_BASE_ADDR       0x20314000
 490 #define CFG_ATA_IDE0_OFFSET     0x0000
 491 #define CFG_ATA_DATA_OFFSET     0x0020  /* Offset for data I/O */
 492 #define CFG_ATA_REG_OFFSET      0x0020  /* Offset for normal register accesses */
 493 #define CFG_ATA_ALT_OFFSET      0x001C  /* Offset for alternate registers */
 494 #define CFG_ATA_STRIDE          2       /* CF.A0 --> Blackfin.A1 */
 495
 496 #undef  CONFIG_SCLK_DIV
 497 #define CONFIG_SCLK_DIV         8
 498 #endif                          /* CONFIG_BFIN_HDD_IDE */
 499
 500 #endif                          /*CONFIG_BFIN_IDE */
 501
 502 #endif