include/configs/bf537-stamp.h

   1 /*
   2  * U-boot - Configuration file for BF537 STAMP board
   3  */
   4
   5 #ifndef __CONFIG_BF537_STAMP_H__
   6 #define __CONFIG_BF537_STAMP_H__
   7
   8 #include <asm/blackfin-config-pre.h>
   9
  10
  11 /*
  12  * Processor Settings
  13  */
  14 #define CONFIG_BFIN_CPU             bf537-0.2
  15 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
  16
  17
  18 /*
  19  * Clock Settings
  20  *      CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
  21  *      SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
  22  */
  23 /* CONFIG_CLKIN_HZ is any value in Hz                                   */
  24 #define CONFIG_CLKIN_HZ                 25000000
  25 /* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN             */
  26 /*                                                1 = CLKIN / 2         */
  27 #define CONFIG_CLKIN_HALF               0
  28 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass     */
  29 /*                                                1 = bypass PLL        */
  30 #define CONFIG_PLL_BYPASS               0
  31 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL              */
  32 /* Values can range from 0-63 (where 0 means 64)                        */
  33 #define CONFIG_VCO_MULT                 20
  34 /* CCLK_DIV controls the core clock divider                             */
  35 /* Values can be 1, 2, 4, or 8 ONLY                                     */
  36 #define CONFIG_CCLK_DIV                 1
  37 /* SCLK_DIV controls the system clock divider                           */
  38 /* Values can range from 1-15                                           */
  39 #define CONFIG_SCLK_DIV                 4
  40
  41
  42 /*
  43  * Memory Settings
  44  */
  45 #define CONFIG_MEM_ADD_WDTH     10
  46 #define CONFIG_MEM_SIZE         64
  47
  48 #define CONFIG_EBIU_SDRRC_VAL   0x306
  49 #define CONFIG_EBIU_SDGCTL_VAL  0x91114d
  50
  51 #define CONFIG_EBIU_AMGCTL_VAL  0xFF
  52 #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
  53 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
  54
  55 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
  56 #define CONFIG_SYS_MALLOC_LEN           (384 * 1024)
  57
  58
  59 /*
  60  * Network Settings
  61  */
  62 #ifndef __ADSPBF534__
  63 #define ADI_CMDS_NETWORK        1
  64 #define CONFIG_BFIN_MAC
  65 #define CONFIG_NETCONSOLE       1
  66 #define CONFIG_NET_MULTI        1
  67 #endif
  68 #define CONFIG_HOSTNAME         bf537-stamp
  69 /* Uncomment next line to use fixed MAC address */
  70 /* #define CONFIG_ETHADDR       02:80:ad:20:31:e8 */
  71
  72
  73 /*
  74  * Flash Settings
  75  */
  76 #define CONFIG_FLASH_CFI_DRIVER
  77 #define CONFIG_SYS_FLASH_BASE           0x20000000
  78 #define CONFIG_SYS_FLASH_CFI
  79 #define CONFIG_SYS_FLASH_PROTECTION
  80 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  81 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
  82 #define CONFIG_SYS_MAX_FLASH_SECT       71
  83
  84
  85 /*
  86  * SPI Settings
  87  */
  88 #define CONFIG_BFIN_SPI
  89 #define CONFIG_ENV_SPI_MAX_HZ   30000000
  90 #define CONFIG_SF_DEFAULT_HZ    30000000
  91 #define CONFIG_SPI_FLASH
  92 #define CONFIG_SPI_FLASH_ATMEL
  93 #define CONFIG_SPI_FLASH_SPANSION
  94 #define CONFIG_SPI_FLASH_STMICRO
  95 #define CONFIG_SPI_FLASH_WINBOND
  96
  97
  98 /*
  99  * Env Storage Settings
 100  */
 101 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
 102 #define CONFIG_ENV_IS_IN_SPI_FLASH
 103 #define CONFIG_ENV_OFFSET       0x4000
 104 #define CONFIG_ENV_SIZE         0x2000
 105 #define CONFIG_ENV_SECT_SIZE    0x2000
 106 #else
 107 #define CONFIG_ENV_IS_IN_FLASH
 108 #define CONFIG_ENV_OFFSET       0x4000
 109 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 110 #define CONFIG_ENV_SIZE         0x2000
 111 #define CONFIG_ENV_SECT_SIZE    0x2000
 112 #endif
 113 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
 114 #define ENV_IS_EMBEDDED
 115 #else
 116 #define ENV_IS_EMBEDDED_CUSTOM
 117 #endif
 118
 119
 120 /*
 121  * I2C Settings
 122  */
 123 #define CONFIG_BFIN_TWI_I2C     1
 124 #define CONFIG_HARD_I2C         1
 125 #define CONFIG_SYS_I2C_SPEED    50000
 126 #define CONFIG_SYS_I2C_SLAVE    0
 127
 128
 129 /*
 130  * SPI_MMC Settings
 131  */
 132 #define CONFIG_MMC
 133 #define CONFIG_BFIN_SPI_MMC
 134
 135
 136 /*
 137  * NAND Settings
 138  */
 139 /* #define CONFIG_BF537_NAND */
 140 #ifdef CONFIG_BF537_NAND
 141 # define CONFIG_CMD_NAND
 142 #endif
 143
 144 #define CONFIG_SYS_NAND_ADDR            0x20212000
 145 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_NAND_ADDR
 146 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 147 #define SECTORSIZE              512
 148 #define ADDR_COLUMN             1
 149 #define ADDR_PAGE               2
 150 #define ADDR_COLUMN_PAGE        3
 151 #define NAND_ChipID_UNKNOWN     0x00
 152 #define NAND_MAX_FLOORS         1
 153 #define BFIN_NAND_READY         PF3
 154
 155 #define NAND_WAIT_READY(nand) \
 156         do { \
 157                 int timeout = 0; \
 158                 while (!(*pPORTFIO & PF3)) \
 159                         if (timeout++ > 100000) \
 160                                 break; \
 161         } while (0)
 162
 163 #define BFIN_NAND_CLE           (1 << 2)        /* A2 -> Command Enable */
 164 #define BFIN_NAND_ALE           (1 << 1)        /* A1 -> Address Enable */
 165 #define WRITE_NAND_COMMAND(d, adr) bfin_write8(adr | BFIN_NAND_CLE, d)
 166 #define WRITE_NAND_ADDRESS(d, adr) bfin_write8(adr | BFIN_NAND_ALE, d)
 167 #define WRITE_NAND(d, adr)         bfin_write8(adr, d)
 168 #define READ_NAND(adr)             bfin_read8(adr)
 169
 170
 171 /*
 172  * CF-CARD IDE-HDD Support
 173  */
 174 /* #define CONFIG_BFIN_TRUE_IDE */      /* Add CF flash card support */
 175 /* #define CONFIG_BFIN_CF_IDE */        /* Add CF flash card support */
 176 /* #define CONFIG_BFIN_HDD_IDE */       /* Add IDE Disk Drive (HDD) support */
 177
 178 #if defined(CONFIG_BFIN_CF_IDE) || \
 179     defined(CONFIG_BFIN_HDD_IDE) || \
 180     defined(CONFIG_BFIN_TRUE_IDE)
 181 # define CONFIG_BFIN_IDE        1
 182 # define CONFIG_CMD_IDE
 183 #endif
 184
 185 #if defined(CONFIG_BFIN_IDE)
 186
 187 #define CONFIG_DOS_PARTITION    1
 188 /*
 189  * IDE/ATA stuff
 190  */
 191 #undef  CONFIG_IDE_8xx_DIRECT   /* no pcmcia interface required */
 192 #undef  CONFIG_IDE_LED          /* no led for ide supported */
 193 #undef  CONFIG_IDE_RESET        /* no reset for ide supported */
 194
 195 #define CONFIG_SYS_IDE_MAXBUS           1
 196 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS * 1)
 197
 198 #undef  CONFIG_EBIU_AMBCTL1_VAL
 199 #define CONFIG_EBIU_AMBCTL1_VAL         0xFFC3FFC3
 200
 201 #define CONFIG_CF_ATASEL_DIS    0x20311800
 202 #define CONFIG_CF_ATASEL_ENA    0x20311802
 203
 204 #if defined(CONFIG_BFIN_TRUE_IDE)
 205 /*
 206  * Note that these settings aren't for the most part used in include/ata.h
 207  * when all of the ATA registers are setup
 208  */
 209 #define CONFIG_SYS_ATA_BASE_ADDR        0x2031C000
 210 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 211 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0020  /* data I/O */
 212 #define CONFIG_SYS_ATA_REG_OFFSET       0x0020  /* normal register accesses */
 213 #define CONFIG_SYS_ATA_ALT_OFFSET       0x001C  /* alternate registers */
 214 #define CONFIG_SYS_ATA_STRIDE           2       /* CF.A0 --> Blackfin.Ax */
 215
 216 #elif defined(CONFIG_BFIN_CF_IDE)
 217 #define CONFIG_SYS_ATA_BASE_ADDR        0x20211800
 218 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 219 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* data I/O */
 220 #define CONFIG_SYS_ATA_REG_OFFSET       0x0000  /* normal register accesses */
 221 #define CONFIG_SYS_ATA_ALT_OFFSET       0x000E  /* alternate registers */
 222 #define CONFIG_SYS_ATA_STRIDE           1       /* CF.A0 --> Blackfin.Ax */
 223
 224 #elif defined(CONFIG_BFIN_HDD_IDE)
 225 #define CONFIG_SYS_ATA_BASE_ADDR        0x20314000
 226 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 227 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0020  /* data I/O */
 228 #define CONFIG_SYS_ATA_REG_OFFSET       0x0020  /* normal register accesses */
 229 #define CONFIG_SYS_ATA_ALT_OFFSET       0x001C  /* alternate registers */
 230 #define CONFIG_SYS_ATA_STRIDE           2       /* CF.A0 --> Blackfin.A1 */
 231 #undef  CONFIG_SCLK_DIV
 232 #define CONFIG_SCLK_DIV         8
 233 #endif
 234
 235 #endif
 236
 237
 238 /*
 239  * Misc Settings
 240  */
 241 #define CONFIG_MISC_INIT_R
 242 #define CONFIG_RTC_BFIN
 243 #define CONFIG_UART_CONSOLE     0
 244
 245 /* #define CONFIG_BF537_STAMP_LEDCMD    1 */
 246
 247 /* Define if want to do post memory test */
 248 #undef CONFIG_POST
 249 #ifdef CONFIG_POST
 250 #define FLASH_START_POST_BLOCK  11      /* Should > = 11 */
 251 #define FLASH_END_POST_BLOCK    71      /* Should < = 71 */
 252 #endif
 253
 254
 255 /*
 256  * Pull in common ADI header for remaining command/environment setup
 257  */
 258 #include <configs/bfin_adi_common.h>
 259
 260 #include <asm/blackfin-config-post.h>
 261
 262 #endif