include/configs/bf537-stamp.h

   1 /*
   2  * U-boot - Configuration file for BF537 STAMP board
   3  */
   4
   5 #ifndef __CONFIG_BF537_STAMP_H__
   6 #define __CONFIG_BF537_STAMP_H__
   7
   8 #include <asm/config-pre.h>
   9
  10
  11 /*
  12  * Processor Settings
  13  */
  14 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
  15
  16
  17 /*
  18  * Clock Settings
  19  *      CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
  20  *      SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
  21  */
  22 /* CONFIG_CLKIN_HZ is any value in Hz                                   */
  23 #define CONFIG_CLKIN_HZ                 25000000
  24 /* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN             */
  25 /*                                                1 = CLKIN / 2         */
  26 #define CONFIG_CLKIN_HALF               0
  27 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass     */
  28 /*                                                1 = bypass PLL        */
  29 #define CONFIG_PLL_BYPASS               0
  30 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL              */
  31 /* Values can range from 0-63 (where 0 means 64)                        */
  32 #define CONFIG_VCO_MULT                 20
  33 /* CCLK_DIV controls the core clock divider                             */
  34 /* Values can be 1, 2, 4, or 8 ONLY                                     */
  35 #define CONFIG_CCLK_DIV                 1
  36 /* SCLK_DIV controls the system clock divider                           */
  37 /* Values can range from 1-15                                           */
  38 #define CONFIG_SCLK_DIV                 4
  39
  40
  41 /*
  42  * Memory Settings
  43  */
  44 #define CONFIG_MEM_ADD_WDTH     10
  45 #define CONFIG_MEM_SIZE         64
  46
  47 #define CONFIG_EBIU_SDRRC_VAL   0x306
  48 #define CONFIG_EBIU_SDGCTL_VAL  0x91114d
  49
  50 #define CONFIG_EBIU_AMGCTL_VAL  0xFF
  51 #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
  52 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
  53
  54 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
  55 #define CONFIG_SYS_MALLOC_LEN           (384 * 1024)
  56
  57
  58 /*
  59  * Network Settings
  60  */
  61 #ifndef __ADSPBF534__
  62 #define ADI_CMDS_NETWORK        1
  63 #define CONFIG_BFIN_MAC
  64 #define CONFIG_NETCONSOLE       1
  65 #define CONFIG_NET_MULTI        1
  66 #endif
  67 #define CONFIG_HOSTNAME         bf537-stamp
  68 /* Uncomment next line to use fixed MAC address */
  69 /* #define CONFIG_ETHADDR       02:80:ad:20:31:e8 */
  70
  71
  72 /*
  73  * Flash Settings
  74  */
  75 #define CONFIG_FLASH_CFI_DRIVER
  76 #define CONFIG_SYS_FLASH_BASE           0x20000000
  77 #define CONFIG_SYS_FLASH_CFI
  78 #define CONFIG_SYS_FLASH_PROTECTION
  79 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  80 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
  81 #define CONFIG_SYS_MAX_FLASH_SECT       71
  82
  83
  84 /*
  85  * SPI Settings
  86  */
  87 #define CONFIG_BFIN_SPI
  88 #define CONFIG_ENV_SPI_MAX_HZ   30000000
  89 #define CONFIG_SF_DEFAULT_SPEED 30000000
  90 #define CONFIG_SPI_FLASH
  91 #define CONFIG_SPI_FLASH_ATMEL
  92 #define CONFIG_SPI_FLASH_SPANSION
  93 #define CONFIG_SPI_FLASH_STMICRO
  94 #define CONFIG_SPI_FLASH_WINBOND
  95
  96
  97 /*
  98  * Env Storage Settings
  99  */
 100 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
 101 #define CONFIG_ENV_IS_IN_SPI_FLASH
 102 #define CONFIG_ENV_OFFSET       0x10000
 103 #define CONFIG_ENV_SIZE         0x2000
 104 #define CONFIG_ENV_SECT_SIZE    0x10000
 105 #else
 106 #define CONFIG_ENV_IS_IN_FLASH
 107 #define CONFIG_ENV_OFFSET       0x4000
 108 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 109 #define CONFIG_ENV_SIZE         0x2000
 110 #define CONFIG_ENV_SECT_SIZE    0x2000
 111 #endif
 112 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
 113 #define ENV_IS_EMBEDDED
 114 #else
 115 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 116 #endif
 117 #ifdef ENV_IS_EMBEDDED
 118 /* WARNING - the following is hand-optimized to fit within
 119  * the sector before the environment sector. If it throws
 120  * an error during compilation remove an object here to get
 121  * it linked after the configuration sector.
 122  */
 123 # define LDS_BOARD_TEXT \
 124         arch/blackfin/cpu/traps.o               (.text .text.*); \
 125         arch/blackfin/cpu/interrupt.o   (.text .text.*); \
 126         arch/blackfin/cpu/serial.o              (.text .text.*); \
 127         common/dlmalloc.o               (.text .text.*); \
 128         lib/crc32.o             (.text .text.*); \
 129         . = DEFINED(env_offset) ? env_offset : .; \
 130         common/env_embedded.o           (.text .text.*);
 131 #endif
 132
 133
 134 /*
 135  * I2C Settings
 136  */
 137 #define CONFIG_BFIN_TWI_I2C     1
 138 #define CONFIG_HARD_I2C         1
 139
 140
 141 /*
 142  * SPI_MMC Settings
 143  */
 144 #define CONFIG_MMC
 145 #define CONFIG_SPI_MMC
 146
 147
 148 /*
 149  * NAND Settings
 150  */
 151 /* #define CONFIG_NAND_PLAT */
 152 #define CONFIG_SYS_NAND_BASE            0x20212000
 153 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 154
 155 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
 156 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
 157 #define BFIN_NAND_WRITE(addr, cmd) \
 158         do { \
 159                 bfin_write8(addr, cmd); \
 160                 SSYNC(); \
 161         } while (0)
 162
 163 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 164 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
 165 #define NAND_PLAT_GPIO_DEV_READY       GPIO_PF3
 166
 167
 168 /*
 169  * CF-CARD IDE-HDD Support
 170  */
 171
 172 /*
 173  * Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card)
 174  * Strange address mapping Blackfin A13 connects to CF_A0
 175  */
 176
 177 /* #define CONFIG_BFIN_TRUE_IDE */
 178
 179 /*
 180  * Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card)
 181  * This should be the preferred mode
 182  */
 183
 184 /* #define CONFIG_BFIN_CF_IDE */
 185
 186 /*
 187  * Add IDE Disk Drive (HDD) support
 188  * See example interface here:
 189  * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin
 190  */
 191
 192 /* #define CONFIG_BFIN_HDD_IDE */
 193
 194 #if defined(CONFIG_BFIN_CF_IDE) || \
 195     defined(CONFIG_BFIN_HDD_IDE) || \
 196     defined(CONFIG_BFIN_TRUE_IDE)
 197 # define CONFIG_BFIN_IDE        1
 198 # define CONFIG_CMD_IDE
 199 #endif
 200
 201 #if defined(CONFIG_BFIN_IDE)
 202
 203 #define CONFIG_DOS_PARTITION    1
 204 /*
 205  * IDE/ATA stuff
 206  */
 207 #undef  CONFIG_IDE_8xx_DIRECT   /* no pcmcia interface required */
 208 #undef  CONFIG_IDE_LED          /* no led for ide supported */
 209 #undef  CONFIG_IDE_RESET        /* no reset for ide supported */
 210
 211 #define CONFIG_SYS_IDE_MAXBUS           1
 212 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS * 1)
 213
 214 #undef  CONFIG_EBIU_AMBCTL1_VAL
 215 #define CONFIG_EBIU_AMBCTL1_VAL         0xFFC3FFC3
 216
 217 #define CONFIG_CF_ATASEL_DIS    0x20311800
 218 #define CONFIG_CF_ATASEL_ENA    0x20311802
 219
 220 #if defined(CONFIG_BFIN_TRUE_IDE)
 221 /*
 222  * Note that these settings aren't for the most part used in include/ata.h
 223  * when all of the ATA registers are setup
 224  */
 225 #define CONFIG_SYS_ATA_BASE_ADDR        0x2031C000
 226 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 227 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0020  /* data I/O */
 228 #define CONFIG_SYS_ATA_REG_OFFSET       0x0020  /* normal register accesses */
 229 #define CONFIG_SYS_ATA_ALT_OFFSET       0x001C  /* alternate registers */
 230 #define CONFIG_SYS_ATA_STRIDE           2       /* CF.A0 --> Blackfin.A13 */
 231
 232 #elif defined(CONFIG_BFIN_CF_IDE)
 233 #define CONFIG_SYS_ATA_BASE_ADDR        0x20211800
 234 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 235 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* data I/O */
 236 #define CONFIG_SYS_ATA_REG_OFFSET       0x0000  /* normal register accesses */
 237 #define CONFIG_SYS_ATA_ALT_OFFSET       0x000E  /* alternate registers */
 238 #define CONFIG_SYS_ATA_STRIDE           1       /* CF_A0=0, with /CE1 /CE2 odd/even byte selects */
 239
 240 #elif defined(CONFIG_BFIN_HDD_IDE)
 241 #define CONFIG_SYS_ATA_BASE_ADDR        0x20314000
 242 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 243 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0020  /* data I/O */
 244 #define CONFIG_SYS_ATA_REG_OFFSET       0x0020  /* normal register accesses */
 245 #define CONFIG_SYS_ATA_ALT_OFFSET       0x001C  /* alternate registers */
 246 #define CONFIG_SYS_ATA_STRIDE           2       /* CF.A0 --> Blackfin.A1 */
 247 #undef  CONFIG_SCLK_DIV
 248 #define CONFIG_SCLK_DIV         8
 249 #endif
 250
 251 #endif
 252
 253
 254 /*
 255  * Misc Settings
 256  */
 257 #define CONFIG_MISC_INIT_R
 258 #define CONFIG_RTC_BFIN
 259 #define CONFIG_UART_CONSOLE     0
 260
 261 /* Define if want to do post memory test */
 262 #undef CONFIG_POST
 263 #ifdef CONFIG_POST
 264 #define FLASH_START_POST_BLOCK  11      /* Should > = 11 */
 265 #define FLASH_END_POST_BLOCK    71      /* Should < = 71 */
 266 #endif
 267 #define CONFIG_SYS_POST_WORD_ADDR       0xFF903FFC
 268
 269 /* These are for board tests */
 270 #if 0
 271 #define CONFIG_BOOTCOMMAND       "bootldr 0x203f0100"
 272 #define CONFIG_AUTOBOOT_KEYED
 273 #define CONFIG_AUTOBOOT_PROMPT \
 274         "autoboot in %d seconds: press space to stop\n", bootdelay
 275 #define CONFIG_AUTOBOOT_STOP_STR " "
 276 #endif
 277
 278
 279 /*
 280  * Pull in common ADI header for remaining command/environment setup
 281  */
 282 #include <configs/bfin_adi_common.h>
 283
 284 #endif