include/configs/blackvme.h

   1 /* U-boot for BlackVME. (C) Wojtek Skulski 2010.
   2  * The board includes ADSP-BF561 rev. 0.5,
   3  * 32-bit SDRAM (2 * MT48LC16M16A2TG or MT48LC32M16A2TG),
   4  * Gigabit Ether AX88180 (ASIX) + 88E1111 rev. B2 (Marvell),
   5  * SPI  boot flash on PF2 (M25P64 8MB, or M25P128 16 MB),
   6  * FPGA boot flash on PF3 (M25P64 8MB, or M25P128 16 MB),
   7  * Spartan6-LX150 (memory-mapped; both PPIs also connected).
   8  * See http://www.skutek.com
   9  */
  10
  11 #ifndef __CONFIG_BLACKVME_H__
  12 #define __CONFIG_BLACKVME_H__
  13
  14 #include <asm/config-pre.h>
  15
  16 /* Debugging: Set these options if you're having problems
  17  * #define CONFIG_DEBUG_EARLY_SERIAL
  18  * #define DEBUG
  19  * #define CONFIG_DEBUG_DUMP
  20  * #define CONFIG_DEBUG_DUMP_SYMS
  21  * CONFIG_PANIC_HANG means that the board will not auto-reboot
  22  */
  23 #define CONFIG_PANIC_HANG 0
  24
  25 /* CPU Options */
  26 #define CONFIG_BFIN_BOOT_MODE   BFIN_BOOT_SPI_MASTER
  27
  28 /*
  29  *              CLOCK SETTINGS CAVEAT
  30  * You CANNOT just change the clock settings, esp. the SCLK.
  31  * The SDRAM timing, SPI baud, and the serial UART baud
  32  * use SCLK frequency to set their own frequencies. Therefore,
  33  * if you change the SCLK_DIV, you may also have to adjust
  34  * SDRAM refresh and other timings.
  35  * --------------------------------------------------------------
  36  *      CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
  37  *              25 *  8 / 1 = 200 MHz
  38  *              25 * 16 / 1 = 400 MHz
  39  *              25 * 24 / 1 = 600 MHz
  40  *      SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
  41  *              25 *  8 / 2 = 100 MHz
  42  *              25 * 24 / 6 = 100 MHz
  43  *              25 * 24 / 5 = 120 MHz
  44  *              25 * 16 / 3 = 133 MHz
  45  * 25 MHz because the oscillator also feeds the ether chip.
  46  * CONFIG_CLKIN_HZ is 25 MHz written in Hz
  47  * CLKIN_HALF controls the DF bit in PLL_CTL
  48  *      0 = CLKIN       1 = CLKIN / 2
  49  * PLL_BYPASS controls the BYPASS bit in PLL_CTL
  50  *      0 = do not bypass       1 = bypass PLL
  51  * VCO_MULT = MSEL (multiplier) in PLL_CTL
  52  * Values can range from 0-63 (where 0 means 64)
  53  * CCLK_DIV = core clock divider (1, 2, 4, or 8 ONLY)
  54  * SCLK_DIV = system clock divider, 1 to 15
  55  */
  56 #define CONFIG_CLKIN_HZ         25000000
  57 #define CONFIG_CLKIN_HALF       0
  58 #define CONFIG_PLL_BYPASS       0
  59 #define CONFIG_VCO_MULT         8
  60 #define CONFIG_CCLK_DIV         1
  61 #define CONFIG_SCLK_DIV         2
  62
  63 /*
  64  * Ether chip in async memory space AMS3, same as BF561-EZ-KIT.
  65  * Used in 32-bit mode. 16-bit mode not supported.
  66  * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
  67  */
  68 /*
  69  * Network settings using a dedicated 2nd ether card in PC
  70  * Windows will automatically acquire IP of that card
  71  * Then use the dedicated card IP + 1 for the board
  72  * http://docs.blackfin.uclinux.org/doku.php?id=setting_up_the_network
  73  */
  74 #define CONFIG_NET_MULTI
  75
  76 #define CONFIG_DRIVER_AX88180   1
  77 #define AX88180_BASE            0x2c000000
  78 #define CONFIG_CMD_MII          /* enable probing PHY */
  79
  80 #ifdef CONFIG_NET_MULTI         /* also used as the network enabler */
  81 # define CONFIG_HOSTNAME        blackvme        /* Bfin board  */
  82 # define CONFIG_IPADDR          169.254.144.145 /* Bfin board  */
  83 # define CONFIG_GATEWAYIP       169.254.144.144 /* dedic card  */
  84 # define CONFIG_SERVERIP        169.254.144.144 /* tftp server */
  85 # define CONFIG_NETMASK         255.255.255.0
  86 # define CONFIG_ROOTPATH        /export/uClinux-dist/romfs      /*NFS*/
  87 # define CFG_AUTOLOAD           "no"
  88 # define CONFIG_CMD_DHCP
  89 # define CONFIG_CMD_PING
  90 # define CONFIG_ENV_OVERWRITE   1       /* enable changing MAC at runtime */
  91 /* Comment out hardcoded MAC to enable MAC storage in EEPROM */
  92 /* # define CONFIG_ETHADDR      ff:ee:dd:cc:bb:aa */
  93 #endif
  94
  95 /*
  96  * SDRAM settings & memory map
  97  */
  98
  99 #define CONFIG_MEM_SIZE         64      /* 128, 64, 32, 16 */
 100 #define CONFIG_MEM_ADD_WDTH      9      /* 8, 9, 10, 11    */
 101 /*
 102  * SDRAM reference page
 103  * http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 104  * NOTE: BlackVME populates only SDRAM bank 0
 105  */
 106 /* CONFIG_EBIU_SDBCTL_VAL bank ctrl may be needed in future */
 107 #define CONFIG_EBIU_SDGCTL_VAL  0x91114d  /* global control */
 108 #define CONFIG_EBIU_SDRRC_VAL   0x306     /* refresh rate */
 109
 110 /* Async memory global settings. (ASRAM, not SDRAM)
 111  * HRM page 16-10. Global ASRAM control = 0x3F. Six lower bits = 1
 112  * CLKOUT enabled, all async banks enabled, core has priority
 113  * bank 0&1 16 bit (FPGA)
 114  * bank 2&3 32 bit (ether and USB chips)
 115  */
 116 #define CONFIG_EBIU_AMGCTL_VAL  0x3F   /* ASRAM setup */
 117
 118 /* Async mem timing: BF561 HRM page 16-12 and 16-15.
 119  * Default values 0xFFC2 FFC2 are the slowest supported.
 120  * Example settings of CONFIG_EBIU_AMBCTL1_VAL
 121  * 1. EZ-KIT settings: 0xFFC2 7BB0
 122  * 2. Bank 3 good timing for AX88180 @ 125MHz = 0x8850 xxxx
 123  *    See the following page:
 124  *    http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
 125  * 3. Bank 3 timing for AX88180 @ SCLK = 100 MHz:
 126  * AX88180  WEN = 5 clocks  REN 6 clocks @ SCLK = 100 MHz
 127  * One extra clock needed because AX88180 is asynchronous to CPU.
 128  */
 129                            /* bank 1   0 */
 130 #define CONFIG_EBIU_AMBCTL0_VAL 0xFFC2FFC2
 131                            /* bank 3   2 */
 132 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC2FFC2
 133
 134 /* memory layout */
 135
 136 #define CONFIG_SYS_MONITOR_LEN  (256 << 10)
 137 #define CONFIG_SYS_MALLOC_LEN   (384 << 10)
 138
 139 /*
 140  * Serial SPI Flash
 141  * For the M25P64 SCK should be kept < 15 MHz
 142  */
 143 #define CONFIG_BFIN_SPI
 144 #define CONFIG_ENV_IS_IN_SPI_FLASH
 145 #define CONFIG_ENV_OFFSET       0x40000
 146 #define CONFIG_ENV_SIZE         0x2000
 147 #define CONFIG_ENV_SECT_SIZE    0x40000
 148
 149 #define CONFIG_ENV_SPI_MAX_HZ   15000000
 150 #define CONFIG_SF_DEFAULT_SPEED 15000000
 151 #define CONFIG_SPI_FLASH
 152 #define CONFIG_SPI_FLASH_STMICRO
 153
 154 /*
 155  * Interactive command settings
 156  */
 157
 158 #define CONFIG_SYS_LONGHELP     1
 159 #define CONFIG_CMDLINE_EDITING  1
 160 #define CONFIG_AUTO_COMPLETE    1
 161
 162 #include <config_cmd_default.h>
 163
 164 #define CONFIG_CMD_BOOTLDR
 165 #define CONFIG_CMD_CACHE
 166 #define CONFIG_CMD_CPLBINFO
 167 #define CONFIG_CMD_SF
 168 #define CONFIG_CMD_ELF
 169
 170 /*
 171  * Default: boot from SPI flash.
 172  * "sfboot" is a composite command defined in extra settings
 173  */
 174 #define CONFIG_BOOTDELAY        5
 175 #define CONFIG_BOOTCOMMAND      "run sfboot"
 176
 177 /*
 178  * Console settings
 179  */
 180 #define CONFIG_BAUDRATE         57600
 181 #define CONFIG_LOADS_ECHO       1
 182 #define CONFIG_UART_CONSOLE     0
 183
 184 /*
 185  * U-Boot environment variables. Use "printenv" to examine.
 186  * http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:env
 187  */
 188 #define CONFIG_BOOTARGS \
 189         "root=/dev/mtdblock0 rw " \
 190         "clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \
 191         "earlyprintk=serial,uart0," \
 192         MK_STR(CONFIG_BAUDRATE) " " \
 193         "console=ttyBF0," MK_STR(CONFIG_BAUDRATE) " "
 194
 195 /* Convenience env variables & commands.
 196  * Reserve kernstart = 0x20000  = 128 kB for U-Boot.
 197  * Reserve kernarea  = 0x500000 = 5 MB   for kernel (reasonable size).
 198  * U-Boot image is saved at flash offset=0.
 199  * Kernel image is saved at flash offset=$kernstart.
 200  * Instructions. Ksave takes about a minute to complete.
 201  *      1. Update U-Boot: run uget; run usave
 202  *      2. Update kernel: run kget; run ksave
 203  * After updating U-Boot also update the kernel per above instructions
 204  * to make the saved environment consistent with the flash.
 205  */
 206 #define CONFIG_EXTRA_ENV_SETTINGS \
 207         "kernstart=0x20000\0" \
 208         "kernarea=0x500000\0" \
 209         "uget=tftp u-boot.ldr\0" \
 210         "kget=tftp uImage\0" \
 211         "usave=sf probe 2; " \
 212                 "sf erase 0 $(kernstart); " \
 213                 "sf write $(fileaddr) 0 $(filesize)\0" \
 214         "ksave=sf probe 2; " \
 215                 "saveenv; " \
 216                 "echo Now patiently wait for the prompt...; " \
 217                 "sf erase $(kernstart) $(kernarea); " \
 218                 "sf write $(fileaddr) $(kernstart) $(filesize)\0" \
 219         "sfboot=sf probe 2; " \
 220                 "sf read $(loadaddr) $(kernstart) $(filesize); " \
 221                 "run addip; bootm\0" \
 222         "addip=setenv bootargs $(bootargs) " \
 223         "ip=$(ipaddr):$(serverip):$(gatewayip):" \
 224                 "$(netmask):$(hostname):eth0:off\0"
 225
 226 /*
 227  * Soft I2C settings (BF561 does not have hard I2C)
 228  * PF12,13 on SPI connector 0.
 229  */
 230 #ifdef CONFIG_SOFT_I2C
 231 # define CONFIG_CMD_I2C
 232 # define CONFIG_SOFT_I2C_GPIO_SCL       GPIO_PF12
 233 # define CONFIG_SOFT_I2C_GPIO_SDA       GPIO_PF13
 234 # define CONFIG_SYS_I2C_SPEED           50000
 235 # define CONFIG_SYS_I2C_SLAVE           0xFE
 236 #endif
 237
 238 /*
 239  * No Parallel Flash on this board
 240  */
 241 #define CONFIG_SYS_NO_FLASH
 242 #undef CONFIG_CMD_IMLS
 243 #undef CONFIG_CMD_JFFS2
 244 #undef CONFIG_CMD_FLASH
 245
 246 #endif