include/configs/bubinga.h

   1 /*
   2  * (C) Copyright 2000-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  21 #define CONFIG_BUBINGA          1       /* ...on a BUBINGA board        */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  24
  25 /*
  26  * Include common defines/options for all AMCC eval boards
  27  */
  28 #define CONFIG_HOSTNAME         bubinga
  29 #include "amcc-common.h"
  30
  31 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  32
  33 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  34
  35 #define CONFIG_NO_SERIAL_EEPROM
  36 /*#undef CONFIG_NO_SERIAL_EEPROM*/
  37 /*----------------------------------------------------------------------------*/
  38 #ifdef CONFIG_NO_SERIAL_EEPROM
  39
  40 /*
  41 !-------------------------------------------------------------------------------
  42 ! Defines for entry options.
  43 ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
  44 !       are plugged in the board will be utilized as non-ECC DIMMs.
  45 !-------------------------------------------------------------------------------
  46 */
  47 #define        AUTO_MEMORY_CONFIG
  48 #define        DIMM_READ_ADDR 0xAB
  49 #define        DIMM_WRITE_ADDR 0xAA
  50
  51 /*
  52 !-------------------------------------------------------------------------------
  53 ! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
  54 ! assuming a 33MHz input clock to the 405EP from the C9531.
  55 !-------------------------------------------------------------------------------
  56 */
  57 #define PLLMR0_DEFAULT   PLLMR0_266_133_66
  58 #define PLLMR1_DEFAULT   PLLMR1_266_133_66
  59
  60 #endif
  61 /*----------------------------------------------------------------------------*/
  62
  63 /*
  64  * Define here the location of the environment variables (FLASH or NVRAM).
  65  * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
  66  *       supported for backward compatibility.
  67  */
  68 #if 1
  69 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
  70 #else
  71 #define CONFIG_ENV_IS_IN_NVRAM  1       /* use NVRAM for environment vars       */
  72 #endif
  73
  74 /*
  75  * Default environment variables
  76  */
  77 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  78         CONFIG_AMCC_DEF_ENV                                             \
  79         CONFIG_AMCC_DEF_ENV_PPC                                         \
  80         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
  81         "kernel_addr=fff80000\0"                                        \
  82         "ramdisk_addr=fff90000\0"                                       \
  83         ""
  84
  85 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
  86 #define CONFIG_HAS_ETH0
  87 #define CONFIG_HAS_ETH1
  88 #define CONFIG_PHY1_ADDR        2       /* EMAC1 PHY address            */
  89
  90 #define CONFIG_RTC_DS174x       1       /* use DS1743 RTC in Bubinga    */
  91
  92 /*
  93  * Commands additional to the ones defined in amcc-common.h
  94  */
  95 #define CONFIG_CMD_DATE
  96 #define CONFIG_CMD_PCI
  97 #define CONFIG_CMD_SDRAM
  98
  99 #define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
 100
 101 /*
 102  * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
 103  * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
 104  * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
 105  * The Linux BASE_BAUD define should match this configuration.
 106  *    baseBaud = cpuClock/(uartDivisor*16)
 107  * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
 108  * set Linux BASE_BAUD to 403200.
 109  */
 110 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 111 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
 112 #undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
 113 #define CONFIG_SYS_BASE_BAUD       691200
 114
 115 /*-----------------------------------------------------------------------
 116  * I2C stuff
 117  *-----------------------------------------------------------------------
 118  */
 119 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 120
 121 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }   /* avoid i2c probe hangup (?) */
 122 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   6       /* 24C02 requires 5ms delay */
 123
 124 #if defined(CONFIG_CMD_EEPROM)
 125 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* I2C boot EEPROM (24C02W)     */
 126 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1       /* Bytes of address             */
 127 #endif
 128
 129 /*-----------------------------------------------------------------------
 130  * PCI stuff
 131  *-----------------------------------------------------------------------
 132  */
 133 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 134 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 135 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 136
 137 #define CONFIG_PCI                      /* include pci support          */
 138 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 139 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 140 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 141                                         /* resource configuration       */
 142 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 143
 144 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC */
 145 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever */
 146 #define CONFIG_SYS_PCI_CLASSCODE       0x0600  /* PCI Class Code: bridge/host  */
 147 #define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
 148 #define CONFIG_SYS_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
 149 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 150 #define CONFIG_SYS_PCI_PTM2LA  0x00000000      /* disabled                     */
 151 #define CONFIG_SYS_PCI_PTM2MS  0x00000000      /* disabled                     */
 152 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 153
 154 /*-----------------------------------------------------------------------
 155  * External peripheral base address
 156  *-----------------------------------------------------------------------
 157  */
 158 #define CONFIG_SYS_KEY_REG_BASE_ADDR    0xF0100000
 159 #define CONFIG_SYS_IR_REG_BASE_ADDR     0xF0200000
 160 #define CONFIG_SYS_FPGA_REG_BASE_ADDR   0xF0300000
 161
 162 /*-----------------------------------------------------------------------
 163  * Start addresses for the final memory configuration
 164  * (Set up by the startup code)
 165  */
 166 #define CONFIG_SYS_SRAM_BASE            0xFFF00000
 167 #define CONFIG_SYS_SRAM_SIZE            (256 << 10)
 168 #define CONFIG_SYS_FLASH_BASE           0xFFF80000
 169
 170 /*-----------------------------------------------------------------------
 171  * FLASH organization
 172  */
 173 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 174 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 175
 176 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 177 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 178
 179 #define CONFIG_SYS_FLASH_ADDR0         0x5555
 180 #define CONFIG_SYS_FLASH_ADDR1         0x2aaa
 181 #define CONFIG_SYS_FLASH_WORD_SIZE     unsigned char
 182
 183 #ifdef CONFIG_ENV_IS_IN_FLASH
 184 #define CONFIG_ENV_SECT_SIZE    0x10000 /* size of one complete sector  */
 185 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 186 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 187
 188 /* Address and size of Redundant Environment Sector     */
 189 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 190 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 191 #endif /* CONFIG_ENV_IS_IN_FLASH */
 192
 193 /*-----------------------------------------------------------------------
 194  * NVRAM organization
 195  */
 196 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xf0000000      /* NVRAM base address   */
 197 #define CONFIG_SYS_NVRAM_SIZE           0x1ff8          /* NVRAM size   */
 198
 199 #ifdef CONFIG_ENV_IS_IN_NVRAM
 200 #define CONFIG_ENV_SIZE         0x0ff8          /* Size of Environment vars     */
 201 #define CONFIG_ENV_ADDR         \
 202         (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)      /* Env  */
 203 #endif
 204
 205 /*
 206  * Init Memory Controller:
 207  *
 208  * BR0/1 and OR0/1 (FLASH)
 209  */
 210
 211 #define FLASH_BASE0_PRELIM      CONFIG_SYS_FLASH_BASE   /* FLASH bank #0        */
 212 #define FLASH_BASE1_PRELIM      0               /* FLASH bank #1        */
 213
 214 /*-----------------------------------------------------------------------
 215  * Definitions for initial stack pointer and data area (in data cache)
 216  */
 217 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 218 #define CONFIG_SYS_TEMP_STACK_OCM        1
 219
 220 /* On Chip Memory location */
 221 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 222 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 223 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 224 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 225
 226 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 227 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 228
 229 /*-----------------------------------------------------------------------
 230  * External Bus Controller (EBC) Setup
 231  */
 232
 233 /* Memory Bank 0 (Flash/SRAM) initialization                                    */
 234 #define CONFIG_SYS_EBC_PB0AP           0x04006000
 235 #define CONFIG_SYS_EBC_PB0CR           0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit  */
 236
 237 /* Memory Bank 1 (NVRAM/RTC) initialization                                     */
 238 #define CONFIG_SYS_EBC_PB1AP           0x04041000
 239 #define CONFIG_SYS_EBC_PB1CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 240
 241 /* Memory Bank 2 (not used) initialization                                      */
 242 #define CONFIG_SYS_EBC_PB2AP           0x00000000
 243 #define CONFIG_SYS_EBC_PB2CR           0x00000000
 244
 245 /* Memory Bank 2 (not used) initialization                                      */
 246 #define CONFIG_SYS_EBC_PB3AP           0x00000000
 247 #define CONFIG_SYS_EBC_PB3CR           0x00000000
 248
 249 /* Memory Bank 4 (FPGA regs) initialization                                     */
 250 #define CONFIG_SYS_EBC_PB4AP           0x01815000
 251 #define CONFIG_SYS_EBC_PB4CR           0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
 252
 253 /*-----------------------------------------------------------------------
 254  * Definitions for Serial Presence Detect EEPROM address
 255  * (to get SDRAM settings)
 256  */
 257 #define SPD_EEPROM_ADDRESS      0x55
 258
 259 /*-----------------------------------------------------------------------
 260  * Definitions for GPIO setup (PPC405EP specific)
 261  *
 262  * GPIO0[0]     - External Bus Controller BLAST output
 263  * GPIO0[1-9]   - Instruction trace outputs
 264  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 265  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
 266  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 267  * GPIO0[24-27] - UART0 control signal inputs/outputs
 268  * GPIO0[28-29] - UART1 data signal input/output
 269  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 270  */
 271 #define CONFIG_SYS_GPIO0_OSRL          0x55555555
 272 #define CONFIG_SYS_GPIO0_OSRH          0x40000110
 273 #define CONFIG_SYS_GPIO0_ISR1L         0x00000000
 274 #define CONFIG_SYS_GPIO0_ISR1H         0x15555445
 275 #define CONFIG_SYS_GPIO0_TSRL          0x00000000
 276 #define CONFIG_SYS_GPIO0_TSRH          0x00000000
 277 #define CONFIG_SYS_GPIO0_TCR           0xFFFF8014
 278
 279 /*-----------------------------------------------------------------------
 280  * Some BUBINGA stuff...
 281  */
 282 #define NVRAM_BASE      0xF0000000
 283 #define FPGA_REG0       0xF0300000    /* FPGA Reg 0              */
 284 #define FPGA_REG1       0xF0300001    /* FPGA Reg 1              */
 285 #define NVRVFY1     0x4f532d4f    /* used to determine if state data in */
 286 #define NVRVFY2     0x50454e00    /* NVRAM initialized (ascii for OS-OPEN)*/
 287
 288 #define FPGA_REG0_F_RANGE     0x80       /* SDRAM PLL freq range              */
 289 #define FPGA_REG0_EXT_INT_DIS 0x20       /* External interface disable        */
 290 #define FPGA_REG0_LED_MASK    0x07       /* Board LEDs DS9, DS10, and DS11    */
 291 #define FPGA_REG0_LED0        0x04       /* Turn on LED0                      */
 292 #define FPGA_REG0_LED1        0x02       /* Turn on LED1                      */
 293 #define FPGA_REG0_LED2        0x01       /* Turn on LED2                      */
 294
 295 #define FPGA_REG1_SSPEC_DIS   0x80       /* C9531 Spread Spectrum disabled    */
 296 #define FPGA_REG1_OFFBD_PCICLK 0x40      /* Onboard PCI clock selected       */
 297 #define FPGA_REG1_CLOCK_MASK  0x30       /* Mask for C9531 output freq select */
 298 #define FPGA_REG1_CLOCK_BIT_SHIFT  4
 299 #define FPGA_REG1_PCI_INT_ARB 0x08       /* PCI Internal arbiter selected     */
 300 #define FPGA_REG1_PCI_FREQ    0x04       /* PCI Frequency select              */
 301 #define FPGA_REG1_OFFB_FLASH  0x02       /* Off board flash                   */
 302 #define FPGA_REG1_SRAM_BOOT   0x01       /* SRAM at 0xFFF80000 not Flash      */
 303
 304 #endif  /* __CONFIG_H */