include/configs/c2mon.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC855           1       /* This is a MPC855 CPU         */
  37 #define CONFIG_C2MON            1       /* ...on a C2MON module         */
  38
  39 #define CONFIG_SYS_TEXT_BASE    0x40000000
  40
  41 #define CONFIG_80MHz            1       /* Running at 5 * 16 = 80 MHz   */
  42
  43 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  44 #undef  CONFIG_8xx_CONS_SMC2
  45 #undef  CONFIG_8xx_CONS_NONE
  46 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  47 #if 0
  48 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  49 #else
  50 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  51 #endif
  52
  53 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  54
  55 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  56
  57 #undef  CONFIG_BOOTARGS
  58 #define CONFIG_BOOTCOMMAND                                                      \
  59         "bootp; "                                                               \
  60         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  61         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
  62         "bootm"
  63
  64 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  65 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  66
  67 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  68
  69 #undef  CONFIG_STATUS_LED               /* Status LED disabled          */
  70
  71 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  72
  73 /*
  74  * BOOTP options
  75  */
  76 #define CONFIG_BOOTP_SUBNETMASK
  77 #define CONFIG_BOOTP_GATEWAY
  78 #define CONFIG_BOOTP_HOSTNAME
  79 #define CONFIG_BOOTP_BOOTPATH
  80 #define CONFIG_BOOTP_BOOTFILESIZE
  81
  82
  83 #define CONFIG_MAC_PARTITION
  84 #define CONFIG_DOS_PARTITION
  85
  86 #define CONFIG_FEC_ENET         1       /* Use Fast Ethernet Controller */
  87
  88 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  89
  90
  91 /*
  92  * Command line configuration.
  93  */
  94 #include <config_cmd_default.h>
  95
  96 #define CONFIG_CMD_DATE
  97 #define CONFIG_CMD_DHCP
  98 #define CONFIG_CMD_IDE
  99 #define CONFIG_CMD_NFS
 100 #define CONFIG_CMD_SNTP
 101
 102
 103 /*
 104  * Miscellaneous configurable options
 105  */
 106 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 107 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 108
 109 #undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
 110 #ifdef  CONFIG_SYS_HUSH_PARSER
 111 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 112 #endif
 113
 114 #if defined(CONFIG_CMD_KGDB)
 115 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 116 #else
 117 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 118 #endif
 119 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 120 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 121 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 122
 123 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 124 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 125
 126 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 127
 128 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 129
 130 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 131
 132 /*
 133  * Low Level Configuration Settings
 134  * (address mappings, register initial values, etc.)
 135  * You should know what you are doing if you make changes here.
 136  */
 137 /*-----------------------------------------------------------------------
 138  * Internal Memory Mapped Register
 139  */
 140 #define CONFIG_SYS_IMMR         0xFFF00000
 141
 142 /*-----------------------------------------------------------------------
 143  * Definitions for initial stack pointer and data area (in DPRAM)
 144  */
 145 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 146 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 147 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 148 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 149
 150 /*-----------------------------------------------------------------------
 151  * Start addresses for the final memory configuration
 152  * (Set up by the startup code)
 153  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 154  */
 155 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 156 #define CONFIG_SYS_FLASH_BASE           0x40000000
 157 #if defined(DEBUG)
 158 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 159 #else
 160 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 161 #endif
 162 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 163 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 164
 165 /*
 166  * For booting Linux, the board info and command line data
 167  * have to be in the first 8 MB of memory, since this is
 168  * the maximum mapped by the Linux kernel during initialization.
 169  */
 170 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 171
 172 /*-----------------------------------------------------------------------
 173  * FLASH organization
 174  */
 175 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 176 #define CONFIG_SYS_MAX_FLASH_SECT       67      /* max number of sectors on one chip    */
 177
 178 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 179 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 180
 181 #define CONFIG_ENV_IS_IN_FLASH  1
 182 #define CONFIG_ENV_OFFSET               0x8000  /*   Offset   of Environment Sector     */
 183 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 184
 185 /*-----------------------------------------------------------------------
 186  * Cache Configuration
 187  */
 188 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 189 #if defined(CONFIG_CMD_KGDB)
 190 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 191 #endif
 192
 193 /*-----------------------------------------------------------------------
 194  * SYPCR - System Protection Control                            11-9
 195  * SYPCR can only be written once after reset!
 196  *-----------------------------------------------------------------------
 197  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 198  */
 199 #if defined(CONFIG_WATCHDOG)
 200 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 201                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 202 #else
 203 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 204 #endif
 205
 206 /*-----------------------------------------------------------------------
 207  * SIUMCR - SIU Module Configuration                            11-6
 208  *-----------------------------------------------------------------------
 209  * PCMCIA config., multi-function pin tri-state
 210  */
 211 #ifndef CONFIG_CAN_DRIVER
 212 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 213 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 214 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 215 #endif  /* CONFIG_CAN_DRIVER */
 216
 217 /*-----------------------------------------------------------------------
 218  * TBSCR - Time Base Status and Control                         11-26
 219  *-----------------------------------------------------------------------
 220  * Clear Reference Interrupt Status, Timebase freezing enabled
 221  */
 222 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 223
 224 /*-----------------------------------------------------------------------
 225  * RTCSC - Real-Time Clock Status and Control Register          11-27
 226  *-----------------------------------------------------------------------
 227  */
 228 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 229
 230 /*-----------------------------------------------------------------------
 231  * PISCR - Periodic Interrupt Status and Control                11-31
 232  *-----------------------------------------------------------------------
 233  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 234  */
 235 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 236
 237 /*-----------------------------------------------------------------------
 238  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 239  *-----------------------------------------------------------------------
 240  * Reset PLL lock status sticky bit, timer expired status bit and timer
 241  * interrupt status bit
 242  *
 243  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 244  */
 245 #ifdef  CONFIG_80MHz    /* for 80 MHz, we use a 16 MHz clock * 5 */
 246 #define CONFIG_SYS_PLPRCR                                                       \
 247                 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
 248 #else                   /* up to 50 MHz we use a 1:1 clock */
 249 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 250 #endif  /* CONFIG_80MHz */
 251
 252 /*-----------------------------------------------------------------------
 253  * SCCR - System Clock and reset Control Register               15-27
 254  *-----------------------------------------------------------------------
 255  * Set clock output, timebase and RTC source and divider,
 256  * power management and some other internal clocks
 257  */
 258 #define SCCR_MASK       SCCR_EBDF11
 259 #ifdef  CONFIG_80MHz    /* for 80 MHz, we use a 16 MHz clock * 5 */
 260 #define CONFIG_SYS_SCCR (/* SCCR_TBS  | */ \
 261                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 262                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 263                          SCCR_DFALCD00)
 264 #else                   /* up to 50 MHz we use a 1:1 clock */
 265 #define CONFIG_SYS_SCCR (SCCR_TBS     | \
 266                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 267                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 268                          SCCR_DFALCD00)
 269 #endif  /* CONFIG_80MHz */
 270
 271 /*-----------------------------------------------------------------------
 272  * PCMCIA stuff
 273  *-----------------------------------------------------------------------
 274  *
 275  */
 276 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 277 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 278 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 279 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 280 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 281 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 282 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 283 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 284
 285 /*-----------------------------------------------------------------------
 286  * PCMCIA Power Switch
 287  *
 288  * The C2MON uses a TPS2211A PC-Card Power-Interface Switch to
 289  * control the voltages on the PCMCIA slot which is connected
 290  * to Port C (all outputs) and Port B (Over-Current Input)
 291  *-----------------------------------------------------------------------
 292  */
 293                         /* Output pins */
 294 #define TPS2211_VCCD0   0x0002          /* PC.14 */
 295 #define TPS2211_VCCD1   0x0004          /* PC.13 */
 296 #define TPS2211_VPPD0   0x0008          /* PC.12 */
 297 #define TPS2211_VPPD1   0x0010          /* PC.11 */
 298 #define TPS2211_OUTPUTS ( TPS2211_VCCD0 | TPS2211_VCCD1 | \
 299                           TPS2211_VPPD0 | TPS2211_VPPD1 )
 300
 301                         /* Input pins */
 302 #define TPS2211_OC      0x00000200      /* PB.22: Over-Current          */
 303 #define TPS2211_INPUTS  ( TPS2211_OC )
 304
 305 /*-----------------------------------------------------------------------
 306  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 307  *-----------------------------------------------------------------------
 308  */
 309
 310 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 311
 312 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 313 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 314 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 315
 316 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 317 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 318
 319 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 320
 321 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 322
 323 /* Offset for data I/O                  */
 324 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 325
 326 /* Offset for normal register accesses  */
 327 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 328
 329 /* Offset for alternate registers       */
 330 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 331
 332
 333 /*-----------------------------------------------------------------------
 334  *
 335  *-----------------------------------------------------------------------
 336  *
 337  */
 338 #define CONFIG_SYS_DER  0
 339
 340 /*
 341  * Init Memory Controller:
 342  *
 343  * BR0/1 and OR0/1 (FLASH)
 344  */
 345
 346 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 347 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 348
 349 /* used to re-map FLASH both when starting from SRAM or FLASH:
 350  * restrict access enough to keep SRAM working (if any)
 351  * but not too much to meddle with FLASH accesses
 352  */
 353 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 354 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 355
 356 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1        */
 357 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
 358                                  OR_SCY_5_CLK | OR_EHTR)
 359
 360 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 361 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 362 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 363
 364 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 365 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 366 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 367
 368 /*
 369  * BR2/3 and OR2/3 (SDRAM)
 370  *
 371  */
 372 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 373 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 374 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 375
 376 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 377 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 378
 379 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 380 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 381
 382 #ifndef CONFIG_CAN_DRIVER
 383 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 384 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 385 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 386 #define CONFIG_SYS_CAN_BASE             0xC0000000      /* CAN mapped at 0xC0000000     */
 387 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 kB address mask           */
 388 #define CONFIG_SYS_OR3_CAN              (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
 389 #define CONFIG_SYS_BR3_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 390                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 391 #endif  /* CONFIG_CAN_DRIVER */
 392
 393 /*
 394  * Memory Periodic Timer Prescaler
 395  */
 396
 397 /* periodic timer for refresh */
 398 #define CONFIG_SYS_MAMR_PTA     97              /* start with divider for 100 MHz       */
 399
 400 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 401 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 402 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 403
 404 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 405 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 406 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 407
 408 /*
 409  * MAMR settings for SDRAM
 410  */
 411
 412 /* 8 column SDRAM */
 413 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 414                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 415                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 416 /* 9 column SDRAM */
 417 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 418                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 419                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 420
 421 #endif  /* __CONFIG_H */