include/configs/cam_enc_4xx.h

   1 /*
   2  * Copyright (C) 2009 Texas Instruments Incorporated
   3  *
   4  * Copyright (C) 2011
   5  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #ifndef __CONFIG_H
  24 #define __CONFIG_H
  25
  26 #define CONFIG_SYS_NO_FLASH             /* that is, no *NOR* flash */
  27 #define CONFIG_SYS_CONSOLE_INFO_QUIET
  28
  29 /* SoC Configuration */
  30 #define CONFIG_ARM926EJS                                /* arm926ejs CPU */
  31 #define CONFIG_SYS_TIMERBASE            0x01c21400      /* use timer 0 */
  32 #define CONFIG_SYS_HZ_CLOCK             24000000        /* timer0 freq */
  33 #define CONFIG_SYS_HZ                   1000
  34 #define CONFIG_SOC_DM365
  35
  36 #define CONFIG_MACH_TYPE        MACH_TYPE_DAVINCI_DM365_EVM
  37
  38 #define CONFIG_HOSTNAME                 cam_enc_4xx
  39
  40 #define BOARD_LATE_INIT
  41 #define CONFIG_CAM_ENC_LED_MASK         0x0fc00000
  42
  43 /* Memory Info */
  44 #define CONFIG_NR_DRAM_BANKS            1
  45 #define PHYS_SDRAM_1                    0x80000000
  46 #define PHYS_SDRAM_1_SIZE               (256 << 20)     /* 256 MiB */
  47 #define DDR_4BANKS                              /* 4-bank DDR2 (256MB) */
  48 #define CONFIG_MAX_RAM_BANK_SIZE        (256 << 20)     /* 256 MB */
  49 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  50
  51 /* Serial Driver info: UART0 for console  */
  52 #define CONFIG_SYS_NS16550
  53 #define CONFIG_SYS_NS16550_SERIAL
  54 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  55 #define CONFIG_SYS_NS16550_COM1         0x01c20000
  56 #define CONFIG_SYS_NS16550_CLK          CONFIG_SYS_HZ_CLOCK
  57 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  58 #define CONFIG_CONS_INDEX               1
  59 #define CONFIG_BAUDRATE                 115200
  60
  61 /* Network Configuration */
  62 #define CONFIG_DRIVER_TI_EMAC
  63 #define CONFIG_EMAC_MDIO_PHY_NUM        0
  64 #define CONFIG_SYS_EMAC_TI_CLKDIV       0xa9    /* 1MHz */
  65 #define CONFIG_MII
  66 #define CONFIG_BOOTP_DEFAULT
  67 #define CONFIG_BOOTP_DNS
  68 #define CONFIG_BOOTP_DNS2
  69 #define CONFIG_BOOTP_SEND_HOSTNAME
  70 #define CONFIG_NET_RETRY_COUNT  10
  71 #define CONFIG_NET_MULTI
  72 #define CONFIG_CMD_MII
  73 #define CONFIG_SYS_DCACHE_OFF
  74 #define CONFIG_RESET_PHY_R
  75
  76 /* I2C */
  77 #define CONFIG_HARD_I2C
  78 #define CONFIG_DRIVER_DAVINCI_I2C
  79 #define CONFIG_SYS_I2C_SPEED            400000
  80 #define CONFIG_SYS_I2C_SLAVE            0x10    /* SMBus host address */
  81
  82 /* NAND: socketed, two chipselects, normally 2 GBytes */
  83 #define CONFIG_NAND_DAVINCI
  84 #define CONFIG_SYS_NAND_CS              2
  85 #define CONFIG_SYS_NAND_USE_FLASH_BBT
  86 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
  87 #define CONFIG_SYS_NAND_PAGE_2K
  88
  89 #define CONFIG_SYS_NAND_LARGEPAGE
  90 #define CONFIG_SYS_NAND_BASE_LIST       { 0x02000000, }
  91 /* socket has two chipselects, nCE0 gated by address BIT(14) */
  92 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  93
  94 /* SPI support */
  95 #define CONFIG_SPI
  96 #define CONFIG_SPI_FLASH
  97 #define CONFIG_SPI_FLASH_STMICRO
  98 #define CONFIG_DAVINCI_SPI
  99 #define CONFIG_SYS_SPI_BASE             DAVINCI_SPI1_BASE
 100 #define CONFIG_SYS_SPI_CLK              davinci_clk_get(SPI_PLLDIV)
 101 #define CONFIG_SF_DEFAULT_SPEED         3000000
 102 #define CONFIG_ENV_SPI_MAX_HZ           CONFIG_SF_DEFAULT_SPEED
 103 #define CONFIG_CMD_SF
 104
 105 /* SD/MMC */
 106 #define CONFIG_MMC
 107 #define CONFIG_GENERIC_MMC
 108 #define CONFIG_DAVINCI_MMC
 109 #define CONFIG_MMC_MBLOCK
 110
 111 /* U-Boot command configuration */
 112 #include <config_cmd_default.h>
 113
 114 #define CONFIG_CMD_BDI
 115 #undef CONFIG_CMD_FLASH
 116 #undef CONFIG_CMD_FPGA
 117 #undef CONFIG_CMD_SETGETDCR
 118 #define CONFIG_CMD_ASKENV
 119 #define CONFIG_CMD_CACHE
 120 #define CONFIG_CMD_DHCP
 121 #define CONFIG_CMD_I2C
 122 #define CONFIG_CMD_PING
 123 #define CONFIG_CMD_SAVES
 124
 125 #ifdef CONFIG_MMC
 126 #define CONFIG_DOS_PARTITION
 127 #define CONFIG_CMD_EXT2
 128 #define CONFIG_CMD_FAT
 129 #define CONFIG_CMD_MMC
 130 #endif
 131
 132 #ifdef CONFIG_NAND_DAVINCI
 133 #define CONFIG_CMD_MTDPARTS
 134 #define CONFIG_MTD_PARTITIONS
 135 #define CONFIG_MTD_DEVICE
 136 #define CONFIG_CMD_NAND
 137 #define CONFIG_CMD_UBI
 138 #define CONFIG_RBTREE
 139 #endif
 140
 141 #define CONFIG_CRC32_VERIFY
 142 #define CONFIG_MX_CYCLIC
 143
 144 /* U-Boot general configuration */
 145 #undef CONFIG_USE_IRQ                           /* No IRQ/FIQ in U-Boot */
 146 #define CONFIG_BOOTFILE         "uImage"        /* Boot file name */
 147 #define CONFIG_SYS_PROMPT       "cam_enc_4xx> " /* Monitor Command Prompt */
 148 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size  */
 149 #define CONFIG_SYS_PBSIZE                       /* Print buffer size */ \
 150                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 151 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 152 #define CONFIG_SYS_HUSH_PARSER
 153 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 154 #define CONFIG_SYS_LONGHELP
 155
 156 #ifdef CONFIG_NAND_DAVINCI
 157 #define CONFIG_ENV_SIZE         (256 << 10)     /* 256 KiB */
 158 #define CONFIG_ENV_IS_IN_NAND
 159 #define CONFIG_ENV_OFFSET       0x0
 160 #undef CONFIG_ENV_IS_IN_FLASH
 161 #endif
 162
 163 #if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
 164 #define CONFIG_CMD_ENV
 165 #define CONFIG_ENV_SIZE         (16 << 10)      /* 16 KiB */
 166 #define CONFIG_ENV_OFFSET       (51 << 9)       /* Sector 51 */
 167 #define CONFIG_ENV_IS_IN_MMC
 168 #undef CONFIG_ENV_IS_IN_FLASH
 169 #endif
 170
 171 #define CONFIG_BOOTDELAY        3
 172
 173 #define CONFIG_CMDLINE_EDITING
 174 #define CONFIG_VERSION_VARIABLE
 175 #define CONFIG_TIMESTAMP
 176
 177 /* U-Boot memory configuration */
 178 #define CONFIG_STACKSIZE                (256 << 10)     /* 256 KiB */
 179 #define CONFIG_SYS_MALLOC_LEN           (1 << 20)       /* 1 MiB */
 180 #define CONFIG_SYS_MEMTEST_START        0x80000000      /* physical address */
 181 #define CONFIG_SYS_MEMTEST_END          0x81000000      /* test 16MB RAM */
 182
 183 /* Linux interfacing */
 184 #define CONFIG_CMDLINE_TAG
 185 #define CONFIG_SETUP_MEMORY_TAGS
 186 #define CONFIG_SYS_BARGSIZE     1024                    /* bootarg Size */
 187 #define CONFIG_SYS_LOAD_ADDR    0x80700000              /* kernel address */
 188
 189 #define MTDIDS_DEFAULT          "nand0=davinci_nand.0"
 190
 191 #ifdef CONFIG_SYS_NAND_LARGEPAGE
 192 /*  Use same layout for 128K/256K blocks; allow some bad blocks */
 193 #define PART_BOOT               "2m(bootloader)ro,"
 194 #endif
 195
 196 #define PART_KERNEL             "4m(kernel),"   /* kernel + initramfs */
 197 #define PART_REST               "-(filesystem)"
 198
 199 #define MTDPARTS_DEFAULT        \
 200         "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
 201
 202 #define CONFIG_SYS_NAND_PAGE_SIZE       (0x800)
 203 #define CONFIG_SYS_NAND_BLOCK_SIZE      (0x20000)
 204
 205 /* Defines for SPL */
 206 #define CONFIG_SPL
 207 #define CONFIG_SPL_NAND_SUPPORT
 208 #define CONFIG_SPL_NAND_SIMPLE
 209 #define CONFIG_SPL_NAND_LOAD
 210 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 211 #define CONFIG_SPL_SERIAL_SUPPORT
 212 #define CONFIG_SPL_POST_MEM_SUPPORT
 213 #define CONFIG_SPL_LDSCRIPT             "$(BOARDDIR)/u-boot-spl.lds"
 214 #define CONFIG_SPL_STACK                (0x00010000 + 0x7f00)
 215
 216 #define CONFIG_SPL_TEXT_BASE            0x0000020 /*CONFIG_SYS_SRAM_START*/
 217 #define CONFIG_SPL_MAX_SIZE             12320
 218
 219 #ifndef CONFIG_SPL_BUILD
 220 #define CONFIG_SYS_TEXT_BASE            0x81080000
 221 #endif
 222
 223 #define CONFIG_SYS_NAND_BASE            0x02000000
 224 #define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE / \
 225                                         CONFIG_SYS_NAND_PAGE_SIZE)
 226
 227 #define CONFIG_SYS_NAND_ECCPOS          {                               \
 228                                 24, 25, 26, 27, 28,                     \
 229                                 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
 230                                 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
 231                                 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
 232                                 59, 60, 61, 62, 63 }
 233 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 234 #define CONFIG_SYS_NAND_ECCSIZE         0x200
 235 #define CONFIG_SYS_NAND_ECCBYTES        10
 236 #define CONFIG_SYS_NAND_OOBSIZE         64
 237 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 238
 239 /*
 240  * RBL searches from Block n (n = 1..24)
 241  * so we can define, how many UBL Headers
 242  * we can write before the real spl code
 243  */
 244 #define CONFIG_SYS_NROF_UBL_HEADER      5
 245 #define CONFIG_SYS_NROF_PAGES_NAND_SPL  6
 246
 247 #define CONFIG_SYS_NAND_U_BOOT_DST      0x81080000 /* u-boot TEXT_BASE */
 248 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 249
 250 /*
 251  * Post tests for memory testing
 252  */
 253 #define CONFIG_POST     CONFIG_SYS_POST_MEMORY
 254 #define _POST_WORD_ADDR 0x0
 255
 256 #define CONFIG_DISPLAY_CPUINFO
 257 #define CONFIG_DISPLAY_BOARDINFO
 258
 259 #define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SPL_STACK
 260
 261 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0xc0000
 262 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x60000
 263
 264 /*
 265  * U-Boot is a 3rd stage loader and if booting with spl, cpu setup is
 266  * done in board_init_f from c code.
 267  */
 268 #define CONFIG_SKIP_LOWLEVEL_INIT
 269
 270 /* for UBL header */
 271 #define CONFIG_SYS_UBL_BLOCK            (CONFIG_SYS_NAND_PAGE_SIZE)
 272
 273 #define CONFIG_SYS_DM36x_PLL1_PLLM      0x55
 274 #define CONFIG_SYS_DM36x_PLL1_PREDIV    0x8005
 275 #define CONFIG_SYS_DM36x_PLL2_PLLM      0x09
 276 #define CONFIG_SYS_DM36x_PLL2_PREDIV    0x8000
 277 #define CONFIG_SYS_DM36x_PERI_CLK_CTRL  0x243F04FC
 278 #define CONFIG_SYS_DM36x_PLL1_PLLDIV1   0x801b
 279 #define CONFIG_SYS_DM36x_PLL1_PLLDIV2   0x8001
 280 /* POST DIV 680/2 = 340Mhz  -> MJCP and HDVICP bus interface clock */
 281 #define CONFIG_SYS_DM36x_PLL1_PLLDIV3   0x8001
 282 /*
 283  * POST DIV 680/4 = 170Mhz  -> EDMA/Peripheral CFG0(1/2 MJCP/HDVICP bus
 284  * interface clk)
 285  */
 286 #define CONFIG_SYS_DM36x_PLL1_PLLDIV4   0x8003
 287 /* POST DIV 680/2 = 340Mhz  -> VPSS */
 288 #define CONFIG_SYS_DM36x_PLL1_PLLDIV5   0x8001
 289 /* POST DIV 680/9 = 75.6 Mhz -> VENC */
 290 #define CONFIG_SYS_DM36x_PLL1_PLLDIV6   0x8008
 291 /*
 292  * POST DIV 680/1 = 680Mhz -> DDRx2(with internal divider of 2, clock boils
 293  * down to 340 Mhz)
 294  */
 295 #define CONFIG_SYS_DM36x_PLL1_PLLDIV7   0x8000
 296 /* POST DIV 680/7= 97Mhz-> MMC0/SD0 */
 297 #define CONFIG_SYS_DM36x_PLL1_PLLDIV8   0x8006
 298 /* POST DIV 680/28 = 24.3Mhz-> CLKOUT */
 299 #define CONFIG_SYS_DM36x_PLL1_PLLDIV9   0x801b
 300
 301 #define CONFIG_SYS_DM36x_PLL2_PLLDIV1   0x8011
 302 /* POST DIV 432/1=432 Mhz  -> ARM926/(HDVICP block) clk */
 303 #define CONFIG_SYS_DM36x_PLL2_PLLDIV2   0x8000
 304 #define CONFIG_SYS_DM36x_PLL2_PLLDIV3   0x8001
 305 /* POST DIV 432/21= 20.5714 Mhz->VOICE Codec clk */
 306 #define CONFIG_SYS_DM36x_PLL2_PLLDIV4   0x8014
 307 /* POST DIV 432/16=27 Mhz  -> VENC(For SD modes, requires) */
 308 #define CONFIG_SYS_DM36x_PLL2_PLLDIV5   0x800f
 309
 310 /*
 311  * READ LATENCY 7 (CL + 2)
 312  * CONFIG_PWRDNEN = 1
 313  * CONFIG_EXT_STRBEN = 1
 314  */
 315 #define CONFIG_SYS_DM36x_DDR2_DDRPHYCR  (0 \
 316         | DV_DDR_PHY_EXT_STRBEN \
 317         | DV_DDR_PHY_PWRDNEN \
 318         | (7 << DV_DDR_PHY_RD_LATENCY_SHIFT))
 319
 320 /*
 321  * T_RFC = (trfc/DDR_CLK) - 1 = (195 / 2.941) - 1
 322  * T_RP  = (trp/DDR_CLK) - 1  = (12.5 / 2.941) - 1
 323  * T_RCD = (trcd/DDR_CLK) - 1 = (12.5 / 2.941) - 1
 324  * T_WR  = (twr/DDR_CLK) - 1  = (15 / 2.941) - 1
 325  * T_RAS = (tras/DDR_CLK) - 1 = (45 / 2.941) - 1
 326  * T_RC  = (trc/DDR_CLK) - 1  = (57.5 / 2.941) - 1
 327  * T_RRD = (trrd/DDR_CLK) - 1 = (7.5 / 2.941) - 1
 328  * T_WTR = (twtr/DDR_CLK) - 1 = (7.5 / 2.941) - 1
 329  */
 330 #define CONFIG_SYS_DM36x_DDR2_SDTIMR    (0 \
 331         | (66 << DV_DDR_SDTMR1_RFC_SHIFT) \
 332         | (4  << DV_DDR_SDTMR1_RP_SHIFT) \
 333         | (4  << DV_DDR_SDTMR1_RCD_SHIFT) \
 334         | (5  << DV_DDR_SDTMR1_WR_SHIFT) \
 335         | (14 << DV_DDR_SDTMR1_RAS_SHIFT) \
 336         | (19 << DV_DDR_SDTMR1_RC_SHIFT) \
 337         | (2  << DV_DDR_SDTMR1_RRD_SHIFT) \
 338         | (2  << DV_DDR_SDTMR1_WTR_SHIFT))
 339
 340 /*
 341  * T_RASMAX = (trasmax/refresh_rate) - 1 = (70K / 7812.6) - 1
 342  * T_XP  = tCKE - 1 = 3 - 2
 343  * T_XSNR= ((trfc + 10)/DDR_CLK) - 1 = (205 / 2.941) - 1
 344  * T_XSRD = txsrd - 1 = 200 - 1
 345  * T_RTP = (trtp/DDR_CLK) - 1 = (7.5 / 2.941) - 1
 346  * T_CKE = tcke - 1     = 3 - 1
 347  */
 348 #define CONFIG_SYS_DM36x_DDR2_SDTIMR2   (0 \
 349         | (8  << DV_DDR_SDTMR2_RASMAX_SHIFT) \
 350         | (2  << DV_DDR_SDTMR2_XP_SHIFT) \
 351         | (69 << DV_DDR_SDTMR2_XSNR_SHIFT) \
 352         | (199 <<  DV_DDR_SDTMR2_XSRD_SHIFT) \
 353         | (2 <<  DV_DDR_SDTMR2_RTP_SHIFT) \
 354         | (2 <<  DV_DDR_SDTMR2_CKE_SHIFT))
 355
 356 /* PR_OLD_COUNT = 0xfe */
 357 #define CONFIG_SYS_DM36x_DDR2_PBBPR     0x000000FE
 358 /* refresh rate = 0x768 */
 359 #define CONFIG_SYS_DM36x_DDR2_SDRCR     0x00000768
 360
 361 #define CONFIG_SYS_DM36x_DDR2_SDBCR     (0 \
 362         | (2 << DV_DDR_SDCR_PAGESIZE_SHIFT) \
 363         | (3 << DV_DDR_SDCR_IBANK_SHIFT) \
 364         | (5 << DV_DDR_SDCR_CL_SHIFT) \
 365         | (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)    \
 366         | (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) \
 367         | (1 << DV_DDR_SDCR_DDREN_SHIFT) \
 368         | (0 << DV_DDR_SDCR_DDRDRIVE0_SHIFT)    \
 369         | (1 << DV_DDR_SDCR_DDR2EN_SHIFT) \
 370         | (1 << DV_DDR_SDCR_DDR_DDQS_SHIFT) \
 371         | (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT))
 372
 373 #define CONFIG_SYS_DM36x_AWCCR  0xff
 374 #define CONFIG_SYS_DM36x_AB1CR  0x40400204
 375 #define CONFIG_SYS_DM36x_AB2CR  0x04ca2650
 376
 377 /* All Video Inputs */
 378 #define CONFIG_SYS_DM36x_PINMUX0        0x00000000
 379 /*
 380  * All Video Outputs,
 381  * GPIO 86, 87 + 90 0x0000f030
 382  */
 383 #define CONFIG_SYS_DM36x_PINMUX1        0x00530002
 384 #define CONFIG_SYS_DM36x_PINMUX2        0x00001815
 385 /*
 386  * SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
 387  * GPIO 25 0x60000000
 388  */
 389 #define CONFIG_SYS_DM36x_PINMUX3        0x9b5affff
 390 /*
 391  * MMC/SD0 instead of MS, SPI0
 392  * GPIO 34 0x0000c000
 393  */
 394 #define CONFIG_SYS_DM36x_PINMUX4        0x00002655
 395
 396 /*
 397  * Default environment settings
 398  */
 399 #define xstr(s) str(s)
 400 #define str(s)  #s
 401
 402 #define DVN4XX_UBOOT_ADDR_R_RAM         0x80000000
 403 /* (DVN4XX_UBOOT_ADDR_R_RAM + CONFIG_SYS_NAND_PAGE_SIZE) */
 404 #define DVN4XX_UBOOT_ADDR_R_NAND_SPL    0x80000800
 405 /*
 406  * (DVN4XX_UBOOT_ADDR_R_NAND_SPL + (CONFIG_SYS_NROF_PAGES_NAND_SPL * \
 407  * CONFIG_SYS_NAND_PAGE_SIZE))
 408  */
 409 #define DVN4XX_UBOOT_ADDR_R_UBOOT       0x80003800
 410
 411 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 412         "u_boot_addr_r=" xstr(DVN4XX_UBOOT_ADDR_R_RAM) "\0"             \
 413         "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.ubl\0"                 \
 414         "load=tftp ${u_boot_addr_r} ${uboot}\0"                         \
 415         "pagesz=" xstr(CONFIG_SYS_NAND_PAGE_SIZE) "\0"                  \
 416         "writeheader=nandrbl rbl;nand erase 80000 ${pagesz};"           \
 417                 "nand write ${u_boot_addr_r} 80000 ${pagesz};"          \
 418                 "nandrbl uboot\0"                                       \
 419         "writenand_spl=nandrbl rbl;nand erase a0000 3000;"              \
 420                 "nand write " xstr(DVN4XX_UBOOT_ADDR_R_NAND_SPL)        \
 421                 " a0000 3000;nandrbl uboot\0"                           \
 422         "writeuboot=nandrbl uboot;"                                     \
 423                 "nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " "     \
 424                  xstr(CONFIG_SYS_NAND_U_BOOT_SIZE)                      \
 425                 ";nand write " xstr(DVN4XX_UBOOT_ADDR_R_UBOOT)          \
 426                 " " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " "               \
 427                 xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0"                  \
 428         "update=run load writenand_spl writeuboot\0"                    \
 429         "bootcmd=run bootcmd\0"                                         \
 430         "rootpath=/opt/eldk-arm/arm\0"                                  \
 431         "\0"
 432
 433 /* USB Configuration */
 434 #define CONFIG_USB_DAVINCI
 435 #define CONFIG_MUSB_HCD
 436 #define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN | \
 437                                 USBPHY_PHY24MHZ)
 438
 439 #define CONFIG_CMD_USB         /* include support for usb cmd */
 440 #define CONFIG_USB_STORAGE     /* MSC class support */
 441 #define CONFIG_CMD_STORAGE     /* inclue support for usb-storage cmd */
 442 #define CONFIG_CMD_FAT         /* inclue support for FAT/storage */
 443 #define CONFIG_DOS_PARTITION   /* inclue support for FAT/storage */
 444
 445 #undef DAVINCI_DM365EVM
 446 #define PINMUX4_USBDRVBUS_BITCLEAR       0x3000
 447 #define PINMUX4_USBDRVBUS_BITSET         0x2000
 448
 449 #endif /* __CONFIG_H */