include/configs/canyonlands.h

   1 /*
   2  * (C) Copyright 2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 /************************************************************************
  22  * canyonlands.h - configuration for Canyonlands (460EX)
  23  ***********************************************************************/
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*-----------------------------------------------------------------------
  28  * High Level Configuration Options
  29  *----------------------------------------------------------------------*/
  30 /*
  31  * This config file is used for Canyonlands (460EX) Glacier (460GT)
  32  * and Arches dual (460GT)
  33  */
  34 #ifdef CONFIG_CANYONLANDS
  35 #define CONFIG_460EX            1       /* Specific PPC460EX            */
  36 #define CONFIG_HOSTNAME         canyonlands
  37 #else
  38 #define CONFIG_460GT            1       /* Specific PPC460GT            */
  39 #ifdef CONFIG_GLACIER
  40 #define CONFIG_HOSTNAME         glacier
  41 #else
  42 #define CONFIG_HOSTNAME         arches
  43 #define CONFIG_USE_NETDEV       eth1
  44 #define CONFIG_BD_NUM_CPUS      2
  45 #endif
  46 #endif
  47
  48 #define CONFIG_440              1
  49 #define CONFIG_4xx              1       /* ... PPC4xx family */
  50
  51 /*
  52  * Include common defines/options for all AMCC eval boards
  53  */
  54 #include "amcc-common.h"
  55
  56 #define CONFIG_SYS_CLK_FREQ     66666667        /* external freq to pll */
  57
  58 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_early_init_f */
  59 #define CONFIG_BOARD_EARLY_INIT_R       1       /* Call board_early_init_r */
  60 #define CONFIG_MISC_INIT_R              1       /* Call misc_init_r */
  61 #define CONFIG_BOARD_TYPES              1       /* support board types */
  62
  63 /*-----------------------------------------------------------------------
  64  * Base addresses -- Note these are effective addresses where the
  65  * actual resources get mapped (not physical addresses)
  66  *----------------------------------------------------------------------*/
  67 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped PCI memory    */
  68 #define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs    */
  69 #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
  70
  71 #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000      /* mapped PCIe memory   */
  72 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* smallest incr for PCIe port */
  73 #define CONFIG_SYS_PCIE_BASE            0xc4000000      /* PCIe UTL regs */
  74
  75 #define CONFIG_SYS_PCIE0_CFGBASE        0xc0000000
  76 #define CONFIG_SYS_PCIE1_CFGBASE        0xc1000000
  77 #define CONFIG_SYS_PCIE0_XCFGBASE       0xc3000000
  78 #define CONFIG_SYS_PCIE1_XCFGBASE       0xc3001000
  79
  80 #define CONFIG_SYS_PCIE0_UTLBASE        0xc08010000ULL  /* 36bit physical addr  */
  81
  82 /* base address of inbound PCIe window */
  83 #define CONFIG_SYS_PCIE_INBOUND_BASE    0x000000000ULL  /* 36bit physical addr  */
  84
  85 /* EBC stuff */
  86 #if !defined(CONFIG_ARCHES)
  87 #define CONFIG_SYS_BCSR_BASE            0xE1000000
  88 #define CONFIG_SYS_FLASH_BASE           0xFC000000      /* later mapped to this addr */
  89 #define CONFIG_SYS_FLASH_SIZE           (64 << 20)
  90 #else
  91 #define CONFIG_SYS_FPGA_BASE            0xE1000000
  92 #define CONFIG_SYS_CPLD_ADDR            (CONFIG_SYS_FPGA_BASE + 0x00080000)
  93 #define CONFIG_SYS_CPLD_DATA            (CONFIG_SYS_FPGA_BASE + 0x00080002)
  94 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* later mapped to this addr  */
  95 #define CONFIG_SYS_FLASH_SIZE           (32 << 20)
  96 #endif
  97
  98 #define CONFIG_SYS_NAND_ADDR            0xE0000000
  99 #define CONFIG_SYS_BOOT_BASE_ADDR       0xFF000000      /* EBC Boot Space: 0xFF000000 */
 100 #define CONFIG_SYS_FLASH_BASE_PHYS_H    0x4
 101 #define CONFIG_SYS_FLASH_BASE_PHYS_L    0xCC000000
 102 #define CONFIG_SYS_FLASH_BASE_PHYS      (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) |    \
 103                                          (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
 104
 105 #define CONFIG_SYS_OCM_BASE             0xE3000000      /* OCM: 16k             */
 106 #define CONFIG_SYS_SRAM_BASE            0xE8000000      /* SRAM: 256k           */
 107 #define CONFIG_SYS_LOCAL_CONF_REGS      0xEF000000
 108
 109 #define CONFIG_SYS_PERIPHERAL_BASE      0xEF600000      /* internal peripherals */
 110
 111 #define CONFIG_SYS_AHB_BASE             0xE2000000      /* internal AHB peripherals     */
 112
 113 /*-----------------------------------------------------------------------
 114  * Initial RAM & stack pointer (placed in OCM)
 115  *----------------------------------------------------------------------*/
 116 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM                  */
 117 #define CONFIG_SYS_INIT_RAM_END (4 << 10)
 118 #define CONFIG_SYS_GBL_DATA_SIZE        256             /* num bytes initial data */
 119 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 120 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 121
 122 /*-----------------------------------------------------------------------
 123  * Serial Port
 124  *----------------------------------------------------------------------*/
 125 #undef CONFIG_UART1_CONSOLE     /* define this if you want console on UART1 */
 126
 127 /*-----------------------------------------------------------------------
 128  * Environment
 129  *----------------------------------------------------------------------*/
 130 /*
 131  * Define here the location of the environment variables (FLASH).
 132  */
 133 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 134 #define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars */
 135 #define CONFIG_SYS_NAND_CS              3       /* NAND chip connected to CSx */
 136 #else
 137 #define CONFIG_ENV_IS_IN_NAND   1       /* use NAND for environment vars  */
 138 #define CONFIG_SYS_NAND_CS              0       /* NAND chip connected to CSx */
 139 #define CONFIG_ENV_IS_EMBEDDED  1       /* use embedded environment */
 140 #endif
 141
 142 /*
 143  * IPL (Initial Program Loader, integrated inside CPU)
 144  * Will load first 4k from NAND (SPL) into cache and execute it from there.
 145  *
 146  * SPL (Secondary Program Loader)
 147  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 148  * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 149  * controller and the NAND controller so that the special U-Boot image can be
 150  * loaded from NAND to SDRAM.
 151  *
 152  * NUB (NAND U-Boot)
 153  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 154  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 155  *
 156  * On 440EPx the SPL is copied to SDRAM before the NAND controller is
 157  * set up. While still running from cache, I experienced problems accessing
 158  * the NAND controller. sr - 2006-08-25
 159  *
 160  * This is the first official implementation of booting from 2k page sized
 161  * NAND devices (e.g. Micron 29F2G08AA 256Mbit * 8)
 162  */
 163 #define CONFIG_SYS_NAND_BOOT_SPL_SRC    0xfffff000      /* SPL location               */
 164 #define CONFIG_SYS_NAND_BOOT_SPL_SIZE   (4 << 10)       /* SPL size                   */
 165 #define CONFIG_SYS_NAND_BOOT_SPL_DST    (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here  */
 166 #define CONFIG_SYS_NAND_U_BOOT_DST      0x01000000      /* Load NUB to this addr      */
 167 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST      /* Start NUB from     */
 168                                                         /*   this addr        */
 169 #define CONFIG_SYS_NAND_BOOT_SPL_DELTA  (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
 170
 171 /*
 172  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 173  */
 174 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)     /* Offset to RAM U-Boot image */
 175 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (1 << 20)       /* Size of RAM U-Boot image   */
 176
 177 /*
 178  * Now the NAND chip has to be defined (no autodetection used!)
 179  */
 180 #define CONFIG_SYS_NAND_PAGE_SIZE       (2 << 10)       /* NAND chip page size        */
 181 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)     /* NAND chip block size       */
 182 #define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE)
 183                                                 /* NAND chip page count       */
 184 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0               /* Location of bad block marker*/
 185 #define CONFIG_SYS_NAND_5_ADDR_CYCLE                    /* Fifth addr used (<=128MB)  */
 186
 187 #define CONFIG_SYS_NAND_ECCSIZE 256
 188 #define CONFIG_SYS_NAND_ECCBYTES        3
 189 #define CONFIG_SYS_NAND_ECCSTEPS        (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
 190 #define CONFIG_SYS_NAND_OOBSIZE 64
 191 #define CONFIG_SYS_NAND_ECCTOTAL        (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
 192 #define CONFIG_SYS_NAND_ECCPOS          {40, 41, 42, 43, 44, 45, 46, 47, \
 193                                  48, 49, 50, 51, 52, 53, 54, 55, \
 194                                  56, 57, 58, 59, 60, 61, 62, 63}
 195
 196 #ifdef CONFIG_ENV_IS_IN_NAND
 197 /*
 198  * For NAND booting the environment is embedded in the U-Boot image. Please take
 199  * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
 200  */
 201 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 202 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 203 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 204 #endif
 205
 206 /*-----------------------------------------------------------------------
 207  * FLASH related
 208  *----------------------------------------------------------------------*/
 209 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 210 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 211 #define CONFIG_SYS_FLASH_CFI_AMD_RESET  1       /* Use AMD (Spansion) reset cmd */
 212
 213 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 214 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 215 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 216
 217 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 218 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 219
 220 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 221 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 222
 223 #ifdef CONFIG_ENV_IS_IN_FLASH
 224 #define CONFIG_ENV_SECT_SIZE    0x20000         /* size of one complete sector  */
 225 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 226 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 227
 228 /* Address and size of Redundant Environment Sector     */
 229 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 230 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 231 #endif /* CONFIG_ENV_IS_IN_FLASH */
 232
 233 /*-----------------------------------------------------------------------
 234  * NAND-FLASH related
 235  *----------------------------------------------------------------------*/
 236 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 237 #define NAND_MAX_CHIPS          1
 238 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 239 #define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips   */
 240
 241 /*------------------------------------------------------------------------------
 242  * DDR SDRAM
 243  *----------------------------------------------------------------------------*/
 244 #if !defined(CONFIG_NAND_U_BOOT)
 245 #if !defined(CONFIG_ARCHES)
 246 /*
 247  * NAND booting U-Boot version uses a fixed initialization, since the whole
 248  * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
 249  * code.
 250  */
 251 #define CONFIG_SPD_EEPROM       1       /* Use SPD EEPROM for setup     */
 252 #define SPD_EEPROM_ADDRESS      {0x50, 0x51}    /* SPD i2c spd addresses*/
 253 #define CONFIG_DDR_ECC          1       /* with ECC support             */
 254 #define CONFIG_DDR_RQDC_FIXED   0x80000038 /* fixed value for RQDC      */
 255
 256 #else /* defined(CONFIG_ARCHES) */
 257
 258 #define CONFIG_AUTOCALIB        "silent\0"      /* default is non-verbose    */
 259
 260 #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration   */
 261 #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION        /* dynamic DDR autocal debug */
 262 #undef CONFIG_PPC4xx_DDR_METHOD_A
 263
 264 /* DDR1/2 SDRAM Device Control Register Data Values */
 265 /* Memory Queue */
 266 #define CONFIG_SYS_SDRAM_R0BAS          0x0000f000
 267 #define CONFIG_SYS_SDRAM_R1BAS          0x00000000
 268 #define CONFIG_SYS_SDRAM_R2BAS          0x00000000
 269 #define CONFIG_SYS_SDRAM_R3BAS          0x00000000
 270 #define CONFIG_SYS_SDRAM_PLBADDULL      0x00000000
 271 #define CONFIG_SYS_SDRAM_PLBADDUHB      0x00000008
 272 #define CONFIG_SYS_SDRAM_CONF1LL        0x00001080
 273 #define CONFIG_SYS_SDRAM_CONF1HB        0x00001080
 274 #define CONFIG_SYS_SDRAM_CONFPATHB      0x10a68000
 275
 276 /* SDRAM Controller */
 277 #define CONFIG_SYS_SDRAM0_MB0CF         0x00000701
 278 #define CONFIG_SYS_SDRAM0_MB1CF         0x00000000
 279 #define CONFIG_SYS_SDRAM0_MB2CF         0x00000000
 280 #define CONFIG_SYS_SDRAM0_MB3CF         0x00000000
 281 #define CONFIG_SYS_SDRAM0_MCOPT1        0x05322000
 282 #define CONFIG_SYS_SDRAM0_MCOPT2        0x00000000
 283 #define CONFIG_SYS_SDRAM0_MODT0         0x01000000
 284 #define CONFIG_SYS_SDRAM0_MODT1         0x00000000
 285 #define CONFIG_SYS_SDRAM0_MODT2         0x00000000
 286 #define CONFIG_SYS_SDRAM0_MODT3         0x00000000
 287 #define CONFIG_SYS_SDRAM0_CODT          0x00800021
 288 #define CONFIG_SYS_SDRAM0_RTR           0x06180000
 289 #define CONFIG_SYS_SDRAM0_INITPLR0      0xb5380000
 290 #define CONFIG_SYS_SDRAM0_INITPLR1      0x82100400
 291 #define CONFIG_SYS_SDRAM0_INITPLR2      0x80820000
 292 #define CONFIG_SYS_SDRAM0_INITPLR3      0x80830000
 293 #define CONFIG_SYS_SDRAM0_INITPLR4      0x80810040
 294 #define CONFIG_SYS_SDRAM0_INITPLR5      0x80800532
 295 #define CONFIG_SYS_SDRAM0_INITPLR6      0x82100400
 296 #define CONFIG_SYS_SDRAM0_INITPLR7      0x8a080000
 297 #define CONFIG_SYS_SDRAM0_INITPLR8      0x8a080000
 298 #define CONFIG_SYS_SDRAM0_INITPLR9      0x8a080000
 299 #define CONFIG_SYS_SDRAM0_INITPLR10     0x8a080000
 300 #define CONFIG_SYS_SDRAM0_INITPLR11     0x80000432
 301 #define CONFIG_SYS_SDRAM0_INITPLR12     0x808103c0
 302 #define CONFIG_SYS_SDRAM0_INITPLR13     0x80810040
 303 #define CONFIG_SYS_SDRAM0_INITPLR14     0x00000000
 304 #define CONFIG_SYS_SDRAM0_INITPLR15     0x00000000
 305 #define CONFIG_SYS_SDRAM0_RQDC          0x80000038
 306 #define CONFIG_SYS_SDRAM0_RFDC          0x00000257
 307 #define CONFIG_SYS_SDRAM0_RDCC          0x40000000
 308 #define CONFIG_SYS_SDRAM0_DLCR          0x03000091
 309 #define CONFIG_SYS_SDRAM0_CLKTR         0x40000000
 310 #define CONFIG_SYS_SDRAM0_WRDTR         0x82000823
 311 #define CONFIG_SYS_SDRAM0_SDTR1         0x80201000
 312 #define CONFIG_SYS_SDRAM0_SDTR2         0x42204243
 313 #define CONFIG_SYS_SDRAM0_SDTR3         0x090c0d1a
 314 #define CONFIG_SYS_SDRAM0_MMODE         0x00000432
 315 #define CONFIG_SYS_SDRAM0_MEMODE        0x00000004
 316 #endif  /* !defined(CONFIG_ARCHES) */
 317 #endif  /* !defined(CONFIG_NAND_U_BOOT) */
 318
 319 #define CONFIG_SYS_MBYTES_SDRAM 512     /* 512MB                        */
 320
 321 /*-----------------------------------------------------------------------
 322  * I2C
 323  *----------------------------------------------------------------------*/
 324 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed                    */
 325
 326 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 327 #define CONFIG_SYS_I2C_EEPROM_ADDR              (0xa8>>1)
 328 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 329 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 330 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 331
 332 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 333 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 334 #define CONFIG_DTT_AD7414       1               /* use AD7414           */
 335 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 336 #define CONFIG_SYS_DTT_MAX_TEMP 70
 337 #define CONFIG_SYS_DTT_LOW_TEMP -30
 338 #define CONFIG_SYS_DTT_HYSTERESIS       3
 339
 340 #if defined(CONFIG_ARCHES)
 341 #define CONFIG_SYS_I2C_DTT_ADDR 0x4a            /* AD7414 I2C address   */
 342 #endif
 343
 344 #if !defined(CONFIG_ARCHES)
 345 /* RTC configuration */
 346 #define CONFIG_RTC_M41T62       1
 347 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 348 #endif
 349
 350 /*-----------------------------------------------------------------------
 351  * Ethernet
 352  *----------------------------------------------------------------------*/
 353 #define CONFIG_IBM_EMAC4_V4     1
 354
 355 #define CONFIG_HAS_ETH0
 356 #define CONFIG_HAS_ETH1
 357
 358 #if !defined(CONFIG_ARCHES)
 359 #define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 360 #define CONFIG_PHY1_ADDR        1
 361 /* Only Glacier (460GT) has 4 EMAC interfaces */
 362 #ifdef CONFIG_460GT
 363 #define CONFIG_PHY2_ADDR        2
 364 #define CONFIG_PHY3_ADDR        3
 365 #define CONFIG_HAS_ETH2
 366 #define CONFIG_HAS_ETH3
 367 #endif
 368
 369 #else /* defined(CONFIG_ARCHES) */
 370
 371 #define CONFIG_FIXED_PHY        0xFFFFFFFF
 372 #define CONFIG_PHY_ADDR         CONFIG_FIXED_PHY
 373 #define CONFIG_PHY1_ADDR        0
 374 #define CONFIG_PHY2_ADDR        1
 375 #define CONFIG_HAS_ETH2
 376
 377 #define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
 378                 {devnum, speed, duplex}
 379 #define CONFIG_SYS_FIXED_PHY_PORTS \
 380                 CONFIG_SYS_FIXED_PHY_PORT(0, 1000, FULL)
 381
 382 #define CONFIG_M88E1112_PHY
 383
 384 /*
 385  * For the GPCS_PHYx_ADDR PHY address, choose some PHY address not
 386  * used by CONFIG_PHYx_ADDR
 387  */
 388 #define CONFIG_GPCS_PHY_ADDR    0xA
 389 #define CONFIG_GPCS_PHY1_ADDR   0xB
 390 #define CONFIG_GPCS_PHY2_ADDR   0xC
 391 #endif  /* !defined(CONFIG_ARCHES) */
 392
 393 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 394 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 395 #define CONFIG_PHY_DYNAMIC_ANEG 1
 396
 397 /*-----------------------------------------------------------------------
 398  * USB-OHCI
 399  *----------------------------------------------------------------------*/
 400 /* Only Canyonlands (460EX) has USB */
 401 #ifdef CONFIG_460EX
 402 #define CONFIG_USB_OHCI_NEW
 403 #define CONFIG_USB_STORAGE
 404 #undef CONFIG_SYS_OHCI_BE_CONTROLLER            /* 460EX has little endian descriptors  */
 405 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register     */
 406 #define CONFIG_SYS_OHCI_USE_NPS         /* force NoPowerSwitching mode          */
 407 #define CONFIG_SYS_USB_OHCI_REGS_BASE   (CONFIG_SYS_AHB_BASE | 0xd0000)
 408 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ppc440"
 409 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 410 #endif
 411
 412 /*
 413  * Default environment variables
 414  */
 415 #if !defined(CONFIG_ARCHES)
 416 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 417         CONFIG_AMCC_DEF_ENV                                             \
 418         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 419         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 420         CONFIG_AMCC_DEF_ENV_NAND_UPD                                    \
 421         "kernel_addr=fc000000\0"                                        \
 422         "fdt_addr=fc1e0000\0"                                           \
 423         "ramdisk_addr=fc200000\0"                                       \
 424         "pciconfighost=1\0"                                             \
 425         "pcie_mode=RP:RP\0"                                             \
 426         ""
 427 #else /* defined(CONFIG_ARCHES) */
 428 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 429         CONFIG_AMCC_DEF_ENV                                             \
 430         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 431         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 432         "kernel_addr=fe000000\0"                                        \
 433         "fdt_addr=fe1e0000\0"                                           \
 434         "ramdisk_addr=fe200000\0"                                       \
 435         "pciconfighost=1\0"                                             \
 436         "pcie_mode=RP:RP\0"                                             \
 437         "ethprime=ppc_4xx_eth1\0"                                       \
 438         ""
 439 #endif  /* !defined(CONFIG_ARCHES) */
 440
 441 /*
 442  * Commands additional to the ones defined in amcc-common.h
 443  */
 444 #if defined(CONFIG_ARCHES)
 445 #define CONFIG_CMD_DTT
 446 #define CONFIG_CMD_PCI
 447 #define CONFIG_CMD_SDRAM
 448 #elif defined(CONFIG_CANYONLANDS)
 449 #define CONFIG_CMD_DATE
 450 #define CONFIG_CMD_DTT
 451 #define CONFIG_CMD_EXT2
 452 #define CONFIG_CMD_FAT
 453 #define CONFIG_CMD_NAND
 454 #define CONFIG_CMD_PCI
 455 #define CONFIG_CMD_SDRAM
 456 #define CONFIG_CMD_SNTP
 457 #define CONFIG_CMD_USB
 458 #elif defined(CONFIG_GLACIER)
 459 #define CONFIG_CMD_DATE
 460 #define CONFIG_CMD_DTT
 461 #define CONFIG_CMD_NAND
 462 #define CONFIG_CMD_PCI
 463 #define CONFIG_CMD_SDRAM
 464 #define CONFIG_CMD_SNTP
 465 #else
 466 #error "board type not defined"
 467 #endif
 468
 469 /* Partitions */
 470 #define CONFIG_MAC_PARTITION
 471 #define CONFIG_DOS_PARTITION
 472 #define CONFIG_ISO_PARTITION
 473
 474 /*-----------------------------------------------------------------------
 475  * PCI stuff
 476  *----------------------------------------------------------------------*/
 477 /* General PCI */
 478 #define CONFIG_PCI                      /* include pci support          */
 479 #define CONFIG_PCI_PNP                  /* do pci plug-and-play   */
 480 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 481 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 482
 483 /* Board-specific PCI */
 484 #define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
 485 #undef  CONFIG_SYS_PCI_MASTER_INIT
 486
 487 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM                          */
 488 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever                     */
 489
 490 #ifdef CONFIG_460GT
 491 #if defined(CONFIG_ARCHES)
 492 /*-----------------------------------------------------------------------
 493  * RapidIO I/O and Registers
 494  *----------------------------------------------------------------------*/
 495 #define CONFIG_RAPIDIO
 496 #define CONFIG_SYS_460GT_SRIO_ERRATA_1
 497
 498 #define SRGPL0_REG_BAR          0x0000000DAA000000ull   /*  16MB */
 499 #define SRGPL0_CFG_BAR          0x0000000DAB000000ull   /*  16MB */
 500 #define SRGPL0_MNT_BAR          0x0000000DAC000000ull   /*  16MB */
 501 #define SRGPL0_MSG_BAR          0x0000000DAD000000ull   /*  16MB */
 502 #define SRGPL0_OUT_BAR          0x0000000DB0000000ull   /* 256MB */
 503
 504 #define CONFIG_SYS_SRGPL0_REG_BAR       0xAA000000              /*  16MB */
 505 #define CONFIG_SYS_SRGPL0_CFG_BAR       0xAB000000              /*  16MB */
 506 #define CONFIG_SYS_SRGPL0_MNT_BAR       0xAC000000              /*  16MB */
 507 #define CONFIG_SYS_SRGPL0_MSG_BAR       0xAD000000              /*  16MB */
 508
 509 #define CONFIG_SYS_I2ODMA_BASE          0xCF000000
 510 #define CONFIG_SYS_I2ODMA_PHYS_ADDR     0x0000000400100000ull
 511
 512 #define CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE
 513 #undef CONFIG_PPC4XX_RAPIDIO_DEBUG
 514 #undef CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM
 515 #define CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB
 516 #undef CONFIG_PPC4XX_RAPIDIO_LOOPBACK
 517 #endif /* CONFIG_ARCHES */
 518 #endif /* CONFIG_460GT */
 519
 520 /*-----------------------------------------------------------------------
 521  * External Bus Controller (EBC) Setup
 522  *----------------------------------------------------------------------*/
 523
 524 /*
 525  * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
 526  * boot EBC mapping only supports a maximum of 16MBytes
 527  * (4.ff00.0000 - 4.ffff.ffff).
 528  * To solve this problem, the FLASH has to get remapped to another
 529  * EBC address which accepts bigger regions:
 530  *
 531  * 0xfc00.0000 -> 4.cc00.0000
 532  *
 533  * Arches has 32MBytes of NOR FLASH (Spansion 29GL256), it will be
 534  * remapped to:
 535  *
 536  * 0xfe00.0000 -> 4.ce00.0000
 537  */
 538
 539 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 540 /* Memory Bank 3 (NOR-FLASH) initialization                                     */
 541 #define CONFIG_SYS_EBC_PB3AP            0x10055e00
 542 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
 543
 544 /* Memory Bank 0 (NAND-FLASH) initialization                                            */
 545 #define CONFIG_SYS_EBC_PB0AP            0x018003c0
 546 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
 547 #else
 548 /* Memory Bank 0 (NOR-FLASH) initialization                                     */
 549 #define CONFIG_SYS_EBC_PB0AP            0x10055e00
 550 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
 551
 552 #if !defined(CONFIG_ARCHES)
 553 /* Memory Bank 3 (NAND-FLASH) initialization                                            */
 554 #define CONFIG_SYS_EBC_PB3AP            0x018003c0
 555 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
 556 #endif
 557 #endif  /*defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
 558
 559 #if !defined(CONFIG_ARCHES)
 560 /* Memory Bank 2 (CPLD) initialization                                          */
 561 #define CONFIG_SYS_EBC_PB2AP            0x00804240
 562 #define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
 563
 564 #else /* defined(CONFIG_ARCHES) */
 565
 566 /* Memory Bank 1 (FPGA) initialization  */
 567 #define CONFIG_SYS_EBC_PB1AP            0x7f8ffe80
 568 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
 569 #endif  /* !defined(CONFIG_ARCHES) */
 570
 571 #define CONFIG_SYS_EBC_CFG              0xB8400000              /*  EBC0_CFG */
 572
 573 /*
 574  * Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO
 575  * pin multiplexing correctly
 576  */
 577 #if defined(CONFIG_ARCHES)
 578 #define GPIO43_USE              GPIO_SEL        /* On Arches this pin is used as GPIO */
 579 #else
 580 #define GPIO43_USE              GPIO_ALT1       /* On Glacier this pin is used as ALT1 -> PerCS3 */
 581 #endif
 582
 583 /*
 584  * PPC4xx GPIO Configuration
 585  */
 586 #ifdef CONFIG_460EX
 587 /* 460EX: Use USB configuration */
 588 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 589 {                                                                                       \
 590 /* GPIO Core 0 */                                                                       \
 591 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0)      USB2HostD(0)    */      \
 592 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1)      USB2HostD(1)    */      \
 593 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2)      USB2HostD(2)    */      \
 594 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3)      USB2HostD(3)    */      \
 595 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4)      USB2HostD(4)    */      \
 596 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5)      USB2HostD(5)    */      \
 597 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6)      USB2HostD(6)    */      \
 598 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7)      USB2HostD(7)    */      \
 599 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0)      USB2OTGD(0)     */      \
 600 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1)      USB2OTGD(1)     */      \
 601 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)     USB2OTGD(2)     */      \
 602 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)     USB2OTGD(3)     */      \
 603 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)     USB2OTGD(4)     */      \
 604 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)     USB2OTGD(5)     */      \
 605 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)     USB2OTGD(6)     */      \
 606 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)     USB2OTGD(7)     */      \
 607 {GPIO0_BASE, GPIO_IN , GPIO_SEL,  GPIO_OUT_0}, /* GPIO16 GMC1TxER       USB2HostStop    */      \
 608 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD         USB2HostNext    */      \
 609 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER       USB2HostDir     */      \
 610 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO19 GMC1TxEN       USB2OTGStop     */      \
 611 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS        USB2OTGNext     */      \
 612 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV       USB2OTGDir      */      \
 613 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY                          */      \
 614 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN                          */      \
 615 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN                          */      \
 616 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE                          */      \
 617 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE                          */      \
 618 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)                         */      \
 619 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)                         */      \
 620 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)                         */      \
 621 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0        DMAReq2         IRQ(7)*/ \
 622 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1        DMAAck2         IRQ(8)*/ \
 623 },                                                                                      \
 624 {                                                                                       \
 625 /* GPIO Core 1 */                                                                       \
 626 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2        EOT2/TC2        IRQ(9)*/ \
 627 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3        DMAReq3         IRQ(4)*/ \
 628 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 629 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 630 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3       UART3_SIN*/ \
 631 {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EOT3/TC3        UART3_SOUT*/ \
 632 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 633 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 634 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)                         */      \
 635 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)                          */      \
 636 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)                          */      \
 637 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)          DMAReq1         IRQ(10)*/ \
 638 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)          DMAAck1         IRQ(11)*/ \
 639 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)          EOT/TC1         IRQ(12)*/ \
 640 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)     DMAReq0         IRQ(13)*/ \
 641 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)     DMAAck0         IRQ(14)*/ \
 642 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)     EOT/TC0         IRQ(15)*/ \
 643 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 644 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 645 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 646 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 647 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 648 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 649 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 650 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 651 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 652 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 653 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 654 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 655 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 656 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 657 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 658 }                                                                                       \
 659 }
 660 #else
 661 /* 460GT: Use EMAC2+3 configuration */
 662 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 663 {                                                                                       \
 664 /* GPIO Core 0 */                                                                       \
 665 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0)      USB2HostD(0)    */      \
 666 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1)      USB2HostD(1)    */      \
 667 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2)      USB2HostD(2)    */      \
 668 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3)      USB2HostD(3)    */      \
 669 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4)      USB2HostD(4)    */      \
 670 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5)      USB2HostD(5)    */      \
 671 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6)      USB2HostD(6)    */      \
 672 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7)      USB2HostD(7)    */      \
 673 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0)      USB2OTGD(0)     */      \
 674 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1)      USB2OTGD(1)     */      \
 675 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)     USB2OTGD(2)     */      \
 676 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)     USB2OTGD(3)     */      \
 677 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)     USB2OTGD(4)     */      \
 678 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)     USB2OTGD(5)     */      \
 679 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)     USB2OTGD(6)     */      \
 680 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)     USB2OTGD(7)     */      \
 681 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER       USB2HostStop    */      \
 682 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD         USB2HostNext    */      \
 683 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER       USB2HostDir     */      \
 684 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN       USB2OTGStop     */      \
 685 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS        USB2OTGNext     */      \
 686 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV       USB2OTGDir      */      \
 687 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY                          */      \
 688 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN                          */      \
 689 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN                          */      \
 690 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE                          */      \
 691 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE                          */      \
 692 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)                         */      \
 693 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)                         */      \
 694 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)                         */      \
 695 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0        DMAReq2         IRQ(7)*/ \
 696 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1        DMAAck2         IRQ(8)*/ \
 697 },                                                                                      \
 698 {                                                                                       \
 699 /* GPIO Core 1 */                                                                       \
 700 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2        EOT2/TC2        IRQ(9)*/ \
 701 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3        DMAReq3         IRQ(4)*/ \
 702 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 703 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 704 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3       UART3_SIN*/ \
 705 {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EOT3/TC3        UART3_SOUT*/ \
 706 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 707 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 708 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)                         */      \
 709 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)                          */      \
 710 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)                          */      \
 711 {GPIO1_BASE, GPIO_OUT, GPIO43_USE, GPIO_OUT_0},/* GPIO43 CS(3)          DMAReq1         IRQ(10)*/ \
 712 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)          DMAAck1         IRQ(11)*/ \
 713 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)          EOT/TC1         IRQ(12)*/ \
 714 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)     DMAReq0         IRQ(13)*/ \
 715 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)     DMAAck0         IRQ(14)*/ \
 716 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)     EOT/TC0         IRQ(15)*/ \
 717 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 718 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 719 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 720 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 721 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 722 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 723 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 724 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 725 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 726 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 727 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 728 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 729 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 730 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 731 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 732 }                                                                                       \
 733 }
 734 #endif
 735
 736 #endif  /* __CONFIG_H */