include/configs/cm5200.h

   1 /*
   2  * (C) Copyright 2003-2007
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #define CONFIG_DISPLAY_BOARDINFO
  12
  13 /*
  14  * High Level Configuration Options
  15  */
  16 #define CONFIG_MPC5200          1       /* This is an MPC5200 CPU */
  17 #define CONFIG_CM5200           1       /* ... on CM5200 platform */
  18
  19 #define CONFIG_SYS_TEXT_BASE    0xfc000000
  20
  21 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  22
  23 /*
  24  * Supported commands
  25  */
  26 #define CONFIG_CMD_BSP
  27 #define CONFIG_CMD_DATE
  28 #define CONFIG_CMD_DIAG
  29 #define CONFIG_CMD_JFFS2
  30 #define CONFIG_CMD_REGINFO
  31
  32 /*
  33  * Serial console configuration
  34  */
  35 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  36 #define CONFIG_BAUDRATE         57600   /* ... at 57600 bps */
  37 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  38 #define CONFIG_SILENT_CONSOLE   1       /* needed to silence i2c_init() */
  39
  40 /*
  41  * Ethernet configuration
  42  */
  43 #define CONFIG_MPC5xxx_FEC      1
  44 #define CONFIG_MPC5xxx_FEC_MII100
  45 #define CONFIG_PHY_ADDR         0x00
  46 #define CONFIG_ENV_OVERWRITE    1       /* allow overwriting of ethaddr */
  47 /* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
  48 #define CONFIG_MISC_INIT_R      1
  49 #define CONFIG_MAC_OFFSET       0x35    /* MAC address offset in I2C EEPROM */
  50
  51 /*
  52  * POST support
  53  */
  54 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU | CONFIG_SYS_POST_I2C)
  55 #define MPC5XXX_SRAM_POST_SIZE  (MPC5XXX_SRAM_SIZE - 4)
  56 /* List of I2C addresses to be verified by POST */
  57 #define CONFIG_SYS_POST_I2C_ADDRS       {CONFIG_SYS_I2C_SLAVE,  \
  58                                          CONFIG_SYS_I2C_IO,     \
  59                                          CONFIG_SYS_I2C_EEPROM}
  60
  61 /* display image timestamps */
  62 #define CONFIG_TIMESTAMP        1
  63
  64 /*
  65  * Autobooting
  66  */
  67 #define CONFIG_PREBOOT  "echo;" \
  68         "echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \
  69         "echo"
  70 #undef CONFIG_BOOTARGS
  71
  72 /*
  73  * Default environment settings
  74  */
  75 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  76         "netdev=eth0\0"                                                 \
  77         "netmask=255.255.0.0\0"                                         \
  78         "ipaddr=192.168.160.33\0"                                       \
  79         "serverip=192.168.1.1\0"                                        \
  80         "gatewayip=192.168.1.1\0"                                       \
  81         "console=ttyPSC0\0"                                             \
  82         "u-boot_addr=100000\0"                                          \
  83         "kernel_addr=200000\0"                                          \
  84         "kernel_addr_flash=fc0c0000\0"                                  \
  85         "fdt_addr=400000\0"                                             \
  86         "fdt_addr_flash=fc0a0000\0"                                     \
  87         "ramdisk_addr=500000\0"                                         \
  88         "rootpath=/opt/eldk-4.1/ppc_6xx\0"                              \
  89         "u-boot=/tftpboot/cm5200/u-boot.bin\0"                          \
  90         "bootfile_fdt=/tftpboot/cm5200/uImage\0"                        \
  91         "fdt_file=/tftpboot/cm5200/cm5200.dtb\0"                        \
  92         "load=tftp ${u-boot_addr} ${u-boot}\0"                          \
  93         "update=prot off fc000000 +${filesize}; "                       \
  94                 "era fc000000 +${filesize}; "                           \
  95                 "cp.b ${u-boot_addr} fc000000 ${filesize}; "            \
  96                 "prot on fc000000 +${filesize}\0"                       \
  97         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  98                 "nfsroot=${serverip}:${rootpath}\0"                     \
  99         "flashargs=setenv bootargs root=/dev/mtdblock5 rw\0"            \
 100         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 101         "addinit=setenv bootargs ${bootargs} init=/linuxrc\0"           \
 102         "addcons=setenv bootargs ${bootargs} "                          \
 103                 "console=${console},${baudrate}\0"                      \
 104         "addip=setenv bootargs ${bootargs} "                            \
 105                 "ip=${ipaddr}:${serverip}:${gatewayip}:"                \
 106                 "${netmask}:${hostname}:${netdev}:off panic=1\0"        \
 107         "flash_flash=run flashargs addinit addip addcons;"              \
 108                 "bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0"      \
 109         "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; "             \
 110                 "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip "      \
 111                 "addcons; bootm ${kernel_addr} - ${fdt_addr}\0"         \
 112         ""
 113 #define CONFIG_BOOTCOMMAND      "run flash_flash"
 114
 115 /*
 116  * Low level configuration
 117  */
 118
 119 /*
 120  * Clock configuration
 121  */
 122 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000        /* SYS_XTAL_IN = 33MHz */
 123 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK 1       /* IPB = 133MHz */
 124
 125 /*
 126  * Memory map
 127  */
 128 #define CONFIG_SYS_MBAR         0xF0000000
 129 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 130 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 131
 132 #define CONFIG_SYS_LOWBOOT              1
 133
 134 /* Use ON-Chip SRAM until RAM will be available */
 135 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 136 #ifdef CONFIG_POST
 137 /* preserve space for the post_word at end of on-chip SRAM */
 138 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_POST_SIZE
 139 #else
 140 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE
 141 #endif
 142
 143 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 144 #define CONFIG_BOARD_TYPES      1       /* we use board_type */
 145
 146 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 147
 148 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 149 #define CONFIG_SYS_MONITOR_LEN          (384 << 10)     /* 384 kB for Monitor */
 150 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)     /* 256 kB for malloc() */
 151 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* initial mem map for Linux */
 152
 153 /*
 154  * Flash configuration
 155  */
 156 #define CONFIG_SYS_FLASH_CFI            1
 157 #define CONFIG_FLASH_CFI_DRIVER 1
 158 #define CONFIG_SYS_FLASH_BASE           0xfc000000
 159 /* we need these despite using CFI */
 160 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks */
 161 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max num of sectors on one chip */
 162 #define CONFIG_SYS_FLASH_SIZE           0x02000000 /* 32 MiB */
 163
 164 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 165 #define CONFIG_SYS_RAMBOOT              1
 166 #undef CONFIG_SYS_LOWBOOT
 167 #endif
 168
 169 /*
 170  * Chip selects configuration
 171  */
 172 /* Boot Chipselect */
 173 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 174 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 175 #define CONFIG_SYS_BOOTCS_CFG           0x00087D31      /* for pci_clk = 33 MHz */
 176 /* use board_early_init_r to enable flash write in CS_BOOT */
 177 #define CONFIG_BOARD_EARLY_INIT_R
 178
 179 /* Flash memory addressing */
 180 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 181 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 182
 183 /* No burst, dead cycle = 1 for CS0 (Flash) */
 184 #define CONFIG_SYS_CS_BURST             0x00000000
 185 #define CONFIG_SYS_CS_DEADCYCLE 0x00000001
 186
 187 /*
 188  * SDRAM configuration
 189  * settings for k4s561632E-xx75, assuming XLB = 132 MHz
 190  */
 191 #define SDRAM_MODE      0x00CD0000      /* CASL 3, burst length 8 */
 192 #define SDRAM_CONTROL   0x514F0000
 193 #define SDRAM_CONFIG1   0xE2333900
 194 #define SDRAM_CONFIG2   0x8EE70000
 195
 196 /*
 197  * MTD configuration
 198  */
 199 #define CONFIG_CMD_MTDPARTS     1
 200 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 201 #define CONFIG_FLASH_CFI_MTD
 202 #define MTDIDS_DEFAULT          "nor0=cm5200-0"
 203 #define MTDPARTS_DEFAULT        "mtdparts=cm5200-0:"                    \
 204                                         "384k(uboot),128k(env),"        \
 205                                         "128k(redund_env),128k(dtb),"   \
 206                                         "2m(kernel),27904k(rootfs),"    \
 207                                         "-(config)"
 208
 209 /*
 210  * I2C configuration
 211  */
 212 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 213 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #2 */
 214 #define CONFIG_SYS_I2C_SPEED            40000   /* 40 kHz */
 215 #define CONFIG_SYS_I2C_SLAVE            0x0
 216 #define CONFIG_SYS_I2C_IO               0x38    /* PCA9554AD I2C I/O port address */
 217 #define CONFIG_SYS_I2C_EEPROM           0x53    /* I2C EEPROM device address */
 218
 219 /*
 220  * RTC configuration
 221  */
 222 #define CONFIG_RTC_MPC5200      1       /* use internal MPC5200 RTC */
 223
 224 /*
 225  * USB configuration
 226  */
 227 #define CONFIG_USB_OHCI         1
 228 #define CONFIG_USB_STORAGE      1
 229 #define CONFIG_USB_CLOCK        0x0001BBBB
 230 #define CONFIG_USB_CONFIG       0x00001000
 231 /* Partitions (for USB) */
 232 #define CONFIG_MAC_PARTITION    1
 233 #define CONFIG_DOS_PARTITION    1
 234 #define CONFIG_ISO_PARTITION    1
 235
 236 /*
 237  * Invoke our last_stage_init function - needed by fwupdate
 238  */
 239 #define CONFIG_LAST_STAGE_INIT  1
 240
 241 /*
 242  * Environment settings
 243  */
 244 #define CONFIG_ENV_IS_IN_FLASH  1
 245 #define CONFIG_ENV_SIZE         0x10000
 246 #define CONFIG_ENV_SECT_SIZE    0x20000
 247 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 248 /* Configuration of redundant environment */
 249 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 250 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 251
 252 /*
 253  * Pin multiplexing configuration
 254  */
 255
 256 /*
 257  * CS1/GPIO_WKUP_6: GPIO (default)
 258  * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1
 259  * IRDA/PSC6: UART
 260  * Ether: Ethernet 100Mbit with MD
 261  * PCI_DIS: PCI controller disabled
 262  * USB: USB
 263  * PSC3: SPI with UART3
 264  * PSC2: UART
 265  * PSC1: UART
 266  */
 267 #define CONFIG_SYS_GPS_PORT_CONFIG      0x10559C44
 268
 269 /*
 270  * Miscellaneous configurable options
 271  */
 272 #define CONFIG_SYS_LONGHELP             1       /* undef to save memory */
 273 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
 274 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 275 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 276 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 277
 278 #define CONFIG_SYS_ALT_MEMTEST          1
 279 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 280 #define CONFIG_SYS_MEMTEST_END          0x03f00000      /* 1 .. 63 MiB in SDRAM */
 281
 282 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 283
 284 /*
 285  * Various low-level settings
 286  */
 287 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 288 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 289
 290 #define CONFIG_SYS_XLB_PIPELINING       1       /* enable transaction pipeling */
 291
 292 /*
 293  * Cache Configuration
 294  */
 295 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
 296 #ifdef CONFIG_CMD_KGDB
 297 #define CONFIG_SYS_CACHELINE_SHIFT      5       /* log base 2 of the above value */
 298 #endif
 299
 300 /*
 301  * Flat Device Tree support
 302  */
 303 #define OF_CPU                  "PowerPC,5200@0"
 304 #define OF_SOC                  "soc5200@f0000000"
 305 #define OF_TBCLK                (bd->bi_busfreq / 4)
 306 #define OF_STDOUT_PATH          "/soc5200@f0000000/serial@2000"
 307
 308 #endif /* __CONFIG_H */