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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/cm5200.h
89a2d229da5cad295faac0396c36c997181995a8
2 * (C) Copyright 2003-2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
12 * High Level Configuration Options
14 #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
15 #define CONFIG_CM5200 1 /* ... on CM5200 platform */
17 #define CONFIG_SYS_TEXT_BASE 0xfc000000
19 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
24 #define CONFIG_CMD_DATE
25 #define CONFIG_CMD_DIAG
26 #define CONFIG_CMD_JFFS2
27 #define CONFIG_CMD_REGINFO
30 * Serial console configuration
32 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
33 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
36 * Ethernet configuration
38 #define CONFIG_MPC5xxx_FEC 1
39 #define CONFIG_MPC5xxx_FEC_MII100
40 #define CONFIG_PHY_ADDR 0x00
41 #define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */
42 /* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
43 #define CONFIG_MISC_INIT_R 1
44 #define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */
49 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU | CONFIG_SYS_POST_I2C)
50 #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
51 /* List of I2C addresses to be verified by POST */
52 #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_SLAVE, \
54 CONFIG_SYS_I2C_EEPROM}
56 /* display image timestamps */
57 #define CONFIG_TIMESTAMP 1
62 #define CONFIG_PREBOOT "echo;" \
63 "echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \
65 #undef CONFIG_BOOTARGS
68 * Default environment settings
70 #define CONFIG_EXTRA_ENV_SETTINGS \
72 "netmask=255.255.0.0\0" \
73 "ipaddr=192.168.160.33\0" \
74 "serverip=192.168.1.1\0" \
75 "gatewayip=192.168.1.1\0" \
77 "u-boot_addr=100000\0" \
78 "kernel_addr=200000\0" \
79 "kernel_addr_flash=fc0c0000\0" \
81 "fdt_addr_flash=fc0a0000\0" \
82 "ramdisk_addr=500000\0" \
83 "rootpath=/opt/eldk-4.1/ppc_6xx\0" \
84 "u-boot=/tftpboot/cm5200/u-boot.bin\0" \
85 "bootfile_fdt=/tftpboot/cm5200/uImage\0" \
86 "fdt_file=/tftpboot/cm5200/cm5200.dtb\0" \
87 "load=tftp ${u-boot_addr} ${u-boot}\0" \
88 "update=prot off fc000000 +${filesize}; " \
89 "era fc000000 +${filesize}; " \
90 "cp.b ${u-boot_addr} fc000000 ${filesize}; " \
91 "prot on fc000000 +${filesize}\0" \
92 "nfsargs=setenv bootargs root=/dev/nfs rw " \
93 "nfsroot=${serverip}:${rootpath}\0" \
94 "flashargs=setenv bootargs root=/dev/mtdblock5 rw\0" \
95 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
96 "addinit=setenv bootargs ${bootargs} init=/linuxrc\0" \
97 "addcons=setenv bootargs ${bootargs} " \
98 "console=${console},${baudrate}\0" \
99 "addip=setenv bootargs ${bootargs} " \
100 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
101 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
102 "flash_flash=run flashargs addinit addip addcons;" \
103 "bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0" \
104 "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; " \
105 "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip " \
106 "addcons; bootm ${kernel_addr} - ${fdt_addr}\0" \
108 #define CONFIG_BOOTCOMMAND "run flash_flash"
111 * Low level configuration
115 * Clock configuration
117 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */
118 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */
123 #define CONFIG_SYS_MBAR 0xF0000000
124 #define CONFIG_SYS_SDRAM_BASE 0x00000000
125 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
127 #define CONFIG_SYS_LOWBOOT 1
129 /* Use ON-Chip SRAM until RAM will be available */
130 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
132 /* preserve space for the post_word at end of on-chip SRAM */
133 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
135 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
138 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
139 #define CONFIG_BOARD_TYPES 1 /* we use board_type */
141 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
143 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
144 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */
145 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */
146 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */
149 * Flash configuration
151 #define CONFIG_SYS_FLASH_CFI 1
152 #define CONFIG_FLASH_CFI_DRIVER 1
153 #define CONFIG_SYS_FLASH_BASE 0xfc000000
154 /* we need these despite using CFI */
155 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
156 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sectors on one chip */
157 #define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */
159 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
160 #define CONFIG_SYS_RAMBOOT 1
161 #undef CONFIG_SYS_LOWBOOT
165 * Chip selects configuration
167 /* Boot Chipselect */
168 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
169 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
170 #define CONFIG_SYS_BOOTCS_CFG 0x00087D31 /* for pci_clk = 33 MHz */
171 /* use board_early_init_r to enable flash write in CS_BOOT */
172 #define CONFIG_BOARD_EARLY_INIT_R
174 /* Flash memory addressing */
175 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
176 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
178 /* No burst, dead cycle = 1 for CS0 (Flash) */
179 #define CONFIG_SYS_CS_BURST 0x00000000
180 #define CONFIG_SYS_CS_DEADCYCLE 0x00000001
183 * SDRAM configuration
184 * settings for k4s561632E-xx75, assuming XLB = 132 MHz
186 #define SDRAM_MODE 0x00CD0000 /* CASL 3, burst length 8 */
187 #define SDRAM_CONTROL 0x514F0000
188 #define SDRAM_CONFIG1 0xE2333900
189 #define SDRAM_CONFIG2 0x8EE70000
194 #define CONFIG_CMD_MTDPARTS 1
195 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
196 #define CONFIG_FLASH_CFI_MTD
197 #define MTDIDS_DEFAULT "nor0=cm5200-0"
198 #define MTDPARTS_DEFAULT "mtdparts=cm5200-0:" \
199 "384k(uboot),128k(env)," \
200 "128k(redund_env),128k(dtb)," \
201 "2m(kernel),27904k(rootfs)," \
207 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
208 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
209 #define CONFIG_SYS_I2C_SPEED 40000 /* 40 kHz */
210 #define CONFIG_SYS_I2C_SLAVE 0x0
211 #define CONFIG_SYS_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */
212 #define CONFIG_SYS_I2C_EEPROM 0x53 /* I2C EEPROM device address */
217 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
222 #define CONFIG_USB_OHCI 1
223 #define CONFIG_USB_CLOCK 0x0001BBBB
224 #define CONFIG_USB_CONFIG 0x00001000
225 /* Partitions (for USB) */
228 * Invoke our last_stage_init function - needed by fwupdate
230 #define CONFIG_LAST_STAGE_INIT 1
233 * Environment settings
235 #define CONFIG_ENV_IS_IN_FLASH 1
236 #define CONFIG_ENV_SIZE 0x10000
237 #define CONFIG_ENV_SECT_SIZE 0x20000
238 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
239 /* Configuration of redundant environment */
240 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
241 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
244 * Pin multiplexing configuration
248 * CS1/GPIO_WKUP_6: GPIO (default)
249 * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1
251 * Ether: Ethernet 100Mbit with MD
252 * PCI_DIS: PCI controller disabled
254 * PSC3: SPI with UART3
258 #define CONFIG_SYS_GPS_PORT_CONFIG 0x10559C44
261 * Miscellaneous configurable options
263 #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
264 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
265 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
266 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
267 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
269 #define CONFIG_SYS_ALT_MEMTEST 1
270 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
271 #define CONFIG_SYS_MEMTEST_END 0x03f00000 /* 1 .. 63 MiB in SDRAM */
273 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
276 * Various low-level settings
278 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
279 #define CONFIG_SYS_HID0_FINAL HID0_ICE
281 #define CONFIG_SYS_XLB_PIPELINING 1 /* enable transaction pipeling */
284 * Cache Configuration
286 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
287 #ifdef CONFIG_CMD_KGDB
288 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
292 * Flat Device Tree support
294 #define OF_CPU "PowerPC,5200@0"
295 #define OF_SOC "soc5200@f0000000"
296 #define OF_TBCLK (bd->bi_busfreq / 4)
297 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
299 #endif /* __CONFIG_H */