include/configs/cmc_pu2.h

   1 /*
   2  * 2004-2005 Gary Jennejohn <garyj@denx.de>
   3  *
   4  * Configuration settings for the CMC PU2 board.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef __CONFIG_H
  26 #define __CONFIG_H
  27
  28 /*
  29  * If we are developing, we might want to start armboot from ram
  30  * so we MUST NOT initialize critical regs like mem-timing ...
  31  */
  32 #define CONFIG_INIT_CRITICAL            /* undef for developing */
  33
  34 /* ARM asynchronous clock */
  35 #define AT91C_MAIN_CLOCK        207360000       /* from 18.432 MHz crystal (18432000 / 4 * 45) */
  36 #define AT91C_MASTER_CLOCK      69120000        /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
  37
  38 #define AT91_SLOW_CLOCK         32768   /* slow clock */
  39
  40 #define CONFIG_AT91RM9200DK     1       /* on an AT91RM9200DK Board      */
  41 #define CONFIG_CMC_PU2          1       /* on an CMC_PU2 Board   */
  42 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
  43 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs      */
  44 #define CONFIG_SETUP_MEMORY_TAGS 1
  45 #define CONFIG_INITRD_TAG       1
  46
  47 /* define this to include the functionality of boot.bin in u-boot */
  48 #define CONFIG_BOOTBINFUNC
  49
  50 /* just to make sure */
  51 #ifndef CONFIG_BOOTBINFUNC
  52 #define CONFIG_BOOTBINFUNC
  53 #endif
  54
  55 #ifdef CONFIG_BOOTBINFUNC
  56 #define CFG_USE_MAIN_OSCILLATOR         1
  57 /* flash */
  58 #define MC_PUIA_VAL     0x00000000
  59 #define MC_PUP_VAL      0x00000000
  60 #define MC_PUER_VAL     0x00000000
  61 #define MC_ASR_VAL      0x00000000
  62 #define MC_AASR_VAL     0x00000000
  63 #define EBI_CFGR_VAL    0x00000000
  64 #define SMC2_CSR_VAL    0x100032ad /* 16bit, 2 TDF, 4 WS */
  65
  66 /* clocks */
  67 #define PLLAR_VAL       0x202CBE04 /* 207.360 MHz for PCK */
  68 #define PLLBR_VAL       0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
  69 #define MCKR_VAL        0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
  70
  71 /* sdram */
  72 #define PIOC_ASR_VAL    0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
  73 #define PIOC_BSR_VAL    0x00000000
  74 #define PIOC_PDR_VAL    0xFFFF0000
  75 #define EBI_CSA_VAL     0x00000002 /* CS1=SDRAM */
  76 #define SDRC_CR_VAL     0x3399c1d4 /* set up the SDRAM */
  77 #define SDRAM           0x20000000 /* address of the SDRAM */
  78 #define SDRAM1          0x20000080 /* address of the SDRAM */
  79 #define SDRAM_VAL       0x00000000 /* value written to SDRAM */
  80 #define SDRC_MR_VAL     0x00000002 /* Precharge All */
  81 #define SDRC_MR_VAL1    0x00000004 /* refresh */
  82 #define SDRC_MR_VAL2    0x00000003 /* Load Mode Register */
  83 #define SDRC_MR_VAL3    0x00000000 /* Normal Mode */
  84 #define SDRC_TR_VAL     0x000002E0 /* Write refresh rate */
  85 #endif
  86
  87 /*
  88  * Size of malloc() pool
  89  */
  90 #define CFG_MALLOC_LEN  (CFG_ENV_SIZE + 128*1024)
  91 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
  92
  93 #define CONFIG_BAUDRATE         9600
  94
  95 #define CFG_AT91C_BRGR_DIVISOR  450     /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK /(baudrate * 16) */
  96
  97 /*
  98  * Hardware drivers
  99  */
 100
 101 /* define one of these to choose the DBGU, USART0  or USART1 as console */
 102 #undef CONFIG_DBGU
 103 #define CONFIG_USART0
 104 #undef CONFIG_USART1
 105
 106 #undef  CONFIG_HWFLOW                   /* don't include RTS/CTS flow control support   */
 107
 108 #undef  CONFIG_MODEM_SUPPORT            /* disable modem initialization stuff */
 109
 110 #define CONFIG_HARD_I2C
 111
 112 #ifdef CONFIG_HARD_I2C
 113 #define CFG_I2C_SPEED           0       /* not used */
 114 #define CFG_I2C_SLAVE           0       /* not used */
 115 #define CONFIG_RTC_RS5C372A             /* RICOH I2C RTC */
 116 #define CFG_I2C_RTC_ADDR        0x32
 117 #define CFG_I2C_EEPROM_ADDR     0x50
 118 #define CFG_I2C_EEPROM_ADDR_LEN 1
 119 #define CFG_I2C_EEPROM_ADDR_OVERFLOW
 120 #endif
 121 /* still about 20 kB free with this defined */
 122 #define CFG_LONGHELP
 123
 124 #define CONFIG_BOOTDELAY      3
 125
 126 #ifdef CONFIG_HARD_I2C
 127 #define CONFIG_COMMANDS         \
 128                        ((CONFIG_CMD_DFL | \
 129                         CFG_CMD_DATE    | \
 130                         CFG_CMD_DHCP    | \
 131                         CFG_CMD_EEPROM  | \
 132                         CFG_CMD_I2C     | \
 133                         CFG_CMD_NFS     | \
 134                         CFG_CMD_SNTP  ) & \
 135                       ~(CFG_CMD_FPGA | CFG_CMD_MISC) )
 136 #else
 137 #define CONFIG_COMMANDS         \
 138                        ((CONFIG_CMD_DFL | \
 139                         CFG_CMD_DHCP    | \
 140                         CFG_CMD_NFS     | \
 141                         CFG_CMD_SNTP  ) & \
 142                       ~(CFG_CMD_FPGA | CFG_CMD_MISC) )
 143 #define CONFIG_TIMESTAMP
 144 #endif
 145 #define CFG_LONGHELP
 146
 147 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 148 #include <cmd_confdefs.h>
 149
 150 #define AT91_SMART_MEDIA_ALE    (1 << 22)       /* our ALE is AD22 */
 151 #define AT91_SMART_MEDIA_CLE    (1 << 21)       /* our CLE is AD21 */
 152
 153 #define CONFIG_NR_DRAM_BANKS    1
 154 #define PHYS_SDRAM              0x20000000
 155 #define PHYS_SDRAM_SIZE         0x1000000       /* 16 megs */
 156
 157 #define CFG_MEMTEST_START               PHYS_SDRAM
 158 #define CFG_MEMTEST_END                 CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
 159
 160 #define CONFIG_DRIVER_ETHER
 161 #define CONFIG_NET_RETRY_COUNT          20
 162 #define CONFIG_AT91C_USE_RMII
 163
 164 #define CONFIG_HAS_DATAFLASH            1
 165 #define CFG_SPI_WRITE_TOUT              (5*CFG_HZ)
 166 #define CFG_MAX_DATAFLASH_BANKS         2
 167 #define CFG_MAX_DATAFLASH_PAGES         16384
 168 #define CFG_DATAFLASH_LOGIC_ADDR_CS0    0xC0000000      /* Logical adress for CS0 */
 169 #define CFG_DATAFLASH_LOGIC_ADDR_CS3    0xD0000000      /* Logical adress for CS3 */
 170
 171 #define PHYS_FLASH_1                    0x10000000
 172 #define PHYS_FLASH_SIZE                 0x800000  /* 8 megs main flash */
 173 #define CFG_FLASH_BASE                  PHYS_FLASH_1
 174 #define CFG_MONITOR_BASE                CFG_FLASH_BASE
 175 #define CFG_MAX_FLASH_BANKS             1
 176 #define CFG_MAX_FLASH_SECT              256
 177 #define CFG_FLASH_ERASE_TOUT            (11 * CFG_HZ)   /* Timeout for Flash Erase */
 178 #define CFG_FLASH_WRITE_TOUT            ( 2 * CFG_HZ)   /* Timeout for Flash Write */
 179
 180 #define CFG_ENV_IS_IN_FLASH             1
 181 #define CFG_ENV_OFFSET                  0x20000         /* after u-boot.bin */
 182 #define CFG_ENV_SECT_SIZE               (64 << 10)      /* sectors are 64 kB */
 183 #define CFG_ENV_SIZE                    (16 << 10)      /* Use only 16 kB */
 184
 185 #define CFG_LOAD_ADDR           0x21000000  /* default load address */
 186
 187 #define CFG_BAUDRATE_TABLE      { 115200, 57600, 38400, 19200, 9600 }
 188
 189 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt */
 190 #define CFG_CBSIZE              256             /* Console I/O Buffer Size */
 191 #define CFG_MAXARGS             32              /* max number of command args */
 192 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 193
 194 #ifndef __ASSEMBLY__
 195 /*-----------------------------------------------------------------------
 196  * Board specific extension for bd_info
 197  *
 198  * This structure is embedded in the global bd_info (bd_t) structure
 199  * and can be used by the board specific code (eg board/...)
 200  */
 201
 202 struct bd_info_ext {
 203         /* helper variable for board environment handling
 204          *
 205          * env_crc_valid == 0    =>   uninitialised
 206          * env_crc_valid  > 0    =>   environment crc in flash is valid
 207          * env_crc_valid  < 0    =>   environment crc in flash is invalid
 208          */
 209         int env_crc_valid;
 210 };
 211 #endif  /* __ASSEMBLY__ */
 212
 213 #define CFG_HZ 1000
 214 #define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2       /* AT91C_TC0_CMR is implicitly set to */
 215                                         /* AT91C_TC_TIMER_DIV1_CLOCK */
 216
 217 #define CONFIG_STACKSIZE        (32*1024)       /* regular stack */
 218
 219 #ifdef CONFIG_USE_IRQ
 220 #error CONFIG_USE_IRQ not supported
 221 #endif
 222
 223 #endif  /* __CONFIG_H */