include/configs/cmi_mpc5xx.h

   1 /*
   2  * (C) Copyright 2003
   3  * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * File:                cmi_mpc5xx.h
  10  *
  11  * Discription:         Config header file for cmi
  12  *                      board  using an MPC5xx CPU
  13  *
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 #define CONFIG_MPC555           1               /* This is an MPC555 CPU                */
  24 #define CONFIG_CMI              1               /* Using the customized cmi board       */
  25
  26 #define CONFIG_SYS_TEXT_BASE    0x02000000      /* Boot from flash at location 0x00000000 */
  27
  28 /* Serial Console Configuration */
  29 #define CONFIG_5xx_CONS_SCI1
  30 #undef  CONFIG_5xx_CONS_SCI2
  31
  32 #define CONFIG_BAUDRATE         57600
  33
  34
  35 /*
  36  * BOOTP options
  37  */
  38 #define CONFIG_BOOTP_BOOTFILESIZE
  39 #define CONFIG_BOOTP_BOOTPATH
  40 #define CONFIG_BOOTP_GATEWAY
  41 #define CONFIG_BOOTP_HOSTNAME
  42
  43
  44 /*
  45  * Command line configuration.
  46  */
  47 #include <config_cmd_default.h>
  48
  49 #undef  CONFIG_CMD_NET          /* disabeled - causes compile errors */
  50 #undef  CONFIG_CMD_NFS
  51
  52 #define CONFIG_CMD_MEMORY
  53 #define CONFIG_CMD_LOADB
  54 #define CONFIG_CMD_REGINFO
  55 #define CONFIG_CMD_FLASH
  56 #define CONFIG_CMD_LOADS
  57 #define CONFIG_CMD_ASKENV
  58 #define CONFIG_CMD_BDI
  59 #define CONFIG_CMD_CONSOLE
  60 #define CONFIG_CMD_SAVEENV
  61 #define CONFIG_CMD_RUN
  62 #define CONFIG_CMD_IMI
  63
  64
  65 #if 0
  66 #define CONFIG_BOOTDELAY        -1              /* autoboot disabled                    */
  67 #else
  68 #define CONFIG_BOOTDELAY        5               /* autoboot after 5 seconds             */
  69 #endif
  70 #define CONFIG_BOOTCOMMAND      "go 02034004"   /* autoboot command                     */
  71
  72 #define CONFIG_BOOTARGS         ""              /* Assuming OS Image in 4 flash sector at offset 4004 */
  73
  74 #define CONFIG_WATCHDOG                         /* turn on platform specific watchdog   */
  75
  76 #define CONFIG_STATUS_LED       1               /* Enable status led */
  77
  78 #define CONFIG_LOADS_ECHO       1               /* Echo on for serial download */
  79
  80 /*
  81  * Miscellaneous configurable options
  82  */
  83
  84 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
  85 #define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt       */
  86 #if defined(CONFIG_CMD_KGDB)
  87 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size      */
  88 #else
  89 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
  90 #endif
  91 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  92 #define CONFIG_SYS_MAXARGS              16             /* max number of command args    */
  93 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  94
  95 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest works on             */
  96 #define CONFIG_SYS_MEMTEST_END          0x000fa000      /* 1 MB in SRAM                 */
  97
  98 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address         */
  99
 100 #define CONFIG_SYS_HZ                   1000            /* Decrementer freq: 1 ms ticks */
 101
 102 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 1250000 }
 103
 104
 105 /*
 106  * Low Level Configuration Settings
 107  */
 108
 109 /*
 110  * Internal Memory Mapped (This is not the IMMR content)
 111  */
 112 #define CONFIG_SYS_IMMR         0x01000000              /* Physical start adress of internal memory map */
 113
 114 /*
 115  * Definitions for initial stack pointer and data area
 116  */
 117 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_IMMR + 0x003f9800)  /* Physical start adress of internal MPC555 writable RAM */
 118 #define CONFIG_SYS_INIT_RAM_SIZE        (CONFIG_SYS_IMMR + 0x003fffff)  /* Physical end adress of internal MPC555 used RAM area */
 119 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
 120 #define CONFIG_SYS_INIT_SP_ADDR 0x013fa000              /* Physical start adress of inital stack */
 121
 122 /*
 123  * Start addresses for the final memory configuration
 124  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 125  */
 126 #define CONFIG_SYS_SDRAM_BASE           0x00000000      /* Monitor won't change memory map                      */
 127 #define CONFIG_SYS_FLASH_BASE           0x02000000      /* External flash */
 128 #define PLD_BASE                0x03000000      /* PLD  */
 129 #define ANYBUS_BASE             0x03010000      /* Anybus Module */
 130
 131 #define CONFIG_SYS_RESET_ADRESS 0x01000000      /* Adress which causes reset */
 132 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE   /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */
 133                                                 /* This adress is given to the linker with -Ttext to    */
 134                                                 /* locate the text section at this adress.              */
 135 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor                           */
 136 #define CONFIG_SYS_MALLOC_LEN           (64 << 10)      /* Reserve 128 kB for malloc()                          */
 137
 138 /*
 139  * For booting Linux, the board info and command line data
 140  * have to be in the first 8 MB of memory, since this is
 141  * the maximum mapped by the Linux kernel during initialization.
 142  */
 143 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux         */
 144
 145
 146 /*-----------------------------------------------------------------------
 147  * FLASH organization
 148  *-----------------------------------------------------------------------
 149  *
 150  */
 151
 152 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* Max number of memory banks           */
 153 #define CONFIG_SYS_MAX_FLASH_SECT       64              /* Max number of sectors on one chip    */
 154 #define CONFIG_SYS_FLASH_ERASE_TOUT     180000          /* Timeout for Flash Erase (in ms)      */
 155 #define CONFIG_SYS_FLASH_WRITE_TOUT     600             /* Timeout for Flash Write (in ms)      */
 156 #define CONFIG_SYS_FLASH_PROTECTION    1                /* Physically section protection on     */
 157
 158 #define CONFIG_ENV_IS_IN_FLASH  1
 159
 160 #ifdef  CONFIG_ENV_IS_IN_FLASH
 161 #define CONFIG_ENV_OFFSET               0x00020000      /* Environment starts at this adress    */
 162 #define CONFIG_ENV_SIZE         0x00010000      /* Set whole sector as env              */
 163 #define CONFIG_SYS_USE_PPCENV                           /* Environment embedded in sect .ppcenv */
 164 #endif
 165
 166 /*-----------------------------------------------------------------------
 167  * SYPCR - System Protection Control
 168  * SYPCR can only be written once after reset!
 169  *-----------------------------------------------------------------------
 170  * SW Watchdog freeze
 171  */
 172 #if defined(CONFIG_WATCHDOG)
 173 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 174                          SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
 175 #else
 176 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 177                          SYPCR_SWP)
 178 #endif  /* CONFIG_WATCHDOG */
 179
 180 /*-----------------------------------------------------------------------
 181  * TBSCR - Time Base Status and Control
 182  *-----------------------------------------------------------------------
 183  * Clear Reference Interrupt Status, Timebase freezing enabled
 184  */
 185 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 186
 187 /*-----------------------------------------------------------------------
 188  * PISCR - Periodic Interrupt Status and Control
 189  *-----------------------------------------------------------------------
 190  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 191  */
 192 #define CONFIG_SYS_PISCR        (PISCR_PITF)
 193
 194 /*-----------------------------------------------------------------------
 195  * SCCR - System Clock and reset Control Register
 196  *-----------------------------------------------------------------------
 197  * Set clock output, timebase and RTC source and divider,
 198  * power management and some other internal clocks
 199  */
 200 #define SCCR_MASK       SCCR_EBDF00
 201 #define CONFIG_SYS_SCCR (SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
 202                          SCCR_COM00   | SCCR_DFNL000 | SCCR_DFNH000)
 203
 204 /*-----------------------------------------------------------------------
 205  * SIUMCR - SIU Module Configuration
 206  *-----------------------------------------------------------------------
 207  * Data show cycle
 208  */
 209 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00)         /* Disable data show cycle      */
 210
 211 /*-----------------------------------------------------------------------
 212  * PLPRCR - PLL, Low-Power, and Reset Control Register
 213  *-----------------------------------------------------------------------
 214  * Set all bits to 40 Mhz
 215  *
 216  */
 217 #define CONFIG_SYS_OSC_CLK      ((uint)4000000)         /* Oscillator clock is 4MHz     */
 218 #define CONFIG_SYS_PLPRCR       (PLPRCR_MF_9 | PLPRCR_DIVF_0)
 219
 220
 221 /*-----------------------------------------------------------------------
 222  * UMCR - UIMB Module Configuration Register
 223  *-----------------------------------------------------------------------
 224  *
 225  */
 226 #define CONFIG_SYS_UMCR (UMCR_FSPEED)           /* IMB clock same as U-bus      */
 227
 228 /*-----------------------------------------------------------------------
 229  * ICTRL - I-Bus Support Control Register
 230  */
 231 #define CONFIG_SYS_ICTRL        (ICTRL_ISCT_SER_7)      /* Take out of serialized mode  */
 232
 233 /*-----------------------------------------------------------------------
 234  * USIU - Memory Controller Register
 235  *-----------------------------------------------------------------------
 236  */
 237
 238 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16)
 239 #define CONFIG_SYS_OR0_PRELIM           (OR_ADDR_MK_FF | OR_SCY_3)
 240 #define CONFIG_SYS_BR1_PRELIM           (ANYBUS_BASE)
 241 #define CONFIG_SYS_OR1_PRELIM           (OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR)
 242 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_SDRAM_BASE | BR_V | BR_PS_32)
 243 #define CONFIG_SYS_OR2_PRELIM           (OR_ADDR_MK_FF)
 244 #define CONFIG_SYS_BR3_PRELIM           (PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8)
 245 #define CONFIG_SYS_OR3_PRELIM           (OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \
 246                                  OR_ACS_10 | OR_ETHR | OR_CSNT)
 247
 248 #define FLASH_BASE0_PRELIM      CONFIG_SYS_FLASH_BASE   /* We don't realign the flash   */
 249
 250 /*-----------------------------------------------------------------------
 251  * DER - Timer Decrementer
 252  *-----------------------------------------------------------------------
 253  * Initialise to zero
 254  */
 255 #define CONFIG_SYS_DER                  0x00000000
 256
 257 #endif  /* __CONFIG_H */