include/configs/cogent_mpc8xx.h

   1 /*
   2  * (C) Copyright 2000-2010
   3  * Murray Jensen <Murray.Jensen@cmst.csiro.au>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * Config header file for Cogent platform using an MPC8xx CPU module
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC860           1       /* This is an MPC860 CPU        */
  37 #define CONFIG_COGENT           1       /* using Cogent Modular Architecture */
  38
  39 #define CONFIG_SYS_TEXT_BASE    0xfff00000
  40
  41 #define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()            */
  42 #define CONFIG_MISC_INIT_R              /* Use misc_init_r()            */
  43
  44 /* Cogent Modular Architecture options */
  45 #define CONFIG_CMA286_60_OLD    1       /* ...on an old CMA286-60 CPU module */
  46 #define CONFIG_CMA102           1       /* ...on a CMA102 motherboard   */
  47 #define CONFIG_CMA302           1       /* ...with a CMA302 flash I/O module */
  48
  49 /* serial console configuration */
  50 #undef  CONFIG_8xx_CONS_SMC1
  51 #undef  CONFIG_8xx_CONS_SMC2
  52 #define CONFIG_8xx_CONS_NONE    /* not on 8xx serial ports (eg on cogent m/b) */
  53
  54 #if defined(CONFIG_CMA286_60_OLD)
  55 #define CONFIG_8xx_GCLK_FREQ    33333000 /* define if cant use get_gclk_freq */
  56 #endif
  57
  58 #define CONFIG_BAUDRATE         230400
  59
  60 #define CONFIG_HARD_I2C         /* I2C with hardware support */
  61 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
  62 #define CONFIG_SYS_I2C_SLAVE            0x7F
  63
  64
  65 /*
  66  * BOOTP options
  67  */
  68 #define CONFIG_BOOTP_BOOTFILESIZE
  69 #define CONFIG_BOOTP_BOOTPATH
  70 #define CONFIG_BOOTP_GATEWAY
  71 #define CONFIG_BOOTP_HOSTNAME
  72
  73
  74 /*
  75  * Command line configuration.
  76  */
  77 #include <config_cmd_default.h>
  78
  79 #define CONFIG_CMD_KGDB
  80 #define CONFIG_CMD_I2C
  81
  82 #undef CONFIG_CMD_NET
  83 #undef CONFIG_CMD_NFS
  84
  85 #if 0
  86 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  87 #else
  88 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  89 #endif
  90 #define CONFIG_BOOTCOMMAND      "bootm 04080000 04200000" /* autoboot command*/
  91
  92 #define CONFIG_BOOTARGS         "root=/dev/ram rw"
  93
  94 #if defined(CONFIG_CMD_KGDB)
  95 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
  96 #undef  CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
  97 #define CONFIG_KGDB_NONE                /* define if kgdb on something else */
  98 #define CONFIG_KGDB_INDEX       2       /* which SMC/SCC channel for kgdb */
  99 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 100 #endif
 101
 102 #define CONFIG_WATCHDOG                 /* turn on platform specific watchdog */
 103
 104 /*
 105  * Miscellaneous configurable options
 106  */
 107 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 108 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 109 #if defined(CONFIG_CMD_KGDB)
 110 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 111 #else
 112 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 113 #endif
 114 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 115 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 116 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 117
 118 #define CONFIG_SYS_MEMTEST_START        0x00400000      /* memtest works on     */
 119 #define CONFIG_SYS_MEMTEST_END          0x01c00000      /* 4 ... 28 MB in DRAM  */
 120
 121 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 122
 123 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 124
 125 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 126
 127 #define CONFIG_SYS_ALLOC_DPRAM
 128
 129 /*
 130  * Low Level Configuration Settings
 131  * (address mappings, register initial values, etc.)
 132  * You should know what you are doing if you make changes here.
 133  */
 134
 135 /*-----------------------------------------------------------------------
 136  * Low Level Cogent settings
 137  * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not.
 138  * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
 139  * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
 140  * (second 2 for CMA120 only)
 141  */
 142 #define CONFIG_SYS_CMA_MB_BASE          0x00000000      /* base of m/b address space */
 143
 144 #include <configs/cogent_common.h>
 145
 146 #define CONFIG_SYS_CMA_CONS_SERIAL      /* use Cogent motherboard serial for console */
 147 #define CONFIG_CONS_INDEX       1
 148 #define CONFIG_SYS_CMA_LCD_HEARTBEAT    /* define for sec rotator in lcd corner */
 149 #define CONFIG_SHOW_ACTIVITY
 150 #if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
 151 /*
 152  * flash exists on the motherboard
 153  * set these four according to TOP dipsw:
 154  * TOP on  => ..._FLLOW_...     (boot EPROM space is high so FLASH is low )
 155  * TOP off => ..._FLHIGH_...    (boot EPROM space is low  so FLASH is high)
 156  */
 157 #define CMA_MB_FLASH_EXEC_BASE  CMA_MB_FLLOW_EXEC_BASE
 158 #define CMA_MB_FLASH_EXEC_SIZE  CMA_MB_FLLOW_EXEC_SIZE
 159 #define CMA_MB_FLASH_RDWR_BASE  CMA_MB_FLLOW_RDWR_BASE
 160 #define CMA_MB_FLASH_RDWR_SIZE  CMA_MB_FLLOW_RDWR_SIZE
 161 #endif
 162 #define CMA_MB_FLASH_BASE       CMA_MB_FLASH_EXEC_BASE
 163 #define CMA_MB_FLASH_SIZE       CMA_MB_FLASH_EXEC_SIZE
 164
 165 /*-----------------------------------------------------------------------
 166  * Internal Memory Mapped Register
 167  */
 168 #define CONFIG_SYS_IMMR         0xFF000000
 169
 170 /*-----------------------------------------------------------------------
 171  * Definitions for initial stack pointer and data area (in DPRAM)
 172  */
 173 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 174 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 175 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 176 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 177
 178 /*-----------------------------------------------------------------------
 179  * Start addresses for the final memory configuration
 180  * (Set up by the startup code)
 181  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 182  */
 183 #define CONFIG_SYS_SDRAM_BASE           CMA_MB_RAM_BASE
 184 #ifdef CONFIG_CMA302
 185 #define CONFIG_SYS_FLASH_BASE           CMA_MB_SLOT2_BASE       /* cma302 in slot 2 */
 186 #else
 187 #define CONFIG_SYS_FLASH_BASE           CMA_MB_FLASH_BASE       /* flash on m/b */
 188 #endif
 189 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 190 #define CONFIG_SYS_MONITOR_LEN          (128 << 10)     /* Reserve 128 kB for Monitor   */
 191 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 192
 193 /*
 194  * For booting Linux, the board info and command line data
 195  * have to be in the first 8 MB of memory, since this is
 196  * the maximum mapped by the Linux kernel during initialization.
 197  */
 198 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 199 /*-----------------------------------------------------------------------
 200  * FLASH organization
 201  */
 202 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 203 #define CONFIG_SYS_MAX_FLASH_SECT       67      /* max number of sectors on one chip    */
 204
 205 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 206 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 207
 208 #define CONFIG_ENV_IS_IN_FLASH  1
 209 #define CONFIG_ENV_ADDR         CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
 210 #ifdef CONFIG_CMA302
 211 #define CONFIG_ENV_SIZE         0x1000  /* Total Size of Environment Sector     */
 212 #define CONFIG_ENV_SECT_SIZE    (512*1024) /* see README - env sect real size */
 213 #else
 214 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 215 #endif
 216 /*-----------------------------------------------------------------------
 217  * Cache Configuration
 218  */
 219 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 220 #if defined(CONFIG_CMD_KGDB)
 221 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 222 #endif
 223
 224
 225 /*-----------------------------------------------------------------------
 226  * SYPCR - System Protection Control                            11-9
 227  * SYPCR can only be written once after reset!
 228  *-----------------------------------------------------------------------
 229  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 230  */
 231 #if defined(CONFIG_WATCHDOG)
 232 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 233                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 234 #else
 235 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 236 #endif  /* CONFIG_WATCHDOG */
 237
 238 /*-----------------------------------------------------------------------
 239  * SIUMCR - SIU Module Configuration                            11-6
 240  *-----------------------------------------------------------------------
 241  * PCMCIA config., multi-function pin tri-state
 242  */
 243 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 244
 245 /*-----------------------------------------------------------------------
 246  * TBSCR - Time Base Status and Control                         11-26
 247  *-----------------------------------------------------------------------
 248  * Clear Reference Interrupt Status, Timebase freezing enabled
 249  */
 250 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 251
 252 /*-----------------------------------------------------------------------
 253  * PISCR - Periodic Interrupt Status and Control                11-31
 254  *-----------------------------------------------------------------------
 255  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 256  */
 257 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 258
 259 /*-----------------------------------------------------------------------
 260  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 261  *-----------------------------------------------------------------------
 262  * Reset PLL lock status sticky bit, timer expired status bit and timer
 263  * interrupt status bit - leave PLL multiplication factor unchanged !
 264  */
 265 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 266
 267 /*-----------------------------------------------------------------------
 268  * SCCR - System Clock and reset Control Register               15-27
 269  *-----------------------------------------------------------------------
 270  * Set clock output, timebase and RTC source and divider,
 271  * power management and some other internal clocks
 272  */
 273 #define SCCR_MASK       SCCR_EBDF11
 274 #define CONFIG_SYS_SCCR (SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
 275                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 276                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 277                          SCCR_DFALCD00)
 278
 279 /*-----------------------------------------------------------------------
 280  * PCMCIA stuff
 281  *-----------------------------------------------------------------------
 282  *
 283  */
 284 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 285 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 286 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 287 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 288 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 289 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 290 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 291 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 292
 293 /*-----------------------------------------------------------------------
 294  *
 295  *-----------------------------------------------------------------------
 296  *
 297  */
 298 /*#define       CONFIG_SYS_DER  0x2002000F*/
 299 #define CONFIG_SYS_DER  0
 300
 301 #if defined(CONFIG_CMA286_60_OLD)
 302
 303 /*
 304  * Init Memory Controller:
 305  *
 306  * NOTE: although the names (CONFIG_SYS_xRn_PRELIM) suggest preliminary settings,
 307  * they are actually the final settings for this cpu/board, because the
 308  * flash and RAM are on the motherboard, accessed via the CMAbus, and the
 309  * mappings are pretty much fixed.
 310  *
 311  * (the *_SIZE vars must be a power of 2)
 312  */
 313
 314 #define CONFIG_SYS_CMA_CS0_BASE CONFIG_SYS_TEXT_BASE            /* EPROM */
 315 #define CONFIG_SYS_CMA_CS0_SIZE (1 << 20)
 316 #define CONFIG_SYS_CMA_CS1_BASE CMA_MB_RAM_BASE         /* RAM + I/O SLOT 1 */
 317 #define CONFIG_SYS_CMA_CS1_SIZE (64 << 20)
 318 #define CONFIG_SYS_CMA_CS2_BASE CMA_MB_SLOT2_BASE       /* I/O SLOTS 2 + 3 */
 319 #define CONFIG_SYS_CMA_CS2_SIZE (64 << 20)
 320 #define CONFIG_SYS_CMA_CS3_BASE CMA_MB_ROMLOW_BASE      /* M/B I/O */
 321 #define CONFIG_SYS_CMA_CS3_SIZE (32 << 20)
 322
 323 /*
 324  * CS0 maps the EPROM on the cpu module
 325  * Set it for 4 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
 326  *
 327  * Note: We must have already transferred control to the final location
 328  * of the EPROM before these are used, because when BR0/OR0 are set, the
 329  * mirror of the eprom at any other addresses will disappear.
 330  */
 331
 332 /* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */
 333 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_CMA_CS0_BASE&BR_BA_MSK)|BR_PS_16|BR_WP|BR_V)
 334 /* mask size CONFIG_SYS_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */
 335 #define CONFIG_SYS_OR0_PRELIM   ((~(CONFIG_SYS_CMA_CS0_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SCY_4_CLK)
 336
 337 /*
 338  * CS1 maps motherboard DRAM and motherboard I/O slot 1
 339  * (each 32Mbyte in size)
 340  */
 341
 342 /* base address = CONFIG_SYS_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */
 343 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_CMA_CS1_BASE&BR_BA_MSK)|BR_V)
 344 /* mask size CONFIG_SYS_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */
 345 #define CONFIG_SYS_OR1_PRELIM   ((~(CONFIG_SYS_CMA_CS1_SIZE-1)&OR_AM_MSK)|OR_SETA)
 346
 347 /*
 348  * CS2 maps motherboard I/O slots 2 and 3
 349  * (each 32Mbyte in size)
 350  */
 351
 352 /* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */
 353 #define CONFIG_SYS_BR2_PRELIM   ((CONFIG_SYS_CMA_CS2_BASE&BR_BA_MSK)|BR_V)
 354 /* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */
 355 #define CONFIG_SYS_OR2_PRELIM   ((~(CONFIG_SYS_CMA_CS2_SIZE-1)&OR_AM_MSK)|OR_SETA)
 356
 357 /*
 358  * CS3 maps motherboard I/O
 359  * (32Mbyte in size)
 360  */
 361
 362 /* base address = CONFIG_SYS_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */
 363 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_CMA_CS3_BASE&BR_BA_MSK)|BR_V)
 364 /* mask size CONFIG_SYS_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */
 365 #define CONFIG_SYS_OR3_PRELIM   ((~(CONFIG_SYS_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA)
 366
 367 #endif
 368 #endif  /* __CONFIG_H */