include/configs/cogent_mpc8xx.h

   1 /*
   2  * (C) Copyright 2000
   3  * Murray Jensen <Murray.Jensen@cmst.csiro.au>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * Config header file for Cogent platform using an MPC8xx CPU module
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC860           1       /* This is an MPC860 CPU        */
  37 #define CONFIG_COGENT           1       /* using Cogent Modular Architecture */
  38
  39 #define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()            */
  40
  41 /* Cogent Modular Architecture options */
  42 #define CONFIG_CMA286_60_OLD    1       /* ...on an old CMA286-60 CPU module */
  43 #define CONFIG_CMA102           1       /* ...on a CMA102 motherboard   */
  44 #define CONFIG_CMA302           1       /* ...with a CMA302 flash I/O module */
  45
  46 /* serial console configuration */
  47 #undef  CONFIG_8xx_CONS_SMC1
  48 #undef  CONFIG_8xx_CONS_SMC2
  49 #define CONFIG_8xx_CONS_NONE    /* not on 8xx serial ports (eg on cogent m/b) */
  50
  51 #if defined(CONFIG_CMA286_60_OLD)
  52 #define CONFIG_8xx_GCLK_FREQ    33333000 /* define if cant use get_gclk_freq */
  53 #endif
  54
  55 #define CONFIG_BAUDRATE         230400
  56
  57 #define CONFIG_HARD_I2C         /* I2C with hardware support */
  58 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
  59 #define CFG_I2C_SLAVE           0x7F
  60
  61
  62 #define CONFIG_COMMANDS         ((CONFIG_CMD_DFL | CFG_CMD_KGDB | CFG_CMD_I2C) & ~CFG_CMD_NET)
  63
  64 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  65 #include <cmd_confdefs.h>
  66
  67 #if 0
  68 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  69 #else
  70 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  71 #endif
  72 #define CONFIG_BOOTCOMMAND      "bootm 04080000 04200000" /* autoboot command*/
  73
  74 #define CONFIG_BOOTARGS         "root=/dev/ram rw"
  75
  76 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  77 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
  78 #undef  CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
  79 #define CONFIG_KGDB_NONE                /* define if kgdb on something else */
  80 #define CONFIG_KGDB_INDEX       2       /* which SMC/SCC channel for kgdb */
  81 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
  82 #endif
  83
  84 #define CONFIG_WATCHDOG                 /* turn on platform specific watchdog */
  85
  86 /*
  87  * Miscellaneous configurable options
  88  */
  89 #define CFG_LONGHELP                    /* undef to save memory         */
  90 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
  91 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  92 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
  93 #else
  94 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
  95 #endif
  96 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  97 #define CFG_MAXARGS     16              /* max number of command args   */
  98 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
  99
 100 #define CFG_MEMTEST_START       0x00400000      /* memtest works on     */
 101 #define CFG_MEMTEST_END         0x01c00000      /* 4 ... 28 MB in DRAM  */
 102
 103 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 104
 105 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 106
 107 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 108
 109 #define CFG_ALLOC_DPRAM
 110
 111 /*
 112  * Low Level Configuration Settings
 113  * (address mappings, register initial values, etc.)
 114  * You should know what you are doing if you make changes here.
 115  */
 116
 117 /*-----------------------------------------------------------------------
 118  * Low Level Cogent settings
 119  * if CFG_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not.
 120  * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
 121  * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
 122  * (second 2 for CMA120 only)
 123  */
 124 #define CFG_CMA_MB_BASE         0x00000000      /* base of m/b address space */
 125
 126 #include <configs/cogent_common.h>
 127
 128 #define CFG_CMA_CONS_SERIAL     /* use Cogent motherboard serial for console */
 129 #define CONFIG_CONS_INDEX       1
 130 #define CFG_CMA_LCD_HEARTBEAT   /* define for sec rotator in lcd corner */
 131 #define CONFIG_SHOW_ACTIVITY
 132 #if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
 133 /*
 134  * flash exists on the motherboard
 135  * set these four according to TOP dipsw:
 136  * TOP on  => ..._FLLOW_...     (boot EPROM space is high so FLASH is low )
 137  * TOP off => ..._FLHIGH_...    (boot EPROM space is low  so FLASH is high)
 138  */
 139 #define CMA_MB_FLASH_EXEC_BASE  CMA_MB_FLLOW_EXEC_BASE
 140 #define CMA_MB_FLASH_EXEC_SIZE  CMA_MB_FLLOW_EXEC_SIZE
 141 #define CMA_MB_FLASH_RDWR_BASE  CMA_MB_FLLOW_RDWR_BASE
 142 #define CMA_MB_FLASH_RDWR_SIZE  CMA_MB_FLLOW_RDWR_SIZE
 143 #endif
 144 #define CMA_MB_FLASH_BASE       CMA_MB_FLASH_EXEC_BASE
 145 #define CMA_MB_FLASH_SIZE       CMA_MB_FLASH_EXEC_SIZE
 146
 147 /*-----------------------------------------------------------------------
 148  * Internal Memory Mapped Register
 149  */
 150 #define CFG_IMMR                0xFF000000
 151
 152 /*-----------------------------------------------------------------------
 153  * Definitions for initial stack pointer and data area (in DPRAM)
 154  */
 155 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 156 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 157 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 158 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 159 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 160
 161 /*-----------------------------------------------------------------------
 162  * Start addresses for the final memory configuration
 163  * (Set up by the startup code)
 164  * Please note that CFG_SDRAM_BASE _must_ start at 0
 165  */
 166 #define CFG_SDRAM_BASE          CMA_MB_RAM_BASE
 167 #ifdef CONFIG_CMA302
 168 #define CFG_FLASH_BASE          CMA_MB_SLOT2_BASE       /* cma302 in slot 2 */
 169 #else
 170 #define CFG_FLASH_BASE          CMA_MB_FLASH_BASE       /* flash on m/b */
 171 #endif
 172 #define CFG_MONITOR_BASE        TEXT_BASE
 173 #define CFG_MONITOR_LEN         (128 << 10)     /* Reserve 128 kB for Monitor   */
 174 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 175
 176 /*
 177  * For booting Linux, the board info and command line data
 178  * have to be in the first 8 MB of memory, since this is
 179  * the maximum mapped by the Linux kernel during initialization.
 180  */
 181 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 182 /*-----------------------------------------------------------------------
 183  * FLASH organization
 184  */
 185 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 186 #define CFG_MAX_FLASH_SECT      67      /* max number of sectors on one chip    */
 187
 188 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 189 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 190
 191 #define CFG_ENV_IS_IN_FLASH     1
 192 #define CFG_ENV_ADDR            CFG_FLASH_BASE /* Addr of Environment Sector */
 193 #ifdef CONFIG_CMA302
 194 #define CFG_ENV_SIZE            0x1000  /* Total Size of Environment Sector     */
 195 #define CFG_ENV_SECT_SIZE       (512*1024) /* see README - env sect real size */
 196 #else
 197 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 198 #endif
 199 /*-----------------------------------------------------------------------
 200  * Cache Configuration
 201  */
 202 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 203 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 204 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 205 #endif
 206
 207
 208 /*-----------------------------------------------------------------------
 209  * SYPCR - System Protection Control                            11-9
 210  * SYPCR can only be written once after reset!
 211  *-----------------------------------------------------------------------
 212  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 213  */
 214 #if defined(CONFIG_WATCHDOG)
 215 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 216                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 217 #else
 218 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 219 #endif  /* CONFIG_WATCHDOG */
 220
 221 /*-----------------------------------------------------------------------
 222  * SIUMCR - SIU Module Configuration                            11-6
 223  *-----------------------------------------------------------------------
 224  * PCMCIA config., multi-function pin tri-state
 225  */
 226 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 227
 228 /*-----------------------------------------------------------------------
 229  * TBSCR - Time Base Status and Control                         11-26
 230  *-----------------------------------------------------------------------
 231  * Clear Reference Interrupt Status, Timebase freezing enabled
 232  */
 233 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 234
 235 /*-----------------------------------------------------------------------
 236  * PISCR - Periodic Interrupt Status and Control                11-31
 237  *-----------------------------------------------------------------------
 238  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 239  */
 240 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 241
 242 /*-----------------------------------------------------------------------
 243  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 244  *-----------------------------------------------------------------------
 245  * Reset PLL lock status sticky bit, timer expired status bit and timer
 246  * interrupt status bit - leave PLL multiplication factor unchanged !
 247  */
 248 #define CFG_PLPRCR      (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 249
 250 /*-----------------------------------------------------------------------
 251  * SCCR - System Clock and reset Control Register               15-27
 252  *-----------------------------------------------------------------------
 253  * Set clock output, timebase and RTC source and divider,
 254  * power management and some other internal clocks
 255  */
 256 #define SCCR_MASK       SCCR_EBDF11
 257 #define CFG_SCCR        (SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
 258                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 259                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 260                          SCCR_DFALCD00)
 261
 262 /*-----------------------------------------------------------------------
 263  * PCMCIA stuff
 264  *-----------------------------------------------------------------------
 265  *
 266  */
 267 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 268 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 269 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 270 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 271 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 272 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 273 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 274 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 275
 276 /*-----------------------------------------------------------------------
 277  *
 278  *-----------------------------------------------------------------------
 279  *
 280  */
 281 /*#define       CFG_DER 0x2002000F*/
 282 #define CFG_DER 0
 283
 284 #if defined(CONFIG_CMA286_60_OLD)
 285
 286 /*
 287  * Init Memory Controller:
 288  *
 289  * NOTE: although the names (CFG_xRn_PRELIM) suggest preliminary settings,
 290  * they are actually the final settings for this cpu/board, because the
 291  * flash and RAM are on the motherboard, accessed via the CMAbus, and the
 292  * mappings are pretty much fixed.
 293  *
 294  * (the *_SIZE vars must be a power of 2)
 295  */
 296
 297 #define CFG_CMA_CS0_BASE        TEXT_BASE               /* EPROM */
 298 #define CFG_CMA_CS0_SIZE        (1 << 20)
 299 #define CFG_CMA_CS1_BASE        CMA_MB_RAM_BASE         /* RAM + I/O SLOT 1 */
 300 #define CFG_CMA_CS1_SIZE        (64 << 20)
 301 #define CFG_CMA_CS2_BASE        CMA_MB_SLOT2_BASE       /* I/O SLOTS 2 + 3 */
 302 #define CFG_CMA_CS2_SIZE        (64 << 20)
 303 #define CFG_CMA_CS3_BASE        CMA_MB_ROMLOW_BASE      /* M/B I/O */
 304 #define CFG_CMA_CS3_SIZE        (32 << 20)
 305
 306 /*
 307  * CS0 maps the EPROM on the cpu module
 308  * Set it for 4 wait states, address CFG_MONITOR_BASE and size 1M
 309  *
 310  * Note: We must have already transferred control to the final location
 311  * of the EPROM before these are used, because when BR0/OR0 are set, the
 312  * mirror of the eprom at any other addresses will disappear.
 313  */
 314
 315 /* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */
 316 #define CFG_BR0_PRELIM  ((CFG_CMA_CS0_BASE&BR_BA_MSK)|BR_PS_16|BR_WP|BR_V)
 317 /* mask size CFG_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */
 318 #define CFG_OR0_PRELIM  ((~(CFG_CMA_CS0_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SCY_4_CLK)
 319
 320 /*
 321  * CS1 maps motherboard DRAM and motherboard I/O slot 1
 322  * (each 32Mbyte in size)
 323  */
 324
 325 /* base address = CFG_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */
 326 #define CFG_BR1_PRELIM  ((CFG_CMA_CS1_BASE&BR_BA_MSK)|BR_V)
 327 /* mask size CFG_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */
 328 #define CFG_OR1_PRELIM  ((~(CFG_CMA_CS1_SIZE-1)&OR_AM_MSK)|OR_SETA)
 329
 330 /*
 331  * CS2 maps motherboard I/O slots 2 and 3
 332  * (each 32Mbyte in size)
 333  */
 334
 335 /* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */
 336 #define CFG_BR2_PRELIM  ((CFG_CMA_CS2_BASE&BR_BA_MSK)|BR_V)
 337 /* mask size CFG_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */
 338 #define CFG_OR2_PRELIM  ((~(CFG_CMA_CS2_SIZE-1)&OR_AM_MSK)|OR_SETA)
 339
 340 /*
 341  * CS3 maps motherboard I/O
 342  * (32Mbyte in size)
 343  */
 344
 345 /* base address = CFG_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */
 346 #define CFG_BR3_PRELIM  ((CFG_CMA_CS3_BASE&BR_BA_MSK)|BR_V)
 347 /* mask size CFG_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */
 348 #define CFG_OR3_PRELIM  ((~(CFG_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA)
 349
 350 #endif
 351
 352 /*
 353  * Internal Definitions
 354  *
 355  * Boot Flags
 356  */
 357 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 358 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 359
 360 #endif  /* __CONFIG_H */