include/configs/corenet_ds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2009-2012 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * Corenet DS style board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include "../board/freescale/common/ics307_clk.h"
  14
  15 #ifdef CONFIG_RAMBOOT_PBL
  16 #ifdef CONFIG_NXP_ESBC
  17 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  18 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  19 #ifdef CONFIG_MTD_RAW_NAND
  20 #define CONFIG_RAMBOOT_NAND
  21 #endif
  22 #define CONFIG_BOOTSCRIPT_COPY_RAM
  23 #else
  24 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  25 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  26 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  27 #if defined(CONFIG_TARGET_P3041DS)
  28 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
  29 #elif defined(CONFIG_TARGET_P4080DS)
  30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
  31 #elif defined(CONFIG_TARGET_P5020DS)
  32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
  33 #elif defined(CONFIG_TARGET_P5040DS)
  34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
  35 #endif
  36 #endif
  37 #endif
  38
  39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  40 /* Set 1M boot space */
  41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  43                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  45 #endif
  46
  47 /* High Level Configuration Options */
  48 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  49
  50 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  51 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  52 #endif
  53
  54 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  55 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  56 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  57 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  58 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  59
  60 #define CONFIG_ENV_OVERWRITE
  61
  62 #if defined(CONFIG_SPIFLASH)
  63 #elif defined(CONFIG_SDCARD)
  64 #define CONFIG_FSL_FIXED_MMC_LOCATION
  65 #define CONFIG_SYS_MMC_ENV_DEV          0
  66 #endif
  67
  68 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
  69
  70 /*
  71  * These can be toggled for performance analysis, otherwise use default.
  72  */
  73 #define CONFIG_SYS_CACHE_STASHING
  74 #define CONFIG_BACKSIDE_L2_CACHE
  75 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  76 #define CONFIG_BTB                      /* toggle branch predition */
  77 #define CONFIG_DDR_ECC
  78 #ifdef CONFIG_DDR_ECC
  79 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  80 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  81 #endif
  82
  83 #define CONFIG_ENABLE_36BIT_PHYS
  84
  85 #ifdef CONFIG_PHYS_64BIT
  86 #define CONFIG_ADDR_MAP
  87 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
  88 #endif
  89
  90 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  91
  92 /*
  93  *  Config the L3 Cache as L3 SRAM
  94  */
  95 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  96 #ifdef CONFIG_PHYS_64BIT
  97 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
  98 #else
  99 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 100 #endif
 101 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 102 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 103
 104 #ifdef CONFIG_PHYS_64BIT
 105 #define CONFIG_SYS_DCSRBAR              0xf0000000
 106 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 107 #endif
 108
 109 /* EEPROM */
 110 #define CONFIG_ID_EEPROM
 111 #define CONFIG_SYS_I2C_EEPROM_NXID
 112 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 113 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 114 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 115
 116 /*
 117  * DDR Setup
 118  */
 119 #define CONFIG_VERY_BIG_RAM
 120 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 121 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 122
 123 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 124 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 125
 126 #define CONFIG_DDR_SPD
 127
 128 #define CONFIG_SYS_SPD_BUS_NUM  1
 129 #define SPD_EEPROM_ADDRESS1     0x51
 130 #define SPD_EEPROM_ADDRESS2     0x52
 131 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 132 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 133
 134 /*
 135  * Local Bus Definitions
 136  */
 137
 138 /* Set the local bus clock 1/8 of platform clock */
 139 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 140
 141 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* Start of PromJet */
 142 #ifdef CONFIG_PHYS_64BIT
 143 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 144 #else
 145 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 146 #endif
 147
 148 #define CONFIG_SYS_FLASH_BR_PRELIM \
 149                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
 150                  | BR_PS_16 | BR_V)
 151 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 152                                         | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 153
 154 #define CONFIG_SYS_BR1_PRELIM \
 155         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 156 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 157
 158 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 159 #ifdef CONFIG_PHYS_64BIT
 160 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 161 #else
 162 #define PIXIS_BASE_PHYS         PIXIS_BASE
 163 #endif
 164
 165 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 166 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 167
 168 #define PIXIS_LBMAP_SWITCH      7
 169 #define PIXIS_LBMAP_MASK        0xf0
 170 #define PIXIS_LBMAP_SHIFT       4
 171 #define PIXIS_LBMAP_ALTBANK     0x40
 172
 173 #define CONFIG_SYS_FLASH_QUIET_TEST
 174 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 175
 176 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 177 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 178 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 179 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 180
 181 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 182
 183 #if defined(CONFIG_RAMBOOT_PBL)
 184 #define CONFIG_SYS_RAMBOOT
 185 #endif
 186
 187 /* Nand Flash */
 188 #ifdef CONFIG_NAND_FSL_ELBC
 189 #define CONFIG_SYS_NAND_BASE            0xffa00000
 190 #ifdef CONFIG_PHYS_64BIT
 191 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 192 #else
 193 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 194 #endif
 195
 196 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 197 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 198 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 199
 200 /* NAND flash config */
 201 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 202                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 203                                | BR_PS_8               /* Port Size = 8 bit */ \
 204                                | BR_MS_FCM             /* MSEL = FCM */ \
 205                                | BR_V)                 /* valid */
 206 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 207                                | OR_FCM_PGS            /* Large Page*/ \
 208                                | OR_FCM_CSCT \
 209                                | OR_FCM_CST \
 210                                | OR_FCM_CHT \
 211                                | OR_FCM_SCY_1 \
 212                                | OR_FCM_TRLX \
 213                                | OR_FCM_EHTR)
 214
 215 #ifdef CONFIG_MTD_RAW_NAND
 216 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 217 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 218 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 219 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 220 #else
 221 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 222 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 223 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 224 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 225 #endif
 226 #else
 227 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 228 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 229 #endif /* CONFIG_NAND_FSL_ELBC */
 230
 231 #define CONFIG_SYS_FLASH_EMPTY_INFO
 232 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 233 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 234
 235 #define CONFIG_HWCONFIG
 236
 237 /* define to use L1 as initial stack */
 238 #define CONFIG_L1_INIT_RAM
 239 #define CONFIG_SYS_INIT_RAM_LOCK
 240 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 241 #ifdef CONFIG_PHYS_64BIT
 242 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 243 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 244 /* The assembler doesn't like typecast */
 245 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 246         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 247           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 248 #else
 249 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 250 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 251 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 252 #endif
 253 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 254
 255 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 256 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 257
 258 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 259 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 260
 261 /* Serial Port - controlled on board with jumper J8
 262  * open - index 2
 263  * shorted - index 1
 264  */
 265 #define CONFIG_SYS_NS16550_SERIAL
 266 #define CONFIG_SYS_NS16550_REG_SIZE     1
 267 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 268
 269 #define CONFIG_SYS_BAUDRATE_TABLE       \
 270         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 271
 272 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 273 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 274 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 275 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 276
 277 /* I2C */
 278 #ifndef CONFIG_DM_I2C
 279 #define CONFIG_SYS_I2C
 280 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 281 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 282 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 283 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 284 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 285 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 286 #else
 287 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 288 #define CONFIG_I2C_DEFAULT_BUS_NUMBER   0
 289 #endif
 290 #define CONFIG_SYS_I2C_FSL
 291
 292 /*
 293  * RapidIO
 294  */
 295 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 296 #ifdef CONFIG_PHYS_64BIT
 297 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 298 #else
 299 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 300 #endif
 301 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 302
 303 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 304 #ifdef CONFIG_PHYS_64BIT
 305 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 306 #else
 307 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 308 #endif
 309 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 310
 311 /*
 312  * for slave u-boot IMAGE instored in master memory space,
 313  * PHYS must be aligned based on the SIZE
 314  */
 315 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 316 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 317 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 318 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 319 /*
 320  * for slave UCODE and ENV instored in master memory space,
 321  * PHYS must be aligned based on the SIZE
 322  */
 323 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 324 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 325 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 326
 327 /* slave core release by master*/
 328 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 329 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 330
 331 /*
 332  * SRIO_PCIE_BOOT - SLAVE
 333  */
 334 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 335 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 336 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 337                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 338 #endif
 339
 340 /*
 341  * eSPI - Enhanced SPI
 342  */
 343
 344 /*
 345  * General PCI
 346  * Memory space is mapped 1-1, but I/O space must start from 0.
 347  */
 348
 349 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 350 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 351 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 352 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 353 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 354
 355 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 356 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 357 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 358 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 359 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 360
 361 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 362 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 363 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 364 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 365 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 366
 367 /* controller 4, Base address 203000 */
 368 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 369 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 370
 371 /* Qman/Bman */
 372 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 373 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 374 #ifdef CONFIG_PHYS_64BIT
 375 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 376 #else
 377 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 378 #endif
 379 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 380 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 381 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 382 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 383 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 384 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 385                                         CONFIG_SYS_BMAN_CENA_SIZE)
 386 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 387 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 388 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 389 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 390 #ifdef CONFIG_PHYS_64BIT
 391 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 392 #else
 393 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 394 #endif
 395 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 396 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 397 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 398 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 399 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 400 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 401                                         CONFIG_SYS_QMAN_CENA_SIZE)
 402 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 403 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 404
 405 #define CONFIG_SYS_DPAA_FMAN
 406 #define CONFIG_SYS_DPAA_PME
 407 /* Default address of microcode for the Linux Fman driver */
 408 #if defined(CONFIG_SPIFLASH)
 409 /*
 410  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 411  * env, so we got 0x110000.
 412  */
 413 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 414 #elif defined(CONFIG_SDCARD)
 415 /*
 416  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 417  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 418  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 419  */
 420 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 421 #elif defined(CONFIG_MTD_RAW_NAND)
 422 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 423 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 424 /*
 425  * Slave has no ucode locally, it can fetch this from remote. When implementing
 426  * in two corenet boards, slave's ucode could be stored in master's memory
 427  * space, the address can be mapped from slave TLB->slave LAW->
 428  * slave SRIO or PCIE outbound window->master inbound window->
 429  * master LAW->the ucode address in master's memory space.
 430  */
 431 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 432 #else
 433 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 434 #endif
 435 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 436 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 437
 438 #ifdef CONFIG_PCI
 439 #if !defined(CONFIG_DM_PCI)
 440 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 441 #define CONFIG_PCI_INDIRECT_BRIDGE
 442 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 443 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 444 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 445 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 446 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 447 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 448 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 449 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 450 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 451 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 452 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 453 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 454 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 455 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 456 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 457 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 458 #endif
 459
 460 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 461 #endif  /* CONFIG_PCI */
 462
 463 /* SATA */
 464 #ifdef CONFIG_FSL_SATA_V2
 465 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 466 #define CONFIG_SATA1
 467 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 468 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 469 #define CONFIG_SATA2
 470 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 471 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 472
 473 #define CONFIG_LBA48
 474 #endif
 475
 476 #ifdef CONFIG_FMAN_ENET
 477 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1c
 478 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x1d
 479 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x1e
 480 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1f
 481 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  4
 482
 483 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR  0x1c
 484 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR  0x1d
 485 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR  0x1e
 486 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR  0x1f
 487 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR  0
 488
 489 #define CONFIG_SYS_TBIPA_VALUE  8
 490 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 491 #endif
 492
 493 /*
 494  * Environment
 495  */
 496 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 497 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 498
 499 /*
 500 * USB
 501 */
 502 #define CONFIG_HAS_FSL_DR_USB
 503 #define CONFIG_HAS_FSL_MPH_USB
 504
 505 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 506 #define CONFIG_USB_EHCI_FSL
 507 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 508 #endif
 509
 510 #ifdef CONFIG_MMC
 511 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 512 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 513 #endif
 514
 515 /*
 516  * Miscellaneous configurable options
 517  */
 518 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 519
 520 /*
 521  * For booting Linux, the board info and command line data
 522  * have to be in the first 64 MB of memory, since this is
 523  * the maximum mapped by the Linux kernel during initialization.
 524  */
 525 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 526 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 527
 528 #ifdef CONFIG_CMD_KGDB
 529 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 530 #endif
 531
 532 /*
 533  * Environment Configuration
 534  */
 535 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 536 #define CONFIG_BOOTFILE         "uImage"
 537 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 538
 539 /* default location for tftp and bootm */
 540 #define CONFIG_LOADADDR         1000000
 541
 542 #ifdef CONFIG_TARGET_P4080DS
 543 #define __USB_PHY_TYPE  ulpi
 544 #else
 545 #define __USB_PHY_TYPE  utmi
 546 #endif
 547
 548 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 549         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 550         "bank_intlv=cs0_cs1;"                                   \
 551         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 552         "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 553         "netdev=eth0\0"                                         \
 554         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 555         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 556         "tftpflash=tftpboot $loadaddr $uboot && "               \
 557         "protect off $ubootaddr +$filesize && "                 \
 558         "erase $ubootaddr +$filesize && "                       \
 559         "cp.b $loadaddr $ubootaddr $filesize && "               \
 560         "protect on $ubootaddr +$filesize && "                  \
 561         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 562         "consoledev=ttyS0\0"                                    \
 563         "ramdiskaddr=2000000\0"                                 \
 564         "ramdiskfile=p4080ds/ramdisk.uboot\0"                   \
 565         "fdtaddr=1e00000\0"                                     \
 566         "fdtfile=p4080ds/p4080ds.dtb\0"                         \
 567         "bdev=sda3\0"
 568
 569 #define CONFIG_HDBOOT                                   \
 570         "setenv bootargs root=/dev/$bdev rw "           \
 571         "console=$consoledev,$baudrate $othbootargs;"   \
 572         "tftp $loadaddr $bootfile;"                     \
 573         "tftp $fdtaddr $fdtfile;"                       \
 574         "bootm $loadaddr - $fdtaddr"
 575
 576 #define CONFIG_NFSBOOTCOMMAND                   \
 577         "setenv bootargs root=/dev/nfs rw "     \
 578         "nfsroot=$serverip:$rootpath "          \
 579         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 580         "console=$consoledev,$baudrate $othbootargs;"   \
 581         "tftp $loadaddr $bootfile;"             \
 582         "tftp $fdtaddr $fdtfile;"               \
 583         "bootm $loadaddr - $fdtaddr"
 584
 585 #define CONFIG_RAMBOOTCOMMAND                           \
 586         "setenv bootargs root=/dev/ram rw "             \
 587         "console=$consoledev,$baudrate $othbootargs;"   \
 588         "tftp $ramdiskaddr $ramdiskfile;"               \
 589         "tftp $loadaddr $bootfile;"                     \
 590         "tftp $fdtaddr $fdtfile;"                       \
 591         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 592
 593 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 594
 595 #include <asm/fsl_secure_boot.h>
 596
 597 #endif  /* __CONFIG_H */