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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/corenet_ds.h
2 * Copyright 2009-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * Corenet DS style board configuration file
13 #include "../board/freescale/common/ics307_clk.h"
15 #ifdef CONFIG_RAMBOOT_PBL
16 #ifdef CONFIG_SECURE_BOOT
17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
20 #define CONFIG_RAMBOOT_NAND
22 #define CONFIG_BOOTSCRIPT_COPY_RAM
24 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
26 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
27 #if defined(CONFIG_TARGET_P3041DS)
28 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
29 #elif defined(CONFIG_TARGET_P4080DS)
30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
31 #elif defined(CONFIG_TARGET_P5020DS)
32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
33 #elif defined(CONFIG_TARGET_P5040DS)
34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
40 /* Set 1M boot space */
41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
47 /* High Level Configuration Options */
48 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
49 #define CONFIG_MP /* support multiple processors */
51 #ifndef CONFIG_RESET_VECTOR_ADDRESS
52 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
55 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
56 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
57 #define CONFIG_PCIE1 /* PCIE controller 1 */
58 #define CONFIG_PCIE2 /* PCIE controller 2 */
59 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
60 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
62 #define CONFIG_ENV_OVERWRITE
64 #ifndef CONFIG_MTD_NOR_FLASH
66 #define CONFIG_FLASH_CFI_DRIVER
67 #define CONFIG_SYS_FLASH_CFI
68 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
71 #if defined(CONFIG_SPIFLASH)
72 #define CONFIG_SYS_EXTRA_ENV_RELOC
73 #define CONFIG_ENV_SPI_BUS 0
74 #define CONFIG_ENV_SPI_CS 0
75 #define CONFIG_ENV_SPI_MAX_HZ 10000000
76 #define CONFIG_ENV_SPI_MODE 0
77 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
78 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
79 #define CONFIG_ENV_SECT_SIZE 0x10000
80 #elif defined(CONFIG_SDCARD)
81 #define CONFIG_SYS_EXTRA_ENV_RELOC
82 #define CONFIG_FSL_FIXED_MMC_LOCATION
83 #define CONFIG_SYS_MMC_ENV_DEV 0
84 #define CONFIG_ENV_SIZE 0x2000
85 #define CONFIG_ENV_OFFSET (512 * 1658)
86 #elif defined(CONFIG_NAND)
87 #define CONFIG_SYS_EXTRA_ENV_RELOC
88 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
89 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
90 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
91 #define CONFIG_ENV_ADDR 0xffe20000
92 #define CONFIG_ENV_SIZE 0x2000
93 #elif defined(CONFIG_ENV_IS_NOWHERE)
94 #define CONFIG_ENV_SIZE 0x2000
96 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
97 #define CONFIG_ENV_SIZE 0x2000
98 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
101 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
104 * These can be toggled for performance analysis, otherwise use default.
106 #define CONFIG_SYS_CACHE_STASHING
107 #define CONFIG_BACKSIDE_L2_CACHE
108 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
109 #define CONFIG_BTB /* toggle branch predition */
110 #define CONFIG_DDR_ECC
111 #ifdef CONFIG_DDR_ECC
112 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
113 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
116 #define CONFIG_ENABLE_36BIT_PHYS
118 #ifdef CONFIG_PHYS_64BIT
119 #define CONFIG_ADDR_MAP
120 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
123 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
124 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
125 #define CONFIG_SYS_MEMTEST_END 0x00400000
126 #define CONFIG_SYS_ALT_MEMTEST
129 * Config the L3 Cache as L3 SRAM
131 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
132 #ifdef CONFIG_PHYS_64BIT
133 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
135 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
137 #define CONFIG_SYS_L3_SIZE (1024 << 10)
138 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
140 #ifdef CONFIG_PHYS_64BIT
141 #define CONFIG_SYS_DCSRBAR 0xf0000000
142 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
146 #define CONFIG_ID_EEPROM
147 #define CONFIG_SYS_I2C_EEPROM_NXID
148 #define CONFIG_SYS_EEPROM_BUS_NUM 0
149 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
150 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
155 #define CONFIG_VERY_BIG_RAM
156 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
157 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
159 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
160 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
162 #define CONFIG_DDR_SPD
164 #define CONFIG_SYS_SPD_BUS_NUM 1
165 #define SPD_EEPROM_ADDRESS1 0x51
166 #define SPD_EEPROM_ADDRESS2 0x52
167 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
168 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
171 * Local Bus Definitions
174 /* Set the local bus clock 1/8 of platform clock */
175 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
177 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
178 #ifdef CONFIG_PHYS_64BIT
179 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
181 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
184 #define CONFIG_SYS_FLASH_BR_PRELIM \
185 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
187 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
188 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
190 #define CONFIG_SYS_BR1_PRELIM \
191 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
192 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
194 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
195 #ifdef CONFIG_PHYS_64BIT
196 #define PIXIS_BASE_PHYS 0xfffdf0000ull
198 #define PIXIS_BASE_PHYS PIXIS_BASE
201 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
202 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
204 #define PIXIS_LBMAP_SWITCH 7
205 #define PIXIS_LBMAP_MASK 0xf0
206 #define PIXIS_LBMAP_SHIFT 4
207 #define PIXIS_LBMAP_ALTBANK 0x40
209 #define CONFIG_SYS_FLASH_QUIET_TEST
210 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
212 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
213 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
214 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
215 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
217 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
219 #if defined(CONFIG_RAMBOOT_PBL)
220 #define CONFIG_SYS_RAMBOOT
224 #ifdef CONFIG_NAND_FSL_ELBC
225 #define CONFIG_SYS_NAND_BASE 0xffa00000
226 #ifdef CONFIG_PHYS_64BIT
227 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
229 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
232 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
233 #define CONFIG_SYS_MAX_NAND_DEVICE 1
234 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
236 /* NAND flash config */
237 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
238 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
239 | BR_PS_8 /* Port Size = 8 bit */ \
240 | BR_MS_FCM /* MSEL = FCM */ \
242 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
243 | OR_FCM_PGS /* Large Page*/ \
252 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
253 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
254 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
255 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
257 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
258 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
259 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
260 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
263 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
264 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
265 #endif /* CONFIG_NAND_FSL_ELBC */
267 #define CONFIG_SYS_FLASH_EMPTY_INFO
268 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
269 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
271 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
272 #define CONFIG_MISC_INIT_R
274 #define CONFIG_HWCONFIG
276 /* define to use L1 as initial stack */
277 #define CONFIG_L1_INIT_RAM
278 #define CONFIG_SYS_INIT_RAM_LOCK
279 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
280 #ifdef CONFIG_PHYS_64BIT
281 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
282 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
283 /* The assembler doesn't like typecast */
284 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
285 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
286 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
288 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
289 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
290 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
292 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
294 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
295 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
297 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
298 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
300 /* Serial Port - controlled on board with jumper J8
304 #define CONFIG_CONS_INDEX 1
305 #define CONFIG_SYS_NS16550_SERIAL
306 #define CONFIG_SYS_NS16550_REG_SIZE 1
307 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
309 #define CONFIG_SYS_BAUDRATE_TABLE \
310 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
312 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
313 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
314 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
315 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
318 #define CONFIG_SYS_I2C
319 #define CONFIG_SYS_I2C_FSL
320 #define CONFIG_SYS_FSL_I2C_SPEED 400000
321 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
322 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
323 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
324 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
325 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
330 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
331 #ifdef CONFIG_PHYS_64BIT
332 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
334 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
336 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
338 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
339 #ifdef CONFIG_PHYS_64BIT
340 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
342 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
344 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
347 * for slave u-boot IMAGE instored in master memory space,
348 * PHYS must be aligned based on the SIZE
350 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
351 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
352 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
353 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
355 * for slave UCODE and ENV instored in master memory space,
356 * PHYS must be aligned based on the SIZE
358 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
359 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
360 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
362 /* slave core release by master*/
363 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
364 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
367 * SRIO_PCIE_BOOT - SLAVE
369 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
370 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
371 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
372 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
376 * eSPI - Enhanced SPI
378 #define CONFIG_SF_DEFAULT_SPEED 10000000
379 #define CONFIG_SF_DEFAULT_MODE 0
383 * Memory space is mapped 1-1, but I/O space must start from 0.
386 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
387 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
388 #ifdef CONFIG_PHYS_64BIT
389 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
390 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
392 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
393 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
395 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
396 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
397 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
398 #ifdef CONFIG_PHYS_64BIT
399 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
401 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
403 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
405 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
406 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
407 #ifdef CONFIG_PHYS_64BIT
408 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
409 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
411 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
412 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
414 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
415 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
416 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
417 #ifdef CONFIG_PHYS_64BIT
418 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
420 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
422 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
424 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
425 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
426 #ifdef CONFIG_PHYS_64BIT
427 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
428 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
430 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
431 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
433 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
434 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
435 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
436 #ifdef CONFIG_PHYS_64BIT
437 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
439 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
441 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
443 /* controller 4, Base address 203000 */
444 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
445 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
446 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
447 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
448 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
449 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
452 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
453 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
454 #ifdef CONFIG_PHYS_64BIT
455 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
457 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
459 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
460 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
461 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
462 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
463 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
464 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
465 CONFIG_SYS_BMAN_CENA_SIZE)
466 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
467 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
468 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
469 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
470 #ifdef CONFIG_PHYS_64BIT
471 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
473 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
475 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
476 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
477 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
478 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
479 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
480 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
481 CONFIG_SYS_QMAN_CENA_SIZE)
482 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
483 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
485 #define CONFIG_SYS_DPAA_FMAN
486 #define CONFIG_SYS_DPAA_PME
487 /* Default address of microcode for the Linux Fman driver */
488 #if defined(CONFIG_SPIFLASH)
490 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
491 * env, so we got 0x110000.
493 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
494 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
495 #elif defined(CONFIG_SDCARD)
497 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
498 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
499 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
501 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
502 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
503 #elif defined(CONFIG_NAND)
504 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
505 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
506 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
508 * Slave has no ucode locally, it can fetch this from remote. When implementing
509 * in two corenet boards, slave's ucode could be stored in master's memory
510 * space, the address can be mapped from slave TLB->slave LAW->
511 * slave SRIO or PCIE outbound window->master inbound window->
512 * master LAW->the ucode address in master's memory space.
514 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
515 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
517 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
518 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
520 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
521 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
523 #ifdef CONFIG_SYS_DPAA_FMAN
524 #define CONFIG_FMAN_ENET
525 #define CONFIG_PHYLIB_10G
526 #define CONFIG_PHY_VITESSE
527 #define CONFIG_PHY_TERANETICS
531 #define CONFIG_PCI_INDIRECT_BRIDGE
533 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
534 #endif /* CONFIG_PCI */
537 #ifdef CONFIG_FSL_SATA_V2
538 #define CONFIG_SYS_SATA_MAX_DEVICE 2
540 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
541 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
543 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
544 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
549 #ifdef CONFIG_FMAN_ENET
550 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
551 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
552 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
553 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
554 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
556 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
557 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
558 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
559 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
560 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
562 #define CONFIG_SYS_TBIPA_VALUE 8
563 #define CONFIG_MII /* MII PHY management */
564 #define CONFIG_ETHPRIME "FM1@DTSEC1"
570 #define CONFIG_LOADS_ECHO /* echo on for serial download */
571 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
576 #define CONFIG_HAS_FSL_DR_USB
577 #define CONFIG_HAS_FSL_MPH_USB
579 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
580 #define CONFIG_USB_EHCI_FSL
581 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
585 #define CONFIG_FSL_ESDHC
586 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
587 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
591 * Miscellaneous configurable options
593 #define CONFIG_SYS_LONGHELP /* undef to save memory */
594 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
595 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
596 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
599 * For booting Linux, the board info and command line data
600 * have to be in the first 64 MB of memory, since this is
601 * the maximum mapped by the Linux kernel during initialization.
603 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
604 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
606 #ifdef CONFIG_CMD_KGDB
607 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
611 * Environment Configuration
613 #define CONFIG_ROOTPATH "/opt/nfsroot"
614 #define CONFIG_BOOTFILE "uImage"
615 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
617 /* default location for tftp and bootm */
618 #define CONFIG_LOADADDR 1000000
620 #ifdef CONFIG_TARGET_P4080DS
621 #define __USB_PHY_TYPE ulpi
623 #define __USB_PHY_TYPE utmi
626 #define CONFIG_EXTRA_ENV_SETTINGS \
627 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
628 "bank_intlv=cs0_cs1;" \
629 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
630 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
632 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
633 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
634 "tftpflash=tftpboot $loadaddr $uboot && " \
635 "protect off $ubootaddr +$filesize && " \
636 "erase $ubootaddr +$filesize && " \
637 "cp.b $loadaddr $ubootaddr $filesize && " \
638 "protect on $ubootaddr +$filesize && " \
639 "cmp.b $loadaddr $ubootaddr $filesize\0" \
640 "consoledev=ttyS0\0" \
641 "ramdiskaddr=2000000\0" \
642 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
643 "fdtaddr=1e00000\0" \
644 "fdtfile=p4080ds/p4080ds.dtb\0" \
647 #define CONFIG_HDBOOT \
648 "setenv bootargs root=/dev/$bdev rw " \
649 "console=$consoledev,$baudrate $othbootargs;" \
650 "tftp $loadaddr $bootfile;" \
651 "tftp $fdtaddr $fdtfile;" \
652 "bootm $loadaddr - $fdtaddr"
654 #define CONFIG_NFSBOOTCOMMAND \
655 "setenv bootargs root=/dev/nfs rw " \
656 "nfsroot=$serverip:$rootpath " \
657 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
658 "console=$consoledev,$baudrate $othbootargs;" \
659 "tftp $loadaddr $bootfile;" \
660 "tftp $fdtaddr $fdtfile;" \
661 "bootm $loadaddr - $fdtaddr"
663 #define CONFIG_RAMBOOTCOMMAND \
664 "setenv bootargs root=/dev/ram rw " \
665 "console=$consoledev,$baudrate $othbootargs;" \
666 "tftp $ramdiskaddr $ramdiskfile;" \
667 "tftp $loadaddr $bootfile;" \
668 "tftp $fdtaddr $fdtfile;" \
669 "bootm $loadaddr $ramdiskaddr $fdtaddr"
671 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
673 #include <asm/fsl_secure_boot.h>
675 #endif /* __CONFIG_H */