include/configs/cradle.h

   1 /*
   2  * (C) Copyright 2002
   3  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   4  *
   5  * (C) Copyright 2002
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35 #define CONFIG_PXA250           1       /* This is an PXA250 CPU    */
  36 #define CONFIG_HHP_CRADLE       1       /* on an Cradle Board       */
  37
  38 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
  39
  40 /* we will never enable dcache, because we have to setup MMU first */
  41 #define CONFIG_SYS_NO_DCACHE
  42
  43 /*
  44  * Size of malloc() pool
  45  */
  46 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 128*1024)
  47 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* size in bytes reserved for initial data */
  48
  49 /*
  50  * Hardware drivers
  51  */
  52 #define CONFIG_NET_MULTI
  53 #define CONFIG_SMC91111
  54 #define CONFIG_SMC91111_BASE 0x10000300
  55 #define CONFIG_SMC91111_EXT_PHY
  56 #define CONFIG_SMC_USE_32_BIT
  57
  58 /*
  59  * select serial console configuration
  60  */
  61 #define CONFIG_PXA_SERIAL
  62 #define CONFIG_FFUART          1       /* we use FFUART on LUBBOCK */
  63
  64 /* allow to overwrite serial and ethaddr */
  65 #define CONFIG_ENV_OVERWRITE
  66
  67 #define CONFIG_BAUDRATE         115200
  68
  69
  70 /*
  71  * BOOTP options
  72  */
  73 #define CONFIG_BOOTP_BOOTFILESIZE
  74 #define CONFIG_BOOTP_BOOTPATH
  75 #define CONFIG_BOOTP_GATEWAY
  76 #define CONFIG_BOOTP_HOSTNAME
  77
  78
  79 /*
  80  * Command line configuration.
  81  */
  82 #include <config_cmd_default.h>
  83
  84
  85 #define CONFIG_BOOTDELAY        3
  86 #define CONFIG_BOOTARGS         "root=/dev/mtdblock2 console=ttyS0,115200"
  87 #define CONFIG_ETHADDR          08:00:3e:26:0a:5b
  88 #define CONFIG_NETMASK          255.255.0.0
  89 #define CONFIG_IPADDR           192.168.0.21
  90 #define CONFIG_SERVERIP         192.168.0.250
  91 #define CONFIG_BOOTCOMMAND      "bootm 40000"
  92 #define CONFIG_CMDLINE_TAG
  93
  94 /*
  95  * Miscellaneous configurable options
  96  */
  97 #define CONFIG_SYS_LONGHELP                            /* undef to save memory         */
  98 #define CONFIG_SYS_PROMPT              "=> "   /* Monitor Command Prompt       */
  99 #define CONFIG_SYS_CBSIZE              256             /* Console I/O Buffer Size      */
 100 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 101 #define CONFIG_SYS_MAXARGS             16              /* max number of command args   */
 102 #define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE      /* Boot Argument Buffer Size    */
 103
 104 #define CONFIG_SYS_MEMTEST_START       0xa0400000      /* memtest works on     */
 105 #define CONFIG_SYS_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
 106
 107 #define CONFIG_SYS_LOAD_ADDR           0xa2000000      /* default load address */
 108
 109 #define CONFIG_SYS_HZ                   1000
 110 #define CONFIG_SYS_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
 111
 112                                                 /* valid baudrates */
 113 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 114
 115 /*
 116  * Stack sizes
 117  *
 118  * The stack sizes are set up in start.S using the settings below
 119  */
 120 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 121 #ifdef CONFIG_USE_IRQ
 122 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 123 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 124 #endif
 125
 126 /*
 127  * Physical Memory Map
 128  */
 129 #define CONFIG_NR_DRAM_BANKS    4          /* we have 2 banks of DRAM */
 130 #define PHYS_SDRAM_1            0xa0000000 /* SDRAM Bank #1 */
 131 #define PHYS_SDRAM_1_SIZE       0x01000000 /* 64 MB */
 132 #define PHYS_SDRAM_2            0xa4000000 /* SDRAM Bank #2 */
 133 #define PHYS_SDRAM_2_SIZE       0x00000000 /* 0 MB */
 134 #define PHYS_SDRAM_3            0xa8000000 /* SDRAM Bank #3 */
 135 #define PHYS_SDRAM_3_SIZE       0x00000000 /* 0 MB */
 136 #define PHYS_SDRAM_4            0xac000000 /* SDRAM Bank #4 */
 137 #define PHYS_SDRAM_4_SIZE       0x00000000 /* 0 MB */
 138
 139 #define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
 140 #define PHYS_FLASH_2            0x04000000 /* Flash Bank #1 */
 141 #define PHYS_FLASH_SIZE         0x02000000 /* 32 MB */
 142
 143 #define CONFIG_SYS_DRAM_BASE           0xa0000000
 144 #define CONFIG_SYS_DRAM_SIZE           0x04000000
 145
 146 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 147
 148 /*
 149  * FLASH and environment organization
 150  */
 151 #define CONFIG_SYS_MAX_FLASH_BANKS     1     /* max number of memory banks           */
 152 #define CONFIG_SYS_MAX_FLASH_SECT      32    /* max number of sectors on one chip    */
 153
 154 /* timeout values are in ticks */
 155 #define CONFIG_SYS_FLASH_ERASE_TOUT    (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
 156 #define CONFIG_SYS_FLASH_WRITE_TOUT    (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 157
 158 #define CONFIG_ENV_IS_IN_FLASH  1
 159 #define CONFIG_ENV_ADDR                         0x00020000      /* absolute address for now   */
 160 #define CONFIG_ENV_SIZE                         0x20000    /* 8K ouch, this may later be */
 161
 162 /******************************************************************************
 163  *
 164  * CPU specific defines
 165  *
 166  ******************************************************************************/
 167
 168 /*
 169  * GPIO settings
 170  *
 171  * GPIO pin assignments
 172  * GPIO     Name        Dir Out AF
 173  * 0        NC
 174  * 1        NC
 175  * 2        SIRQ1       I
 176  * 3        SIRQ2       I
 177  * 4        SIRQ3       I
 178  * 5        DMAACK1     O   0
 179  * 6        DMAACK2     O   0
 180  * 7        DMAACK3     O   0
 181  * 8        TC1         O   0
 182  * 9        TC2         O   0
 183  * 10       TC3         O   0
 184  * 11       nDMAEN      O   1
 185  * 12       AENCTRL     O   0
 186  * 13       PLDTC       O   0
 187  * 14       ETHIRQ      I
 188  * 15       NC
 189  * 16       NC
 190  * 17       NC
 191  * 18       RDY         I
 192  * 19       DMASIO      I
 193  * 20       ETHIRQ      NC
 194  * 21       NC
 195  * 22       PGMEN       O   1    FIXME for debug only enable flash
 196  * 23       NC
 197  * 24       NC
 198  * 25       NC
 199  * 26       NC
 200  * 27       NC
 201  * 28       NC
 202  * 29       NC
 203  * 30       NC
 204  * 31       NC
 205  * 32       NC
 206  * 33       NC
 207  * 34       FFRXD       I       01
 208  * 35       FFCTS       I       01
 209  * 36       FFDCD       I       01
 210  * 37       FFDSR       I       01
 211  * 38       FFRI        I       01
 212  * 39       FFTXD       O   1   10
 213  * 40       FFDTR       O   0   10
 214  * 41       FFRTS       O   0   10
 215  * 42       RS232FOFF   O   0   00
 216  * 43       NC
 217  * 44       NC
 218  * 45       IRSL0       O   0
 219  * 46       IRRX0       I       01
 220  * 47       IRTX0       O   0   10
 221  * 48       NC
 222  * 49       nIOWE       O   0
 223  * 50       NC
 224  * 51       NC
 225  * 52       NC
 226  * 53       NC
 227  * 54       NC
 228  * 55       NC
 229  * 56       NC
 230  * 57       NC
 231  * 58       DKDIRQ      I
 232  * 59       NC
 233  * 60       NC
 234  * 61       NC
 235  * 62       NC
 236  * 63       NC
 237  * 64       COMLED      O   0
 238  * 65       COMLED      O   0
 239  * 66       COMLED      O   0
 240  * 67       COMLED      O   0
 241  * 68       COMLED      O   0
 242  * 69       COMLED      O   0
 243  * 70       COMLED      O   0
 244  * 71       COMLED      O   0
 245  * 72       NC
 246  * 73       NC
 247  * 74       NC
 248  * 75       NC
 249  * 76       NC
 250  * 77       NC
 251  * 78       CSIO        O   1
 252  * 79       NC
 253  * 80       CSETH       O   1
 254  *
 255  * NOTE: All NC's are defined to be outputs
 256  *
 257  */
 258 /* Pin direction control */
 259 /* NOTE GPIO 0, 61, 62 are set for inputs due to CPLD SPAREs */
 260 #define CONFIG_SYS_GPDR0_VAL       0xfff3bf02
 261 #define CONFIG_SYS_GPDR1_VAL       0xfbffbf83
 262 #define CONFIG_SYS_GPDR2_VAL       0x0001ffff
 263 /* Set and Clear registers */
 264 #define CONFIG_SYS_GPSR0_VAL       0x00400800
 265 #define CONFIG_SYS_GPSR1_VAL       0x00000480
 266 #define CONFIG_SYS_GPSR2_VAL       0x00014000
 267 #define CONFIG_SYS_GPCR0_VAL       0x00000000
 268 #define CONFIG_SYS_GPCR1_VAL       0x00000000
 269 #define CONFIG_SYS_GPCR2_VAL       0x00000000
 270 /* Edge detect registers (these are set by the kernel) */
 271 #define CONFIG_SYS_GRER0_VAL       0x00000000
 272 #define CONFIG_SYS_GRER1_VAL       0x00000000
 273 #define CONFIG_SYS_GRER2_VAL       0x00000000
 274 #define CONFIG_SYS_GFER0_VAL       0x00000000
 275 #define CONFIG_SYS_GFER1_VAL       0x00000000
 276 #define CONFIG_SYS_GFER2_VAL       0x00000000
 277 /* Alternate function registers */
 278 #define CONFIG_SYS_GAFR0_L_VAL     0x00000000
 279 #define CONFIG_SYS_GAFR0_U_VAL     0x00000010
 280 #define CONFIG_SYS_GAFR1_L_VAL     0x900a9550
 281 #define CONFIG_SYS_GAFR1_U_VAL     0x00000008
 282 #define CONFIG_SYS_GAFR2_L_VAL     0x20000000
 283 #define CONFIG_SYS_GAFR2_U_VAL     0x00000002
 284
 285 /*
 286  * Clocks, power control and interrupts
 287  */
 288 #define CONFIG_SYS_PSSR_VAL        0x00000020
 289 #define CONFIG_SYS_CCCR_VAL        0x00000141  /* 100 MHz memory, 200 MHz CPU  */
 290 #define CONFIG_SYS_CKEN_VAL        0x00000060  /* FFUART and STUART enabled    */
 291 #define CONFIG_SYS_ICMR_VAL        0x00000000  /* No interrupts enabled        */
 292
 293 /* FIXME
 294  *
 295  * RTC settings
 296  * Watchdog
 297  *
 298  */
 299
 300 /*
 301  * Memory settings
 302  *
 303  * FIXME Can ethernet be burst read and/or write?? This is set for lubbock
 304  *       Verify timings on all
 305  */
 306 #define CONFIG_SYS_MSC0_VAL        0x000023FA  /* flash bank    (cs0)   */
 307 /*#define CONFIG_SYS_MSC1_VAL        0x00003549  / * SuperIO bank  (cs2)   */
 308 #define CONFIG_SYS_MSC1_VAL        0x0000354c  /* SuperIO bank  (cs2)   */
 309 #define CONFIG_SYS_MSC2_VAL        0x00001224  /* Ethernet bank (cs4)   */
 310 #ifdef REDBOOT_WAY
 311 #define CONFIG_SYS_MDCNFG_VAL      0x00001aa1  /* FIXME can DTC be 01?     */
 312 #define CONFIG_SYS_MDMRS_VAL       0x00000000
 313 #define CONFIG_SYS_MDREFR_VAL      0x00018018
 314 #else
 315 #define CONFIG_SYS_MDCNFG_VAL      0x00001aa1  /* FIXME can DTC be 01?     */
 316 #define CONFIG_SYS_MDMRS_VAL       0x00000000
 317 #define CONFIG_SYS_MDREFR_VAL      0x00403018  /* Initial setting, individual bits set in lowlevel_init.S */
 318 #endif
 319
 320 /*
 321  * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
 322  */
 323 #define CONFIG_SYS_MECR_VAL          0x00000000
 324 #define CONFIG_SYS_MCMEM0_VAL        0x00010504
 325 #define CONFIG_SYS_MCMEM1_VAL        0x00010504
 326 #define CONFIG_SYS_MCATT0_VAL        0x00010504
 327 #define CONFIG_SYS_MCATT1_VAL        0x00010504
 328 #define CONFIG_SYS_MCIO0_VAL         0x00004715
 329 #define CONFIG_SYS_MCIO1_VAL         0x00004715
 330
 331 /* Board specific defines */
 332
 333 /* LED defines */
 334 #define YELLOW    0x03
 335 #define RED       0x02
 336 #define GREEN     0x01
 337 #define OFF       0x00
 338 #define LED_IRDA0 0
 339 #define LED_IRDA1 2
 340 #define LED_IRDA2 4
 341 #define LED_IRDA3 6
 342
 343 /* SuperIO defines */
 344 #define CRADLE_SIO_INDEX      0x2e
 345 #define CRADLE_SIO_DATA       0x2f
 346
 347 /* IO defines */
 348 #define CRADLE_CPLD_PHYS      0x08000000
 349 #define CRADLE_SIO1_PHYS      0x08100000
 350 #define CRADLE_SIO2_PHYS      0x08200000
 351 #define CRADLE_SIO3_PHYS      0x08300000
 352 #define CRADLE_ETH_PHYS       0x10000000
 353
 354 #ifndef __ASSEMBLY__
 355
 356 /* global prototypes */
 357 void led_code(int code, int color);
 358
 359 #endif
 360
 361 #endif  /* __CONFIG_H */