include/configs/csb272.h

   1 /*
   2  * (C) Copyright 2004
   3  * Tolunay Orkun, Nextio Inc., torkun@nextio.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_405GP            1       /* This is a PPC405GP CPU       */
  21 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  22 #define CONFIG_CSB272           1       /* on a Cogent CSB272 board     */
  23 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f()    */
  24 #define CONFIG_LAST_STAGE_INIT  1       /* Call last_stage_init()       */
  25 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  26
  27 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  28
  29 /*
  30  * OS Bootstrap configuration
  31  *
  32  */
  33
  34 #if 0
  35 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled */
  36 #else
  37 #define CONFIG_BOOTDELAY        3       /* autoboot after X seconds     */
  38 #endif
  39
  40 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check keypress when bootdelay = 0 */
  41
  42 #if 1
  43 #undef  CONFIG_BOOTARGS
  44 #define CONFIG_BOOTCOMMAND \
  45         "setenv bootargs console=ttyS0,38400 debug " \
  46         "root=/dev/ram rw ramdisk_size=4096 " \
  47         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
  48         "bootm fe000000 fe100000"
  49 #endif
  50
  51 #if 0
  52 #undef  CONFIG_BOOTARGS
  53 #define CONFIG_BOOTCOMMAND \
  54         "bootp; " \
  55         "setenv bootargs console=ttyS0,38400 debug " \
  56         "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
  57         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
  58         "bootm"
  59 #endif
  60
  61 /*
  62  * BOOTP options
  63  */
  64 #define CONFIG_BOOTP_SUBNETMASK
  65 #define CONFIG_BOOTP_GATEWAY
  66 #define CONFIG_BOOTP_HOSTNAME
  67 #define CONFIG_BOOTP_BOOTPATH
  68 #define CONFIG_BOOTP_BOOTFILESIZE
  69 #define CONFIG_BOOTP_DNS2
  70
  71
  72 /*
  73  * Command line configuration.
  74  */
  75 #include <config_cmd_default.h>
  76
  77 #define CONFIG_CMD_ASKENV
  78 #define CONFIG_CMD_BEDBUG
  79 #define CONFIG_CMD_ELF
  80 #define CONFIG_CMD_IRQ
  81 #define CONFIG_CMD_I2C
  82 #define CONFIG_CMD_PCI
  83 #define CONFIG_CMD_DATE
  84 #define CONFIG_CMD_MII
  85 #define CONFIG_CMD_PING
  86 #define CONFIG_CMD_DHCP
  87
  88
  89 /*
  90  * Serial download configuration
  91  *
  92  */
  93 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  94 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  95
  96 /*
  97  * KGDB Configuration
  98  *
  99  */
 100 #if defined(CONFIG_CMD_KGDB)
 101 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 102 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 103 #endif
 104
 105 /*
 106  * Miscellaneous configurable options
 107  *
 108  */
 109 #undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser */
 110
 111 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 112 #if defined(CONFIG_CMD_KGDB)
 113 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
 114 #else
 115 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 116 #endif
 117 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 118 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 119 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 120
 121 #define CONFIG_SYS_MEMTEST_START        0x0400000 /* memtest works on */
 122 #define CONFIG_SYS_MEMTEST_END          0x0C00000 /* 4 ... 12 MB in DRAM */
 123
 124 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 125 #define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_info (bd_t) */
 126 #define CONFIG_SYS_LOAD_ADDR            0x100000 /* default load address */
 127
 128 /*
 129  * For booting Linux, the board info and command line data
 130  * have to be in the first 8 MB of memory, since this is
 131  * the maximum mapped by the Linux kernel during initialization.
 132  */
 133 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 134
 135 /*
 136  * watchdog configuration
 137  *
 138  */
 139 #undef  CONFIG_WATCHDOG                 /* watchdog disabled */
 140
 141 /*
 142  * UART configuration
 143  *
 144  */
 145 #define CONFIG_CONS_INDEX               1       /* Use UART0            */
 146 #define CONFIG_SYS_NS16550
 147 #define CONFIG_SYS_NS16550_SERIAL
 148 #define CONFIG_SYS_NS16550_REG_SIZE     1
 149 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 150
 151 #define CONFIG_SYS_EXT_SERIAL_CLOCK     3868400 /* use external serial clock */
 152 #undef  CONFIG_SYS_BASE_BAUD
 153 #define CONFIG_BAUDRATE         38400   /* Default baud rate */
 154 #define CONFIG_SYS_BAUDRATE_TABLE      \
 155     { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
 156
 157 /*
 158  * I2C configuration
 159  *
 160  */
 161 #define CONFIG_SYS_I2C
 162 #define CONFIG_SYS_I2C_PPC4XX
 163 #define CONFIG_SYS_I2C_PPC4XX_CH0
 164 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
 165 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F    /* I2C slave address */
 166
 167 /*
 168  * MII PHY configuration
 169  *
 170  */
 171 #define CONFIG_PPC4xx_EMAC
 172 #define CONFIG_MII              1       /* MII PHY management           */
 173 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
 174 #define CONFIG_PHY_CMD_DELAY    40      /* PHY COMMAND delay            */
 175                                         /* 32usec min. for LXT971A      */
 176 #define CONFIG_PHY_RESET_DELAY  300     /* PHY RESET recovery delay     */
 177
 178 /*
 179  * RTC configuration
 180  *
 181  * Note that DS1307 RTC is limited to 100Khz I2C bus.
 182  *
 183  */
 184 #define CONFIG_RTC_DS1307               /* Use Dallas 1307 RTC          */
 185
 186 /*
 187  * PCI stuff
 188  *
 189  */
 190 #define CONFIG_PCI                      /* include pci support          */
 191 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 192 #define PCI_HOST_ADAPTER        0       /* configure ar pci adapter     */
 193 #define PCI_HOST_FORCE          1       /* configure as pci host        */
 194 #define PCI_HOST_AUTO           2       /* detected via arbiter enable  */
 195
 196 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 197 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 198                                         /* resource configuration       */
 199 #undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 200 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 201
 202 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
 203 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
 204 #define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
 205 #define CONFIG_SYS_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
 206 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 207 #define CONFIG_SYS_PCI_PTM2LA  0x00000000      /* disabled                     */
 208 #define CONFIG_SYS_PCI_PTM2MS  0x00000000      /* disabled                     */
 209 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 210
 211 /*
 212  * IDE stuff
 213  *
 214  */
 215 #undef  CONFIG_IDE_PCMCIA               /* no pcmcia interface required */
 216 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 217 #undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
 218
 219 /*
 220  * Environment configuration
 221  *
 222  */
 223 #define CONFIG_ENV_IS_IN_FLASH  1       /* environment is in FLASH      */
 224 #undef CONFIG_ENV_IS_IN_NVRAM
 225 #undef CONFIG_ENV_IS_IN_EEPROM
 226
 227 /*
 228  * General Memory organization
 229  *
 230  * Start addresses for the final memory configuration
 231  * (Set up by the startup code)
 232  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 233  */
 234 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 235 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 236 #define CONFIG_SYS_FLASH_SIZE           0x02000000
 237 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 238 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 KB for Monitor */
 239 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024) /* Reserve 128 KB for malloc() */
 240
 241 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
 242 #define CONFIG_SYS_RAMSTART
 243 #endif
 244
 245 #if defined(CONFIG_ENV_IS_IN_FLASH)
 246 #define CONFIG_ENV_IN_OWN_SECTOR        1          /* Give Environment own sector */
 247 #define CONFIG_ENV_ADDR         0xFFF00000 /* Address of Environment Sector */
 248 #define CONFIG_ENV_SIZE         0x00001000 /* Size of Environment */
 249 #define CONFIG_ENV_SECT_SIZE    0x00040000 /* Size of Environment Sector */
 250 #endif
 251
 252 /*
 253  * FLASH Device configuration
 254  *
 255  */
 256 #define CONFIG_SYS_FLASH_CFI            1       /* flash is CFI conformant      */
 257 #define CONFIG_FLASH_CFI_DRIVER 1       /* use common cfi driver        */
 258 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster) */
 259 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max # of memory banks        */
 260 #define CONFIG_SYS_FLASH_INCREMENT      0       /* there is only one bank       */
 261 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max # of sectors on one chip */
 262 #define CONFIG_SYS_FLASH_PROTECTION     1       /* hardware flash protection    */
 263 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 264
 265 /*
 266  * On Chip Memory location/size
 267  *
 268  */
 269 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 270 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 271
 272 /*
 273  * Global info and initial stack
 274  *
 275  */
 276 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
 277 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
 278 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 279 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 280
 281 /*
 282  * Miscellaneous board specific definitions
 283  *
 284  */
 285 #define CONFIG_SYS_I2C_PLL_ADDR 0x58    /* I2C address of AMIS FS6377-01 PLL */
 286 #define CONFIG_I2CFAST          1       /* enable "i2cfast" env. setting     */
 287
 288 #endif  /* __CONFIG_H */