include/configs/csb472.h

   1 /*
   2  * (C) Copyright 2004
   3  * Tolunay Orkun, Nextio Inc., torkun@nextio.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_405GP            1       /* This is a PPC405GP CPU       */
  21 #define CONFIG_CSB472           1       /* on a Cogent CSB472 board     */
  22 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f()    */
  23 #define CONFIG_LAST_STAGE_INIT  1       /* Call last_stage_init()       */
  24 #define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
  25
  26 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  27
  28 /*
  29  * OS Bootstrap configuration
  30  *
  31  */
  32
  33 #if 0
  34 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled */
  35 #else
  36 #define CONFIG_BOOTDELAY        3       /* autoboot after X seconds     */
  37 #endif
  38
  39 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check keypress when bootdelay = 0 */
  40
  41 #if 1
  42 #undef  CONFIG_BOOTARGS
  43 #define CONFIG_BOOTCOMMAND \
  44         "setenv bootargs console=ttyS0,38400 debug " \
  45         "root=/dev/ram rw ramdisk_size=4096 " \
  46         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
  47         "bootm ff800000 ff900000"
  48 #endif
  49
  50 #if 0
  51 #undef  CONFIG_BOOTARGS
  52 #define CONFIG_BOOTCOMMAND \
  53         "bootp; " \
  54         "setenv bootargs console=ttyS0,38400 debug " \
  55         "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
  56         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
  57         "bootm"
  58 #endif
  59
  60 /*
  61  * BOOTP options
  62  */
  63 #define CONFIG_BOOTP_SUBNETMASK
  64 #define CONFIG_BOOTP_GATEWAY
  65 #define CONFIG_BOOTP_HOSTNAME
  66 #define CONFIG_BOOTP_BOOTPATH
  67 #define CONFIG_BOOTP_BOOTFILESIZE
  68 #define CONFIG_BOOTP_DNS2
  69
  70
  71 /*
  72  * Command line configuration.
  73  */
  74 #define CONFIG_CMD_ASKENV
  75 #define CONFIG_CMD_BEDBUG
  76 #define CONFIG_CMD_ELF
  77 #define CONFIG_CMD_IRQ
  78 #define CONFIG_CMD_I2C
  79 #define CONFIG_CMD_PCI
  80 #define CONFIG_CMD_DATE
  81 #define CONFIG_CMD_MII
  82 #define CONFIG_CMD_PING
  83 #define CONFIG_CMD_DHCP
  84
  85 /*
  86  * Serial download configuration
  87  *
  88  */
  89 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  90 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  91
  92 /*
  93  * KGDB Configuration
  94  *
  95  */
  96 #if defined(CONFIG_CMD_KGDB)
  97 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
  98 #endif
  99
 100 /*
 101  * Miscellaneous configurable options
 102  *
 103  */
 104 #undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser */
 105
 106 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 107 #if defined(CONFIG_CMD_KGDB)
 108 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
 109 #else
 110 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 111 #endif
 112 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 113 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 114 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 115
 116 #define CONFIG_SYS_MEMTEST_START        0x0400000 /* memtest works on */
 117 #define CONFIG_SYS_MEMTEST_END          0x0C00000 /* 4 ... 12 MB in DRAM */
 118
 119 #define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_info (bd_t) */
 120 #define CONFIG_SYS_LOAD_ADDR            0x100000 /* default load address */
 121
 122 /*
 123  * For booting Linux, the board info and command line data
 124  * have to be in the first 8 MB of memory, since this is
 125  * the maximum mapped by the Linux kernel during initialization.
 126  */
 127 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 128
 129 /*
 130  * watchdog configuration
 131  *
 132  */
 133 #undef  CONFIG_WATCHDOG                 /* watchdog disabled */
 134
 135 /*
 136  * UART configuration
 137  *
 138  */
 139 #define CONFIG_CONS_INDEX               1       /* Use UART0            */
 140 #define CONFIG_SYS_NS16550
 141 #define CONFIG_SYS_NS16550_SERIAL
 142 #define CONFIG_SYS_NS16550_REG_SIZE     1
 143 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 144
 145 #undef CONFIG_SYS_EXT_SERIAL_CLOCK              /* use internal serial clock */
 146 #define CONFIG_SYS_BASE_BAUD            691200
 147 #define CONFIG_BAUDRATE         38400   /* Default baud rate */
 148 #define CONFIG_SYS_BAUDRATE_TABLE      \
 149     { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
 150
 151 /*
 152  * I2C configuration
 153  *
 154  */
 155 #define CONFIG_SYS_I2C
 156 #define CONFIG_SYS_I2C_PPC4XX
 157 #define CONFIG_SYS_I2C_PPC4XX_CH0
 158 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
 159 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F    /* I2C slave address */
 160
 161 /*
 162  * MII PHY configuration
 163  *
 164  */
 165 #define CONFIG_PPC4xx_EMAC
 166 #define CONFIG_MII              1       /* MII PHY management           */
 167 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
 168 #define CONFIG_PHY_CMD_DELAY    40      /* PHY COMMAND delay            */
 169                                         /* 32usec min. for LXT971A      */
 170 #define CONFIG_PHY_RESET_DELAY  300     /* PHY RESET recovery delay     */
 171
 172 /*
 173  * RTC configuration
 174  *
 175  * Note that DS1307 RTC is limited to 100Khz I2C bus.
 176  *
 177  */
 178 #define CONFIG_RTC_DS1307               /* Use Dallas 1307 RTC          */
 179
 180 /*
 181  * PCI stuff
 182  *
 183  */
 184 #define CONFIG_PCI                      /* include pci support          */
 185 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 186 #define PCI_HOST_ADAPTER        0       /* configure ar pci adapter     */
 187 #define PCI_HOST_FORCE          1       /* configure as pci host        */
 188 #define PCI_HOST_AUTO           2       /* detected via arbiter enable  */
 189
 190 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 191 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 192                                         /* resource configuration       */
 193 #undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 194 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 195
 196 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
 197 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
 198 #define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
 199 #define CONFIG_SYS_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
 200 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 201 #define CONFIG_SYS_PCI_PTM2LA  0x00000000      /* disabled                     */
 202 #define CONFIG_SYS_PCI_PTM2MS  0x00000000      /* disabled                     */
 203 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 204
 205 /*
 206  * IDE stuff
 207  *
 208  */
 209 #undef  CONFIG_IDE_PCMCIA               /* no pcmcia interface required */
 210 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 211 #undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
 212
 213 /*
 214  * Environment configuration
 215  *
 216  */
 217 #define CONFIG_ENV_IS_IN_FLASH  1       /* environment is in FLASH      */
 218 #undef CONFIG_ENV_IS_IN_NVRAM
 219 #undef CONFIG_ENV_IS_IN_EEPROM
 220
 221 /*
 222  * General Memory organization
 223  *
 224  * Start addresses for the final memory configuration
 225  * (Set up by the startup code)
 226  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 227  */
 228 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 229 #define CONFIG_SYS_FLASH_BASE           0xFF800000
 230 #define CONFIG_SYS_FLASH_SIZE           0x00800000
 231 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 232 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 KB for Monitor */
 233 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024) /* Reserve 128 KB for malloc() */
 234
 235 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
 236 #define CONFIG_SYS_RAMSTART
 237 #endif
 238
 239 #if defined(CONFIG_ENV_IS_IN_FLASH)
 240 #define CONFIG_ENV_IN_OWN_SECTOR        1          /* Give Environment own sector */
 241 #define CONFIG_ENV_ADDR         0xFFF00000 /* Address of Environment Sector */
 242 #define CONFIG_ENV_SIZE         0x00001000 /* Size of Environment */
 243 #define CONFIG_ENV_SECT_SIZE    0x00040000 /* Size of Environment Sector */
 244 #endif
 245
 246 /*
 247  * FLASH Device configuration
 248  *
 249  */
 250 #define CONFIG_SYS_FLASH_CFI            1       /* flash is CFI conformant      */
 251 #define CONFIG_FLASH_CFI_DRIVER 1       /* use common cfi driver        */
 252 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster) */
 253 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max # of memory banks        */
 254 #define CONFIG_SYS_FLASH_INCREMENT      0       /* there is only one bank       */
 255 #define CONFIG_SYS_MAX_FLASH_SECT       64      /* max # of sectors on one chip */
 256 #define CONFIG_SYS_FLASH_PROTECTION     1       /* hardware flash protection    */
 257 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 258
 259 /*
 260  * On Chip Memory location/size
 261  *
 262  */
 263 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 264 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 265
 266 /*
 267  * Global info and initial stack
 268  *
 269  */
 270 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
 271 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
 272 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 273 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 274
 275 /*
 276  * Miscellaneous board specific definitions
 277  *
 278  */
 279 #define CONFIG_I2CFAST          1       /* enable "i2cfast" env. setting     */
 280
 281 #endif  /* __CONFIG_H */