include/configs/davinci_dvevm.h

   1 /*
   2  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation; either version 2 of
   7  * the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17  * MA 02111-1307 USA
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22 #include <asm/sizes.h>
  23
  24 /*
  25  * Define this to make U-Boot skip low level initialization when loaded
  26  * by initial bootloader. Not required by NAND U-Boot version but IS
  27  * required for a NOR version used to burn the real NOR U-Boot into
  28  * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
  29  * so it is NOT possible to build a U-Boot with both NAND and NOR routines.
  30  * NOR U-Boot is loaded directly from Flash so it must perform all the
  31  * low level initialization itself. NAND version is loaded by an initial
  32  * bootloader (UBL in TI-ese) that performs such an initialization so it's
  33  * skipped in NAND version. The third DaVinci boot mode loads a bootloader
  34  * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
  35  * performing low level init prior to loading. All that means we can NOT use
  36  * NAND version to put U-Boot into NOR because it doesn't have NOR support and
  37  * we can NOT use NOR version because it performs low level initialization
  38  * effectively destroying itself in DDR memory. That's why a separate NOR
  39  * version with this define is needed. It is loaded via UART, then one uses
  40  * it to somehow download a proper NOR version built WITHOUT this define to
  41  * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
  42  * NOR support into the initial bootloader so it won't be needed but DaVinci
  43  * static RAM might be too small for this (I have something like 2Kbytes left
  44  * as of now, without NOR support) so this might've not happened...
  45  *
  46 #define CONFIG_NOR_UART_BOOT
  47  */
  48
  49 /*=======*/
  50 /* Board */
  51 /*=======*/
  52 #define DV_EVM
  53 #define CFG_NAND_SMALLPAGE
  54 #define CFG_USE_NOR
  55 #define CFG_USE_INTEL_NOR       /* Define this when your DVEVM has Intel
  56                                  * flash instead of AMD flash
  57                                  */
  58 /*===================*/
  59 /* SoC Configuration */
  60 /*===================*/
  61 #define CONFIG_ARM926EJS                        /* arm926ejs CPU core */
  62 #define CONFIG_SYS_CLK_FREQ     297000000       /* Arm Clock frequency */
  63 #define CFG_TIMERBASE           0x01c21400      /* use timer 0 */
  64 #define CFG_HZ_CLOCK            27000000        /* Timer Input clock freq */
  65 #define CFG_HZ                  1000
  66 #define CFG_DAVINCI_PINMUX_0    0x00000c1f
  67 #define CFG_DAVINCI_WAITCFG     0x00000000
  68 #define CFG_DAVINCI_ACFG2       0x3ffffffd      /* CE configs */
  69 #define CFG_DAVINCI_ACFG3       0x3ffffffd
  70 #define CFG_DAVINCI_ACFG4       0x3ffffffd
  71 #define CFG_DAVINCI_ACFG5       0x3ffffffd
  72 #undef  CFG_DAVINCI_NANDCE              /* When using NAND, define 2,3 or 4 */
  73 #define CFG_DAVINCI_DDRCTL      0x50006405      /* DDR timing config */
  74 #define CFG_DAVINCI_SDREF       0x000005c3
  75 #define CFG_DAVINCI_SDCFG       0x00178632      /* 8 banks */
  76 #define CFG_DAVINCI_SDTIM0      0x28923211
  77 #define CFG_DAVINCI_SDTIM1      0x0016c722
  78 #define CFG_DAVINCI_MMARG_BRF0  0x00444400
  79 /* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
  80 #define CFG_DAVINCI_PLL1_PLLM   0x15
  81 #define CFG_DAVINCI_PLL2_PLLM   0x17            /* 162 MHz */
  82 #define CFG_DAVINCI_PLL2_DIV1   0x0b            /* 54 MHz */
  83 #define CFG_DAVINCI_PLL2_DIV2   0x01
  84 /*====================================================*/
  85 /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
  86 /* on Sonata/DV_EVM board. No EEPROM on schmoogie.    */
  87 /*====================================================*/
  88 #define CFG_I2C_EEPROM_ADDR_LEN         2
  89 #define CFG_I2C_EEPROM_ADDR             0x50
  90 #define CFG_EEPROM_PAGE_WRITE_BITS      6
  91 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  20
  92 /*=============*/
  93 /* Memory Info */
  94 /*=============*/
  95 #define CFG_MALLOC_LEN          (0x10000 + 128*1024)    /* malloc() len */
  96 #define CFG_GBL_DATA_SIZE       128             /* reserved for initial data */
  97 #define CFG_MEMTEST_START       0x80000000      /* memtest start address */
  98 #define CFG_MEMTEST_END         0x81000000      /* 16MB RAM test */
  99 #define CONFIG_NR_DRAM_BANKS    1               /* we have 1 bank of DRAM */
 100 #define CONFIG_STACKSIZE        (256*1024)      /* regular stack */
 101 #define PHYS_SDRAM_1            0x80000000      /* DDR Start */
 102 #define PHYS_SDRAM_1_SIZE       0x10000000      /* DDR size 256MB */
 103 #define DDR_8BANKS                              /* 8-bank DDR2 (256MB) */
 104 /*====================*/
 105 /* Serial Driver info */
 106 /*====================*/
 107 #define CFG_NS16550
 108 #define CFG_NS16550_SERIAL
 109 #define CFG_NS16550_REG_SIZE    4               /* NS16550 register size */
 110 #define CFG_NS16550_COM1        0x01c20000      /* Base address of UART0 */
 111 #define CFG_NS16550_CLK         27000000        /* Input clock to NS16550 */
 112 #define CONFIG_CONS_INDEX       1               /* use UART0 for console */
 113 #define CONFIG_BAUDRATE         115200          /* Default baud rate */
 114 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 115 /*===================*/
 116 /* I2C Configuration */
 117 /*===================*/
 118 #define CONFIG_HARD_I2C
 119 #define CONFIG_DRIVER_DAVINCI_I2C
 120 #define CFG_I2C_SPEED           80000   /* 100Kbps won't work, silicon bug */
 121 #define CFG_I2C_SLAVE           10      /* Bogus, master-only in U-Boot */
 122 /*==================================*/
 123 /* Network & Ethernet Configuration */
 124 /*==================================*/
 125 #define CONFIG_DRIVER_TI_EMAC
 126 #define CONFIG_MII
 127 #define CONFIG_BOOTP_DEFAULT
 128 #define CONFIG_BOOTP_DNS
 129 #define CONFIG_BOOTP_DNS2
 130 #define CONFIG_BOOTP_SEND_HOSTNAME
 131 #define CONFIG_NET_RETRY_COUNT  10
 132 /*=====================*/
 133 /* Flash & Environment */
 134 /*=====================*/
 135 #ifdef CFG_USE_NAND
 136 #undef CFG_ENV_IS_IN_FLASH
 137 #define CFG_NO_FLASH
 138 #define CFG_ENV_IS_IN_NAND              /* U-Boot env in NAND Flash */
 139 #ifdef CFG_NAND_SMALLPAGE
 140 #define CFG_ENV_SECT_SIZE       512     /* Env sector Size */
 141 #define CFG_ENV_SIZE            SZ_16K
 142 #else
 143 #define CFG_ENV_SECT_SIZE       2048    /* Env sector Size */
 144 #define CFG_ENV_SIZE            SZ_128K
 145 #endif
 146 #define CONFIG_SKIP_LOWLEVEL_INIT       /* U-Boot is loaded by a bootloader */
 147 #define CONFIG_SKIP_RELOCATE_UBOOT      /* to a proper address, init done */
 148 #define CFG_NAND_BASE           0x02000000
 149 #define CFG_NAND_HW_ECC
 150 #define CFG_MAX_NAND_DEVICE     1       /* Max number of NAND devices */
 151 #define NAND_MAX_CHIPS          1
 152 #define CFG_ENV_OFFSET          0x0     /* Block 0--not used by bootcode */
 153 #define DEF_BOOTM               ""
 154 #elif defined(CFG_USE_NOR)
 155 #ifdef CONFIG_NOR_UART_BOOT
 156 #define CONFIG_SKIP_LOWLEVEL_INIT       /* U-Boot is loaded by a bootloader */
 157 #define CONFIG_SKIP_RELOCATE_UBOOT      /* to a proper address, init done */
 158 #else
 159 #undef CONFIG_SKIP_LOWLEVEL_INIT
 160 #undef CONFIG_SKIP_RELOCATE_UBOOT
 161 #endif
 162 #define CFG_ENV_IS_IN_FLASH
 163 #undef  CFG_NO_FLASH
 164 #define CFG_FLASH_CFI_DRIVER
 165 #define CFG_FLASH_CFI
 166 #define CFG_MAX_FLASH_BANKS     1               /* max number of flash banks */
 167 #define CFG_ENV_ADDR            (PHYS_FLASH_1 + 0x40000)
 168 #define CFG_ENV_OFFSET          (CFG_ENV_ADDR)
 169 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
 170 #define PHYS_FLASH_1            0x02000000      /* CS2 Base address */
 171 #define CFG_FLASH_BASE          PHYS_FLASH_1    /* Flash Base for U-Boot */
 172 #define PHYS_FLASH_SIZE         0x2000000       /* Flash size 32MB */
 173 #define CFG_MAX_FLASH_SECT      (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
 174 #define CFG_ENV_SECT_SIZE       CFG_FLASH_SECT_SZ       /* Env sector Size */
 175 #ifdef CFG_USE_INTEL_NOR
 176 #define CFG_FLASH_SECT_SZ       0x20000 /* 128KB sect size INTEL Flash */
 177 #define CFG_FLASH_PROTECTION    1
 178 #else
 179 #define CFG_FLASH_SECT_SZ       0x10000 /* 64KB sect size AMD Flash */
 180 #endif
 181 #endif
 182 /*==============================*/
 183 /* U-Boot general configuration */
 184 /*==============================*/
 185 #undef  CONFIG_USE_IRQ                          /* No IRQ/FIQ in U-Boot */
 186 #define CONFIG_MISC_INIT_R
 187 #undef  CONFIG_BOOTDELAY
 188 #define CONFIG_BOOTFILE         "uImage"        /* Boot file name */
 189 #define CFG_PROMPT              "U-Boot > "     /* Monitor Command Prompt */
 190 #define CFG_CBSIZE              1024            /* Console I/O Buffer Size  */
 191 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)      /* Print buffer sz */
 192 #define CFG_MAXARGS             16              /* max number of command args */
 193 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size */
 194 #define CFG_LOAD_ADDR           0x80700000      /* default Linux kernel load address */
 195 #define CONFIG_VERSION_VARIABLE
 196 #define CONFIG_AUTO_COMPLETE            /* Won't work with hush so far, may be later */
 197 #define CFG_HUSH_PARSER
 198 #define CFG_PROMPT_HUSH_PS2     "> "
 199 #define CONFIG_CMDLINE_EDITING
 200 #define CFG_LONGHELP
 201 #define CONFIG_CRC32_VERIFY
 202 #define CONFIG_MX_CYCLIC
 203 /*===================*/
 204 /* Linux Information */
 205 /*===================*/
 206 #define LINUX_BOOT_PARAM_ADDR   0x80000100
 207 #define CONFIG_CMDLINE_TAG
 208 #define CONFIG_SETUP_MEMORY_TAGS
 209 #define CONFIG_BOOTARGS         "mem=120M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
 210 #define CONFIG_BOOTCOMMAND      "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2050000"
 211 /*=================*/
 212 /* U-Boot commands */
 213 /*=================*/
 214 #include <config_cmd_default.h>
 215 #define CONFIG_CMD_ASKENV
 216 #define CONFIG_CMD_DHCP
 217 #define CONFIG_CMD_DIAG
 218 #define CONFIG_CMD_I2C
 219 #define CONFIG_CMD_MII
 220 #define CONFIG_CMD_PING
 221 #define CONFIG_CMD_SAVES
 222 #define CONFIG_CMD_EEPROM
 223 #undef CONFIG_CMD_BDI
 224 #undef CONFIG_CMD_FPGA
 225 #undef CONFIG_CMD_SETGETDCR
 226 #ifdef CFG_USE_NAND
 227 #undef CONFIG_CMD_FLASH
 228 #undef CONFIG_CMD_IMLS
 229 #define CONFIG_CMD_NAND
 230 #elif defined(CFG_USE_NOR)
 231 #define CONFIG_CMD_JFFS2
 232 #else
 233 #error "Either CFG_USE_NAND or CFG_USE_NOR _MUST_ be defined !!!"
 234 #endif
 235 /*=======================*/
 236 /* KGDB support (if any) */
 237 /*=======================*/
 238 #ifdef CONFIG_CMD_KGDB
 239 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port */
 240 #define CONFIG_KGDB_SER_INDEX   1       /* which serial port to use */
 241 #endif
 242 #endif /* __CONFIG_H */