include/configs/debris.h

   1 /*
   2  * (C) Copyright 2001, 2002
   3  * Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* ------------------------------------------------------------------------- */
  25
  26 /*
  27  * board/config.h - configuration options, board specific
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  34
  35 /* Environments */
  36
  37 /* bootargs */
  38 #define CONFIG_BOOTARGS \
  39         "console=ttyS0,9600 init=/linuxrc " \
  40         "root=/dev/nfs rw nfsroot=192.168.0.1:" \
  41         "/tftpboot/target " \
  42         "ip=192.168.0.2:192.168.0.1:192.168.0.1:" \
  43         "255.255.255.0:debris:eth0:none " \
  44         "mtdparts=phys:12m(root),-(kernel)"
  45
  46 /* bootcmd */
  47 #define CONFIG_BOOTCOMMAND \
  48         "tftp 800000 pImage; " \
  49         "setenv bootargs console=ttyS0,9600 init=/linuxrc " \
  50         "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
  51         "ip=${ipaddr}:${serverip}:${gatewayip}:" \
  52         "${netmask}:${hostname}:eth0:none " \
  53         "mtdparts=phys:12m(root),-(kernel); " \
  54         "bootm 800000"
  55
  56 /* bootdelay */
  57 #define CONFIG_BOOTDELAY        5       /* autoboot 5s */
  58
  59 /* baudrate */
  60 #define CONFIG_BAUDRATE         9600    /* console baudrate = 9600bps   */
  61
  62 /* loads_echo */
  63 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
  64
  65 /* ethaddr */
  66 #undef CONFIG_ETHADDR
  67
  68 /* eth2addr */
  69 #undef CONFIG_ETH2ADDR
  70
  71 /* eth3addr */
  72 #undef CONFIG_ETH3ADDR
  73
  74 /* ipaddr */
  75 #define CONFIG_IPADDR   192.168.0.2
  76
  77 /* serverip */
  78 #define CONFIG_SERVERIP 192.168.0.1
  79
  80 /* autoload */
  81 #undef CONFIG_SYS_AUTOLOAD
  82
  83 /* rootpath */
  84 #define CONFIG_ROOTPATH "/tftpboot/target"
  85
  86 /* gatewayip */
  87 #define CONFIG_GATEWAYIP 192.168.0.1
  88
  89 /* netmask */
  90 #define CONFIG_NETMASK 255.255.255.0
  91
  92 /* hostname */
  93 #define CONFIG_HOSTNAME debris
  94
  95 /* bootfile */
  96 #define CONFIG_BOOTFILE "pImage"
  97
  98 /* loadaddr */
  99 #define CONFIG_LOADADDR 800000
 100
 101 /* preboot */
 102 #undef CONFIG_PREBOOT
 103
 104 /* clocks_in_mhz */
 105 #undef CONFIG_CLOCKS_IN_MHZ
 106
 107
 108 /*
 109  * High Level Configuration Options
 110  * (easy to change)
 111  */
 112
 113 #define CONFIG_MPC824X          1
 114 #define CONFIG_MPC8245          1
 115 #define CONFIG_DEBRIS           1
 116
 117 #if 0
 118 #define USE_DINK32              1
 119 #else
 120 #undef USE_DINK32
 121 #endif
 122
 123 #define CONFIG_CONS_INDEX       1
 124 #define CONFIG_BAUDRATE         9600
 125 #define CONFIG_DRAM_SPEED       100             /* MHz */
 126
 127
 128 /*
 129  * BOOTP options
 130  */
 131 #define CONFIG_BOOTP_BOOTFILESIZE
 132 #define CONFIG_BOOTP_BOOTPATH
 133 #define CONFIG_BOOTP_GATEWAY
 134 #define CONFIG_BOOTP_HOSTNAME
 135
 136
 137 /*
 138  * Command line configuration.
 139  */
 140 #include <config_cmd_default.h>
 141
 142 #define CONFIG_CMD_ASKENV
 143 #define CONFIG_CMD_CACHE
 144 #define CONFIG_CMD_DATE
 145 #define CONFIG_CMD_DHCP
 146 #define CONFIG_CMD_DIAG
 147 #define CONFIG_CMD_EEPROM
 148 #define CONFIG_CMD_ELF
 149 #define CONFIG_CMD_I2C
 150 #define CONFIG_CMD_JFFS2
 151 #define CONFIG_CMD_KGDB
 152 #define CONFIG_CMD_PCI
 153 #define CONFIG_CMD_PING
 154 #define CONFIG_CMD_SAVES
 155 #define CONFIG_CMD_SDRAM
 156
 157
 158 /*
 159  * Miscellaneous configurable options
 160  */
 161 #define CONFIG_SYS_LONGHELP             1               /* undef to save memory         */
 162 #define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt       */
 163 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 164 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size    */
 165 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 166 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 167 #define CONFIG_SYS_LOAD_ADDR            0x00100000      /* default load address         */
 168 #define CONFIG_SYS_HZ                   1000            /* decrementer freq: 1 ms ticks */
 169
 170 /*-----------------------------------------------------------------------
 171  * PCI stuff
 172  *-----------------------------------------------------------------------
 173  */
 174 #define CONFIG_PCI                              /* include pci support          */
 175 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 176 #define CONFIG_PCI_PNP
 177
 178 #define CONFIG_EEPRO100
 179 #define CONFIG_SYS_RX_ETH_BUFFER        8       /* use 8 rx buffer on eepro100  */
 180 #define CONFIG_EEPRO100_SROM_WRITE
 181
 182 #define PCI_ENET0_IOADDR        0x80000000
 183 #define PCI_ENET0_MEMADDR       0x80000000
 184 #define PCI_ENET1_IOADDR        0x81000000
 185 #define PCI_ENET1_MEMADDR       0x81000000
 186 /*-----------------------------------------------------------------------
 187  * Start addresses for the final memory configuration
 188  * (Set up by the startup code)
 189  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 190  */
 191 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 192 #define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
 193 #define CONFIG_VERY_BIG_RAM
 194
 195 #define CONFIG_SYS_RESET_ADDRESS        0xFFF00100
 196
 197 #if defined (USE_DINK32)
 198 #define CONFIG_SYS_MONITOR_LEN          0x00040000
 199 #define CONFIG_SYS_MONITOR_BASE 0x00090000
 200 #define CONFIG_SYS_RAMBOOT              1
 201 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 202 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
 203 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 204 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 205 #else
 206 #undef  CONFIG_SYS_RAMBOOT
 207 #define CONFIG_SYS_MONITOR_LEN          0x00040000
 208 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 209
 210
 211 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
 212 #define CONFIG_SYS_INIT_RAM_SIZE      0x1000
 213 #define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 214
 215 #endif
 216
 217 #define CONFIG_SYS_FLASH_BASE           0x7C000000
 218 #define CONFIG_SYS_FLASH_SIZE           (16*1024*1024)  /* debris has tiny eeprom       */
 219
 220 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)     /* Reserve 512 kB for malloc()  */
 221
 222 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest works on             */
 223 #define CONFIG_SYS_MEMTEST_END          0x04000000      /* 0 ... 32 MB in DRAM          */
 224
 225 #define CONFIG_SYS_EUMB_ADDR            0xFC000000
 226
 227 #define CONFIG_SYS_FLASH_RANGE_BASE     0xFF000000      /* flash memory address range   */
 228 #define CONFIG_SYS_FLASH_RANGE_SIZE     0x01000000
 229 #define FLASH_BASE0_PRELIM      0x7C000000      /* debris flash         */
 230
 231 /*
 232  * JFFS2 partitions
 233  *
 234  */
 235 /* No command line, one static partition, whole device */
 236 #undef CONFIG_CMD_MTDPARTS
 237 #define CONFIG_JFFS2_DEV                "nor0"
 238 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 239 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 240
 241 /* mtdparts command line support */
 242
 243 /* Use first bank for JFFS2, second bank contains U-Boot.
 244  *
 245  * Note: fake mtd_id's used, no linux mtd map file.
 246  */
 247 /*
 248 #define CONFIG_CMD_MTDPARTS
 249 #define MTDIDS_DEFAULT          "nor0=debris-0"
 250 #define MTDPARTS_DEFAULT        "mtdparts=debris-0:-(jffs2)"
 251 */
 252
 253 #define CONFIG_ENV_IS_IN_NVRAM      1
 254 #define CONFIG_ENV_OVERWRITE     1
 255 #define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1
 256 #define CONFIG_ENV_ADDR         0xFF000000 /* right at the start of NVRAM  */
 257 #define CONFIG_ENV_SIZE         0x400   /* Size of the Environment - 8K    */
 258 #define CONFIG_ENV_OFFSET               0       /* starting right at the beginning */
 259
 260 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xff000000
 261
 262 /*
 263  * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS =
 264  * NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET
 265  */
 266 #define CONFIG_SYS_NVRAM_VXWORKS_OFFS   0x6900
 267
 268 /*
 269  * select i2c support configuration
 270  *
 271  * Supported configurations are {none, software, hardware} drivers.
 272  * If the software driver is chosen, there are some additional
 273  * configuration items that the driver uses to drive the port pins.
 274  */
 275 #define CONFIG_HARD_I2C         1               /* To enable I2C support        */
 276 #undef  CONFIG_SYS_I2C_SOFT                     /* I2C bit-banged */
 277 #define CONFIG_SYS_I2C_SPEED            400000          /* I2C speed and slave address  */
 278 #define CONFIG_SYS_I2C_SLAVE            0x7F
 279
 280 #ifdef CONFIG_SYS_I2C_SOFT
 281 #error "Soft I2C is not configured properly.  Please review!"
 282 #define CONFIG_SYS_I2C
 283 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
 284 #define CONFIG_SYS_I2C_SOFT_SLAVE       0x7F
 285 #define I2C_PORT                3               /* Port A=0, B=1, C=2, D=3 */
 286 #define I2C_ACTIVE              (iop->pdir |=  0x00010000)
 287 #define I2C_TRISTATE            (iop->pdir &= ~0x00010000)
 288 #define I2C_READ                ((iop->pdat & 0x00010000) != 0)
 289 #define I2C_SDA(bit)            if(bit) iop->pdat |=  0x00010000; \
 290                                 else    iop->pdat &= ~0x00010000
 291 #define I2C_SCL(bit)            if(bit) iop->pdat |=  0x00020000; \
 292                                 else    iop->pdat &= ~0x00020000
 293 #define I2C_DELAY               udelay(5)       /* 1/4 I2C clock duration */
 294 #endif /* CONFIG_SYS_I2C_SOFT */
 295
 296 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57            /* EEPROM IS24C02               */
 297 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1               /* Bytes of address             */
 298 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 299 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 300
 301 #define CONFIG_SYS_FLASH_BANKS          { FLASH_BASE0_PRELIM }
 302
 303 /*-----------------------------------------------------------------------
 304  * Definitions for initial stack pointer and data area (in DPRAM)
 305  */
 306
 307 /*
 308  * NS16550 Configuration
 309  */
 310 #define CONFIG_SYS_NS16550
 311 #define CONFIG_SYS_NS16550_SERIAL
 312
 313 #define CONFIG_SYS_NS16550_REG_SIZE     1
 314
 315 #define CONFIG_SYS_NS16550_CLK          7372800
 316
 317 #define CONFIG_SYS_NS16550_COM1 0xFF080000
 318 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_NS16550_COM1 + 8)
 319 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_NS16550_COM1 + 16)
 320 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_NS16550_COM1 + 24)
 321
 322 /*
 323  * Low Level Configuration Settings
 324  * (address mappings, register initial values, etc.)
 325  * You should know what you are doing if you make changes here.
 326  */
 327
 328 #define CONFIG_SYS_CLK_FREQ  33333333   /* external frequency to pll */
 329 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
 330
 331 #define CONFIG_SYS_DLL_EXTEND           0x00
 332 #define CONFIG_SYS_PCI_HOLD_DEL 0x20
 333
 334 #define CONFIG_SYS_ROMNAL       15      /* rom/flash next access time */
 335 #define CONFIG_SYS_ROMFAL       31      /* rom/flash access time */
 336
 337 #define CONFIG_SYS_REFINT       430     /* # of clocks between CBR refresh cycles */
 338
 339 #define CONFIG_SYS_DBUS_SIZE2   1       /* set for 8-bit RCS1, clear for 32,64 */
 340
 341 /* the following are for SDRAM only*/
 342 #define CONFIG_SYS_BSTOPRE      121     /* Burst To Precharge, sets open page interval */
 343 #define CONFIG_SYS_REFREC       8       /* Refresh to activate interval         */
 344 #define CONFIG_SYS_RDLAT        4       /* data latency from read command       */
 345 #define CONFIG_SYS_PRETOACT     3       /* Precharge to activate interval       */
 346 #define CONFIG_SYS_ACTTOPRE     5       /* Activate to Precharge interval       */
 347 #define CONFIG_SYS_ACTORW               3       /* Activate to R/W                      */
 348 #define CONFIG_SYS_SDMODE_CAS_LAT       3       /* SDMODE CAS latency                   */
 349 #define CONFIG_SYS_SDMODE_WRAP          0       /* SDMODE wrap type                     */
 350 #if 0
 351 #define CONFIG_SYS_SDMODE_BURSTLEN      2       /* OBSOLETE!  SDMODE Burst length 2=4, 3=8              */
 352 #endif
 353
 354 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
 355 #define CONFIG_SYS_EXTROM 1
 356 #define CONFIG_SYS_REGDIMM 0
 357
 358
 359 /* memory bank settings*/
 360 /*
 361  * only bits 20-29 are actually used from these vales to set the
 362  * start/end address the upper two bits will be 0, and the lower 20
 363  * bits will be set to 0x00000 for a start address, or 0xfffff for an
 364  * end address
 365  */
 366 #define CONFIG_SYS_BANK0_START          0x00000000
 367 #define CONFIG_SYS_BANK0_END            (0x4000000 - 1)
 368 #define CONFIG_SYS_BANK0_ENABLE 1
 369 #define CONFIG_SYS_BANK1_START          0x04000000
 370 #define CONFIG_SYS_BANK1_END            (0x8000000 - 1)
 371 #define CONFIG_SYS_BANK1_ENABLE 1
 372 #define CONFIG_SYS_BANK2_START          0x3ff00000
 373 #define CONFIG_SYS_BANK2_END            0x3fffffff
 374 #define CONFIG_SYS_BANK2_ENABLE 0
 375 #define CONFIG_SYS_BANK3_START          0x3ff00000
 376 #define CONFIG_SYS_BANK3_END            0x3fffffff
 377 #define CONFIG_SYS_BANK3_ENABLE 0
 378 #define CONFIG_SYS_BANK4_START          0x00000000
 379 #define CONFIG_SYS_BANK4_END            0x00000000
 380 #define CONFIG_SYS_BANK4_ENABLE 0
 381 #define CONFIG_SYS_BANK5_START          0x00000000
 382 #define CONFIG_SYS_BANK5_END            0x00000000
 383 #define CONFIG_SYS_BANK5_ENABLE 0
 384 #define CONFIG_SYS_BANK6_START          0x00000000
 385 #define CONFIG_SYS_BANK6_END            0x00000000
 386 #define CONFIG_SYS_BANK6_ENABLE 0
 387 #define CONFIG_SYS_BANK7_START          0x00000000
 388 #define CONFIG_SYS_BANK7_END            0x00000000
 389 #define CONFIG_SYS_BANK7_ENABLE 0
 390 /*
 391  * Memory bank enable bitmask, specifying which of the banks defined above
 392  are actually present. MSB is for bank #7, LSB is for bank #0.
 393  */
 394 #define CONFIG_SYS_BANK_ENABLE          0x01
 395
 396 #define CONFIG_SYS_ODCR         0x75    /* configures line driver impedances,   */
 397                                         /* see 8240 book for bit definitions    */
 398 #define CONFIG_SYS_PGMAX                0x32    /* how long the 8240 retains the        */
 399                                         /* currently accessed page in memory    */
 400                                         /* see 8240 book for details            */
 401
 402 /* SDRAM 0 - 256MB */
 403 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 404 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 405
 406 /* stack in DCACHE @ 1GB (no backing mem) */
 407 #if defined(USE_DINK32)
 408 #define CONFIG_SYS_IBAT1L       (0x40000000 | BATL_PP_00 )
 409 #define CONFIG_SYS_IBAT1U       (0x40000000 | BATU_BL_128K )
 410 #else
 411 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 412 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 413 #endif
 414
 415 /* PCI memory */
 416 #define CONFIG_SYS_IBAT2L       (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 417 #define CONFIG_SYS_IBAT2U       (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 418
 419 /* Flash, config addrs, etc */
 420 #define CONFIG_SYS_IBAT3L       (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 421 #define CONFIG_SYS_IBAT3U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 422
 423 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 424 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 425 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 426 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 427 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 428 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 429 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 430 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 431
 432 /*
 433  * For booting Linux, the board info and command line data
 434  * have to be in the first 8 MB of memory, since this is
 435  * the maximum mapped by the Linux kernel during initialization.
 436  */
 437 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 438 /*-----------------------------------------------------------------------
 439  * FLASH organization
 440  */
 441 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 442 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 443
 444 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 445 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 446
 447 /*-----------------------------------------------------------------------
 448  * Cache Configuration
 449  */
 450 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8240 CPU                      */
 451 #if defined(CONFIG_CMD_KGDB)
 452 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 453 #endif
 454
 455 /* values according to the manual */
 456
 457 #define CONFIG_DRAM_50MHZ       1
 458 #define CONFIG_SDRAM_50MHZ
 459
 460 #define CONFIG_DISK_SPINUP_TIME 1000000
 461
 462 #endif  /* __CONFIG_H */