include/configs/delta.h

   1 /*
   2  * Configuation settings for the Delta board.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #ifndef __CONFIG_H
  24 #define __CONFIG_H
  25
  26 /*
  27  * High Level Configuration Options
  28  * (easy to change)
  29  */
  30 #define CONFIG_CPU_MONAHANS     1       /* Intel Monahan CPU    */
  31 #define CONFIG_DELTA            1       /* Delta board       */
  32
  33 /* #define CONFIG_LCD           1 */
  34 #ifdef CONFIG_LCD
  35 #define CONFIG_SHARP_LM8V31
  36 #endif
  37 /* #define CONFIG_MMC           1 */
  38 #define BOARD_LATE_INIT         1
  39
  40 #undef CONFIG_SKIP_RELOCATE_UBOOT
  41 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
  42
  43 /*
  44  * Size of malloc() pool
  45  */
  46 #define CFG_MALLOC_LEN      (CFG_ENV_SIZE + 256*1024)
  47 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
  48
  49 /*
  50  * Hardware drivers
  51  */
  52 #undef TURN_ON_ETHERNET
  53 #ifdef TURN_ON_ETHERNET
  54 # define CONFIG_DRIVER_SMC91111 1
  55 # define CONFIG_SMC91111_BASE   0x14000300
  56 # define CONFIG_SMC91111_EXT_PHY
  57 # define CONFIG_SMC_USE_32_BIT
  58 # undef CONFIG_SMC_USE_IOFUNCS          /* just for use with the kernel */
  59 #endif
  60
  61 #define CONFIG_HARD_I2C         1       /* required for DA9030 access */
  62 #define CFG_I2C_SPEED           400000  /* I2C speed */
  63 #define CFG_I2C_SLAVE           1       /* I2C controllers address */
  64 #define DA9030_I2C_ADDR         0x49    /* I2C address of DA9030 */
  65 #define CFG_DA9030_EXTON_DELAY  100000  /* wait x us after DA9030 reset via EXTON */
  66 #define CFG_I2C_INIT_BOARD      1
  67 /* #define CONFIG_HW_WATCHDOG   1       /\* Required for hitting the DA9030 WD *\/ */
  68
  69 #define DELTA_CHECK_KEYBD       1       /* check for keys pressed during boot */
  70 #define CONFIG_PREBOOT          "\0"
  71
  72 #ifdef DELTA_CHECK_KEYBD
  73 # define KEYBD_DATALEN          4       /* we have four keys */
  74 # define KEYBD_KP_DKIN0         0x1     /* vol+ */
  75 # define KEYBD_KP_DKIN1         0x2     /* vol- */
  76 # define KEYBD_KP_DKIN2         0x3     /* multi */
  77 # define KEYBD_KP_DKIN5         0x4     /* SWKEY_GN */
  78 #endif /* DELTA_CHECK_KEYBD */
  79
  80 /*
  81  * select serial console configuration
  82  */
  83 #define CONFIG_FFUART           1
  84
  85 /* allow to overwrite serial and ethaddr */
  86 #define CONFIG_ENV_OVERWRITE
  87
  88 #define CONFIG_BAUDRATE         115200
  89
  90
  91 /*
  92  * BOOTP options
  93  */
  94 #define CONFIG_BOOTP_BOOTFILESIZE
  95 #define CONFIG_BOOTP_BOOTPATH
  96 #define CONFIG_BOOTP_GATEWAY
  97 #define CONFIG_BOOTP_HOSTNAME
  98
  99
 100 /*
 101  * Command line configuration.
 102  */
 103 #include <config_cmd_default.h>
 104
 105 #ifdef TURN_ON_ETHERNET
 106
 107 #define CONFIG_CMD_PING
 108
 109 #else
 110
 111 #define CONFIG_CMD_ENV
 112 #define CONFIG_CMD_NAND
 113 #define CONFIG_CMD_I2C
 114
 115 #undef CONFIG_CMD_NET
 116 #undef CONFIG_CMD_FLASH
 117 #undef CONFIG_CMD_IMLS
 118
 119 #endif
 120
 121
 122 #define CONFIG_BOOTDELAY        -1
 123 #define CONFIG_ETHADDR          08:00:3e:26:0a:5b
 124 #define CONFIG_NETMASK          255.255.0.0
 125 #define CONFIG_IPADDR           192.168.0.21
 126 #define CONFIG_SERVERIP         192.168.0.250
 127 #define CONFIG_BOOTCOMMAND      "bootm 80000"
 128 #define CONFIG_BOOTARGS         "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
 129 #define CONFIG_CMDLINE_TAG
 130 #define CONFIG_TIMESTAMP
 131
 132 #if defined(CONFIG_CMD_KGDB)
 133 #define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
 134 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
 135 #endif
 136
 137 /*
 138  * Miscellaneous configurable options
 139  */
 140 #define CFG_HUSH_PARSER         1
 141 #define CFG_PROMPT_HUSH_PS2     "> "
 142
 143 #define CFG_LONGHELP                            /* undef to save memory         */
 144 #ifdef CFG_HUSH_PARSER
 145 #define CFG_PROMPT              "$ "            /* Monitor Command Prompt */
 146 #else
 147 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt */
 148 #endif
 149 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 150 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 151 #define CFG_MAXARGS             16              /* max number of command args   */
 152 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 153 #define CFG_DEVICE_NULLDEV      1
 154
 155 #define CFG_MEMTEST_START       0x80400000      /* memtest works on     */
 156 #define CFG_MEMTEST_END         0x80800000      /* 4 ... 8 MB in DRAM   */
 157
 158 #undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
 159
 160 #define CFG_LOAD_ADDR   (CFG_DRAM_BASE + 0x8000) /* default load address */
 161
 162 #define CFG_HZ                  3250000         /* incrementer freq: 3.25 MHz */
 163
 164 /* Monahans Core Frequency */
 165 #define CFG_MONAHANS_RUN_MODE_OSC_RATIO         16 /* valid values: 8, 16, 24, 31 */
 166 #define CFG_MONAHANS_TURBO_RUN_MODE_RATIO       1  /* valid values: 1, 2 */
 167
 168
 169                                                 /* valid baudrates */
 170 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 171
 172 /* #define CFG_MMC_BASE         0xF0000000 */
 173
 174 /*
 175  * Stack sizes
 176  *
 177  * The stack sizes are set up in start.S using the settings below
 178  */
 179 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 180 #ifdef CONFIG_USE_IRQ
 181 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 182 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 183 #endif
 184
 185 /*
 186  * Physical Memory Map
 187  */
 188 #define CONFIG_NR_DRAM_BANKS    4          /* we have 2 banks of DRAM */
 189 #define PHYS_SDRAM_1            0x80000000 /* SDRAM Bank #1 */
 190 #define PHYS_SDRAM_1_SIZE       0x1000000  /* 64 MB */
 191 #define PHYS_SDRAM_2            0x81000000 /* SDRAM Bank #2 */
 192 #define PHYS_SDRAM_2_SIZE       0x1000000  /* 64 MB */
 193 #define PHYS_SDRAM_3            0x82000000 /* SDRAM Bank #3 */
 194 #define PHYS_SDRAM_3_SIZE       0x1000000  /* 64 MB */
 195 #define PHYS_SDRAM_4            0x83000000 /* SDRAM Bank #4 */
 196 #define PHYS_SDRAM_4_SIZE       0x1000000  /* 64 MB */
 197
 198 #define CFG_DRAM_BASE           0x80000000 /* at CS0 */
 199 #define CFG_DRAM_SIZE           0x04000000 /* 64 MB Ram */
 200
 201 #undef CFG_SKIP_DRAM_SCRUB
 202
 203 /*
 204  * NAND Flash
 205  */
 206 #undef CFG_NAND_LEGACY
 207
 208 #define CFG_NAND0_BASE          0x0 /* 0x43100040 */ /* 0x10000000 */
 209 #undef CFG_NAND1_BASE
 210
 211 #define CFG_NAND_BASE_LIST      { CFG_NAND0_BASE }
 212 #define CFG_MAX_NAND_DEVICE     1       /* Max number of NAND devices */
 213
 214 /* nand timeout values */
 215 #define CFG_NAND_PROG_ERASE_TO  3000
 216 #define CFG_NAND_OTHER_TO       100
 217 #define CFG_NAND_SENDCMD_RETRY  3
 218 #undef NAND_ALLOW_ERASE_ALL     /* Allow erasing bad blocks - don't use */
 219
 220 /* NAND Timing Parameters (in ns) */
 221 #define NAND_TIMING_tCH         10
 222 #define NAND_TIMING_tCS         0
 223 #define NAND_TIMING_tWH         20
 224 #define NAND_TIMING_tWP         40
 225
 226 #define NAND_TIMING_tRH         20
 227 #define NAND_TIMING_tRP         40
 228
 229 #define NAND_TIMING_tR          11123
 230 #define NAND_TIMING_tWHR        100
 231 #define NAND_TIMING_tAR         10
 232
 233 /* NAND debugging */
 234 #define CFG_DFC_DEBUG1 /* usefull */
 235 #undef CFG_DFC_DEBUG2  /* noisy */
 236 #undef CFG_DFC_DEBUG3  /* extremly noisy  */
 237
 238 #define CONFIG_MTD_DEBUG
 239 #define CONFIG_MTD_DEBUG_VERBOSE 1
 240
 241 #define ADDR_COLUMN             1
 242 #define ADDR_PAGE               2
 243 #define ADDR_COLUMN_PAGE        3
 244
 245 #define NAND_ChipID_UNKNOWN     0x00
 246 #define NAND_MAX_FLOORS         1
 247 #define NAND_MAX_CHIPS          1
 248
 249 #define CFG_NO_FLASH            1
 250
 251 #define CFG_ENV_IS_IN_NAND      1
 252 #define CFG_ENV_OFFSET          0x40000
 253 #define CFG_ENV_OFFSET_REDUND   0x44000
 254 #define CFG_ENV_SIZE            0x4000
 255
 256 #endif  /* __CONFIG_H */