include/configs/dig297.h

   1 /*
   2  * (C) Copyright 2011 Comelit Group SpA
   3  * Luca Ceresoli <luca.ceresoli@comelit.it>
   4  *
   5  * Based on omap3_beagle.h:
   6  * (C) Copyright 2006-2008
   7  * Texas Instruments.
   8  * Richard Woodruff <r-woodruff2@ti.com>
   9  * Syed Mohammed Khasim <x0khasim@ti.com>
  10  *
  11  * Configuration settings for the Comelit DIG297 board.
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31
  32 #ifndef __CONFIG_H
  33 #define __CONFIG_H
  34
  35 /*
  36  * High Level Configuration Options
  37  */
  38 #define CONFIG_OMAP             /* in a TI OMAP core */
  39 #define CONFIG_OMAP34XX         /* which is a 34XX */
  40 #define CONFIG_OMAP3430         /* which is in a 3430 */
  41
  42 #define CONFIG_SYS_TEXT_BASE    0x80008000
  43
  44 #define CONFIG_SDRC     /* The chip has SDRC controller */
  45
  46 #include <asm/arch/cpu.h>               /* get chip and board defs */
  47 #include <asm/arch/omap3.h>
  48
  49 /*
  50  * Display CPU and Board information
  51  */
  52 #define CONFIG_DISPLAY_CPUINFO
  53 #define CONFIG_DISPLAY_BOARDINFO
  54
  55 /* Clock Defines */
  56 #define V_OSCK                  26000000        /* Clock output from T2 */
  57 #define V_SCLK                  (V_OSCK >> 1)
  58
  59 #undef CONFIG_USE_IRQ                           /* no support for IRQs */
  60 #define CONFIG_MISC_INIT_R
  61
  62 #define CONFIG_CMDLINE_TAG                      /* enable passing of ATAGs */
  63 #define CONFIG_SETUP_MEMORY_TAGS
  64 #define CONFIG_INITRD_TAG
  65 #define CONFIG_REVISION_TAG
  66
  67 /*
  68  * Size of malloc() pool
  69  */
  70 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB */
  71                                                 /* Sector */
  72 #define CONFIG_SYS_MALLOC_LEN           (1024 << 10) /* UBI needs >= 512 kB */
  73
  74 /*
  75  * Hardware drivers
  76  */
  77
  78 /*
  79  * NS16550 Configuration
  80  */
  81 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  82
  83 #define CONFIG_SYS_NS16550
  84 #define CONFIG_SYS_NS16550_SERIAL
  85 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  86 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  87
  88 /*
  89  * select serial console configuration: UART3 (ttyO2)
  90  */
  91 #define CONFIG_CONS_INDEX               3
  92 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  93 #define CONFIG_SERIAL3                  3
  94
  95 /* allow to overwrite serial and ethaddr */
  96 #define CONFIG_ENV_OVERWRITE
  97 #define CONFIG_BAUDRATE                 115200
  98 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  99                                         115200}
 100 #define CONFIG_MMC
 101 #define CONFIG_OMAP3_MMC
 102 #define CONFIG_DOS_PARTITION
 103
 104 /* DDR - I use Micron DDR */
 105 #define CONFIG_OMAP3_MICRON_DDR
 106
 107 /* library portions to compile in */
 108 #define CONFIG_RBTREE
 109 #define CONFIG_MTD_PARTITIONS
 110 #define CONFIG_LZO
 111
 112 /* commands to include */
 113 #include <config_cmd_default.h>
 114
 115 #define CONFIG_CMD_FAT          /* FAT support                  */
 116 #define CONFIG_CMD_UBI          /* UBI Support                  */
 117 #define CONFIG_CMD_UBIFS        /* UBIFS Support                */
 118 #define CONFIG_CMD_MTDPARTS     /* Enable MTD parts commands    */
 119 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
 120 #define MTDIDS_DEFAULT          "nand0=omap2-nand.0"
 121 #define MTDPARTS_DEFAULT        "mtdparts=omap2-nand.0:896k(uboot),"\
 122                                 "128k(uboot-env),3m(kernel),252m(ubi)"
 123
 124 #define CONFIG_CMD_I2C          /* I2C serial bus support       */
 125 #define CONFIG_CMD_MMC          /* MMC support                  */
 126 #define CONFIG_CMD_NAND         /* NAND support                 */
 127
 128 #undef CONFIG_CMD_FLASH         /* flinfo, erase, protect       */
 129 #undef CONFIG_CMD_FPGA          /* FPGA configuration Support   */
 130 #undef CONFIG_CMD_IMI           /* iminfo                       */
 131 #undef CONFIG_CMD_IMLS          /* List all found images        */
 132 #define CONFIG_CMD_NET          /* bootp, tftpboot, rarpboot    */
 133 #undef CONFIG_CMD_NFS           /* NFS support                  */
 134
 135 #define CONFIG_SYS_NO_FLASH
 136 #define CONFIG_HARD_I2C
 137 #define CONFIG_SYS_I2C_SPEED            100000
 138 #define CONFIG_SYS_I2C_SLAVE            1
 139 #define CONFIG_SYS_I2C_BUS              0
 140 #define CONFIG_SYS_I2C_BUS_SELECT       1
 141 #define CONFIG_DRIVER_OMAP34XX_I2C      1
 142
 143 /*
 144  * TWL4030
 145  */
 146 #define CONFIG_TWL4030_POWER
 147 #define CONFIG_TWL4030_LED
 148
 149 /*
 150  * Board NAND Info.
 151  */
 152 #define CONFIG_NAND_OMAP_GPMC
 153 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 154                                                         /* to access nand */
 155 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 156                                                         /* to access nand at */
 157                                                         /* CS0 */
 158 #define GPMC_NAND_ECC_LP_x16_LAYOUT
 159
 160 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 161
 162 #if defined(CONFIG_CMD_NET)
 163 /*
 164  * SMSC9220 Ethernet
 165  */
 166
 167 #define CONFIG_NET_MULTI
 168 #define CONFIG_SMC911X
 169 #define CONFIG_SMC911X_32_BIT
 170 #define CONFIG_SMC911X_BASE     0x2C000000
 171
 172 #endif /* (CONFIG_CMD_NET) */
 173
 174 /* Environment information */
 175 #define CONFIG_BOOTDELAY                1
 176
 177 #define CONFIG_EXTRA_ENV_SETTINGS \
 178         "loadaddr=0x82000000\0" \
 179         "console=ttyO2,115200n8\0" \
 180         "mtdids=" MTDIDS_DEFAULT "\0" \
 181         "mtdparts=" MTDPARTS_DEFAULT "\0" \
 182         "partition=nand0,3\0"\
 183         "mmcroot=/dev/mmcblk0p2 rw\0" \
 184         "mmcrootfstype=ext3 rootwait\0" \
 185         "nandroot=ubi0:rootfs ro\0" \
 186         "nandrootfstype=ubifs\0" \
 187         "nfspath=/srv/nfs\0" \
 188         "tftpfilename=uImage\0" \
 189         "gatewayip=0.0.0.0\0" \
 190         "mmcargs=setenv bootargs console=${console} " \
 191                 "${mtdparts} " \
 192                 "root=${mmcroot} " \
 193                 "rootfstype=${mmcrootfstype} " \
 194                 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
 195                         "${netmask}:${hostname}::off\0" \
 196         "nandargs=setenv bootargs console=${console} " \
 197                 "${mtdparts} " \
 198                 "ubi.mtd=3 " \
 199                 "root=${nandroot} " \
 200                 "rootfstype=${nandrootfstype} " \
 201                 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
 202                         "${netmask}:${hostname}::off\0" \
 203         "netargs=setenv bootargs console=${console} " \
 204                 "${mtdparts} " \
 205                 "root=/dev/nfs rw " \
 206                 "nfsroot=${serverip}:${nfspath} " \
 207                 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
 208                         "${netmask}:${hostname}::off\0" \
 209         "mmcboot=echo Booting from mmc ...; " \
 210                 "run mmcargs; " \
 211                 "bootm ${loadaddr}\0" \
 212         "nandboot=echo Booting from nand ...; " \
 213                 "run nandargs; " \
 214                 "nand read ${loadaddr} 100000 300000; " \
 215                 "bootm ${loadaddr}\0" \
 216         "netboot=echo Booting from network ...; " \
 217                 "run netargs; " \
 218                 "tftp ${loadaddr} ${serverip}:${tftpfilename}; " \
 219                 "bootm ${loadaddr}\0" \
 220         "resetenv=nand erase e0000 20000\0"\
 221
 222 #define CONFIG_BOOTCOMMAND \
 223         "run nandboot"
 224
 225 #define CONFIG_AUTO_COMPLETE
 226 /*
 227  * Miscellaneous configurable options
 228  */
 229 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 230 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
 231 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 232 #define CONFIG_SYS_PROMPT               "DIG297# "
 233 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 234 /* Print Buffer Size */
 235 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 236                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 237 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 238 /* Boot Argument Buffer Size */
 239 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 240
 241 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)     /* memtest */
 242                                                                 /* works on */
 243 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 244                                         0x01F00000) /* 31MB */
 245
 246 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
 247                                                         /* load address */
 248
 249 /*
 250  * OMAP3 has 12 GP timers, they can be driven by the system clock
 251  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 252  * This rate is divided by a local divisor.
 253  */
 254 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 255 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 256 #define CONFIG_SYS_HZ                   1000
 257
 258 /*-----------------------------------------------------------------------
 259  * Stack sizes
 260  *
 261  * The stack sizes are set up in start.S using the settings below
 262  */
 263 #define CONFIG_STACKSIZE        (128 << 10)     /* regular stack 128 KiB */
 264 #ifdef CONFIG_USE_IRQ
 265 #define CONFIG_STACKSIZE_IRQ    (4 << 10)       /* IRQ stack 4 KiB */
 266 #define CONFIG_STACKSIZE_FIQ    (4 << 10)       /* FIQ stack 4 KiB */
 267 #endif
 268
 269 /*-----------------------------------------------------------------------
 270  * Physical Memory Map
 271  */
 272 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
 273 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 274 #define PHYS_SDRAM_1_SIZE       (32 << 20)      /* at least 32 MiB */
 275 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 276
 277 /* SDRAM Bank Allocation method */
 278 #define SDRC_R_B_C              1
 279
 280 /*-----------------------------------------------------------------------
 281  * FLASH and environment organization
 282  */
 283
 284 /* **** PISMO SUPPORT *** */
 285
 286 /* Configure the PISMO */
 287 #define PISMO1_NAND_SIZE                GPMC_SIZE_128M
 288
 289 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 290
 291 #define CONFIG_SYS_FLASH_BASE           boot_flash_base
 292
 293 /* Monitor at start of flash */
 294 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 295
 296 #define CONFIG_ENV_IS_IN_NAND
 297 #define SMNAND_ENV_OFFSET               0x0E0000 /* environment starts here */
 298
 299 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)     /* 128 KiB */
 300 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 301 #define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 302
 303 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 304 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 305 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 306 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
 307                                          CONFIG_SYS_INIT_RAM_SIZE - \
 308                                          GENERATED_GBL_DATA_SIZE)
 309
 310 #endif /* __CONFIG_H */