include/configs/eb_cpu5282.h

   1 /*
   2  * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
   3  *
   4  * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef _CONFIG_EB_CPU5282_H_
  10 #define _CONFIG_EB_CPU5282_H_
  11
  12 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
  13
  14 /*----------------------------------------------------------------------*
  15  * High Level Configuration Options (easy to change)                    *
  16  *----------------------------------------------------------------------*/
  17
  18 #define CONFIG_MISC_INIT_R
  19
  20 #define CONFIG_MCFUART
  21 #define CONFIG_SYS_UART_PORT            (0)
  22
  23 #undef  CONFIG_MONITOR_IS_IN_RAM                /* starts uboot direct */
  24
  25 #define CONFIG_BOOTCOMMAND "printenv"
  26
  27 /*----------------------------------------------------------------------*
  28  * Options                                                              *
  29  *----------------------------------------------------------------------*/
  30
  31 #define CONFIG_BOOT_RETRY_TIME  -1
  32 #define CONFIG_RESET_TO_RETRY
  33 #define CONFIG_SPLASH_SCREEN
  34
  35 #define CONFIG_HW_WATCHDOG
  36
  37 #define STATUS_LED_ACTIVE               0
  38
  39 /*----------------------------------------------------------------------*
  40  * Configuration for environment                                        *
  41  * Environment is in the second sector of the first 256k of flash       *
  42  *----------------------------------------------------------------------*/
  43
  44 #define CONFIG_ENV_ADDR         0xFF040000
  45 #define CONFIG_ENV_SECT_SIZE    0x00020000
  46
  47 /*
  48  * BOOTP options
  49  */
  50 #define CONFIG_BOOTP_BOOTFILESIZE
  51
  52 /*
  53  * Command line configuration.
  54  */
  55
  56 #define CONFIG_MCFTMR
  57
  58 #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size      */
  59 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  60
  61 #define CONFIG_SYS_LOAD_ADDR            0x20000
  62
  63 #define CONFIG_SYS_MEMTEST_START        0x100000
  64 #define CONFIG_SYS_MEMTEST_END          0x400000
  65 /*#define CONFIG_SYS_DRAM_TEST          1 */
  66 #undef CONFIG_SYS_DRAM_TEST
  67
  68 /*----------------------------------------------------------------------*
  69  * Clock and PLL Configuration                                          *
  70  *----------------------------------------------------------------------*/
  71 #define CONFIG_SYS_CLK                  80000000      /* 8MHz * 8 */
  72
  73 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
  74
  75 #define CONFIG_SYS_MFD          0x02    /* PLL Multiplication Factor Devider */
  76 #define CONFIG_SYS_RFD          0x00    /* PLL Reduce Frecuency Devider */
  77
  78 /*----------------------------------------------------------------------*
  79  * Network                                                              *
  80  *----------------------------------------------------------------------*/
  81
  82 #define CONFIG_MCFFEC
  83 #define CONFIG_MII                      1
  84 #define CONFIG_MII_INIT                 1
  85 #define CONFIG_SYS_DISCOVER_PHY
  86 #define CONFIG_SYS_RX_ETH_BUFFER        8
  87 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  88
  89 #define CONFIG_SYS_FEC0_PINMUX          0
  90 #define CONFIG_SYS_FEC0_MIIBASE         CONFIG_SYS_FEC0_IOBASE
  91 #define MCFFEC_TOUT_LOOP                50000
  92
  93 #define CONFIG_OVERWRITE_ETHADDR_ONCE
  94
  95 /*-------------------------------------------------------------------------
  96  * Low Level Configuration Settings
  97  * (address mappings, register initial values, etc.)
  98  * You should know what you are doing if you make changes here.
  99  *-----------------------------------------------------------------------*/
 100
 101 #define CONFIG_SYS_MBAR                 0x40000000
 102
 103 /*-----------------------------------------------------------------------
 104  * Definitions for initial stack pointer and data area (in DPRAM)
 105  *-----------------------------------------------------------------------*/
 106
 107 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 108 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
 109 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 110         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 111 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 112
 113 /*-----------------------------------------------------------------------
 114  * Start addresses for the final memory configuration
 115  * (Set up by the startup code)
 116  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 117  */
 118 #define CONFIG_SYS_SDRAM_BASE0          0x00000000
 119 #define CONFIG_SYS_SDRAM_SIZE0          16      /* SDRAM size in MB */
 120
 121 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_SDRAM_BASE0
 122 #define CONFIG_SYS_SDRAM_SIZE           CONFIG_SYS_SDRAM_SIZE0
 123
 124 #define CONFIG_SYS_MONITOR_LEN          0x20000
 125 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 126 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 127
 128 /*
 129  * For booting Linux, the board info and command line data
 130  * have to be in the first 8 MB of memory, since this is
 131  * the maximum mapped by the Linux kernel during initialization ??
 132  */
 133 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20) /* Initial Memory map for Linux */
 134
 135 /*-----------------------------------------------------------------------
 136  * FLASH organization
 137  */
 138 #define CONFIG_FLASH_SHOW_PROGRESS      45
 139
 140 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 141 #define CONFIG_SYS_INT_FLASH_BASE       0xF0000000
 142 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
 143
 144 #define CONFIG_SYS_MAX_FLASH_SECT       128
 145 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 146 #define CONFIG_SYS_FLASH_ERASE_TOUT     10000000
 147 #define CONFIG_SYS_FLASH_PROTECTION
 148
 149 #define CONFIG_SYS_FLASH_CFI
 150 #define CONFIG_FLASH_CFI_DRIVER
 151 #define CONFIG_SYS_FLASH_SIZE           16*1024*1024
 152 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 153
 154 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 155
 156 /*-----------------------------------------------------------------------
 157  * Cache Configuration
 158  */
 159 #define CONFIG_SYS_CACHELINE_SIZE       16
 160
 161 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 162                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 163 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 164                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 165 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 166 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 167                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 168                                          CF_ACR_EN | CF_ACR_SM_ALL)
 169 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 170                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 171                                          CF_CACR_EUSP)
 172
 173 /*-----------------------------------------------------------------------
 174  * Memory bank definitions
 175  */
 176
 177 #define CONFIG_SYS_CS0_BASE             0xFF000000
 178 #define CONFIG_SYS_CS0_CTRL             0x00001980
 179 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 180
 181 #define CONFIG_SYS_CS2_BASE             0xE0000000
 182 #define CONFIG_SYS_CS2_CTRL             0x00001980
 183 #define CONFIG_SYS_CS2_MASK             0x000F0001
 184
 185 #define CONFIG_SYS_CS3_BASE             0xE0100000
 186 #define CONFIG_SYS_CS3_CTRL             0x00001980
 187 #define CONFIG_SYS_CS3_MASK             0x000F0001
 188
 189 /*-----------------------------------------------------------------------
 190  * Port configuration
 191  */
 192 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 193 #define CONFIG_SYS_PADDR                0x0000000
 194 #define CONFIG_SYS_PADAT                0x0000000
 195
 196 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 197 #define CONFIG_SYS_PBDDR                0x0000000
 198 #define CONFIG_SYS_PBDAT                0x0000000
 199
 200 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 201 #define CONFIG_SYS_PCDDR                0x0000000
 202 #define CONFIG_SYS_PCDAT                0x0000000
 203
 204 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 205 #define CONFIG_SYS_PCDDR                0x0000000
 206 #define CONFIG_SYS_PCDAT                0x0000000
 207
 208 #define CONFIG_SYS_PASPAR               0x0F0F
 209 #define CONFIG_SYS_PEHLPAR              0xC0
 210 #define CONFIG_SYS_PUAPAR               0x0F
 211 #define CONFIG_SYS_DDRUA                0x05
 212 #define CONFIG_SYS_PJPAR                0xFF
 213
 214 /*-----------------------------------------------------------------------
 215  * I2C
 216  */
 217
 218 #define CONFIG_SYS_I2C
 219 #define CONFIG_SYS_I2C_FSL
 220
 221 #define CONFIG_SYS_FSL_I2C_OFFSET       0x00000300
 222 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
 223
 224 #define CONFIG_SYS_FSL_I2C_SPEED        100000
 225 #define CONFIG_SYS_FSL_I2C_SLAVE        0
 226
 227 #ifdef CONFIG_CMD_DATE
 228 #define CONFIG_RTC_DS1338
 229 #define CONFIG_I2C_RTC_ADDR             0x68
 230 #endif
 231
 232 /*-----------------------------------------------------------------------
 233  * VIDEO configuration
 234  */
 235
 236 #ifdef CONFIG_VIDEO
 237 #define CONFIG_VIDEO_VCXK                       1
 238
 239 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN       2
 240 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED          1
 241 #define CONFIG_SYS_VCXK_BASE                    CONFIG_SYS_CS2_BASE
 242
 243 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT        MCFGPTB_GPTPORT
 244 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR         MCFGPTB_GPTDDR
 245 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN         0x0001
 246
 247 #define CONFIG_SYS_VCXK_ENABLE_PORT             MCFGPTB_GPTPORT
 248 #define CONFIG_SYS_VCXK_ENABLE_DDR              MCFGPTB_GPTDDR
 249 #define CONFIG_SYS_VCXK_ENABLE_PIN              0x0002
 250
 251 #define CONFIG_SYS_VCXK_REQUEST_PORT            MCFGPTB_GPTPORT
 252 #define CONFIG_SYS_VCXK_REQUEST_DDR             MCFGPTB_GPTDDR
 253 #define CONFIG_SYS_VCXK_REQUEST_PIN             0x0004
 254
 255 #define CONFIG_SYS_VCXK_INVERT_PORT             MCFGPIO_PORTE
 256 #define CONFIG_SYS_VCXK_INVERT_DDR              MCFGPIO_DDRE
 257 #define CONFIG_SYS_VCXK_INVERT_PIN              MCFGPIO_PORT2
 258
 259 #endif /* CONFIG_VIDEO */
 260 #endif  /* _CONFIG_M5282EVB_H */
 261 /*---------------------------------------------------------------------*/