include/configs/eb_cpux9k2.h

   1 /*
   2  * (C) Copyright 2008-2009
   3  * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
   4  * Jens Scharsig <esw@bus-elektronik.de>
   5  *
   6  * Configuation settings for the EB+CPUx9K2 board.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef _CONFIG_EB_CPUx9K2_H_
  12 #define _CONFIG_EB_CPUx9K2_H_
  13
  14 /*--------------------------------------------------------------------------*/
  15
  16 #define CONFIG_AT91RM9200               /* It's an Atmel AT91RM9200 SoC */
  17 #define CONFIG_EB_CPUX9K2               /* on an EP+CPUX9K2 Board       */
  18 #define USE_920T_MMU
  19
  20 #define CONFIG_VERSION_VARIABLE
  21 #define CONFIG_IDENT_STRING     " on EB+CPUx9K2"
  22
  23 #include <asm/hardware.h>       /* needed for port definitions */
  24
  25 #define CONFIG_MISC_INIT_R
  26 #define CONFIG_BOARD_EARLY_INIT_F
  27
  28 #define MACH_TYPE_EB_CPUX9K2            1977
  29 #define CONFIG_MACH_TYPE                MACH_TYPE_EB_CPUX9K2
  30
  31 #define CONFIG_SYS_CACHELINE_SIZE       32
  32 #define CONFIG_SYS_DCACHE_OFF
  33
  34 /*--------------------------------------------------------------------------*/
  35 #ifndef CONFIG_RAMBOOT
  36 #define CONFIG_SYS_TEXT_BASE            0x00000000
  37 #else
  38 #define CONFIG_SKIP_LOWLEVEL_INIT
  39 #define CONFIG_SYS_TEXT_BASE            0x21800000
  40 #endif
  41 #define CONFIG_SYS_LOAD_ADDR            0x21000000  /* default load address */
  42 #define CONFIG_STANDALONE_LOAD_ADDR     0x21000000
  43
  44 #define CONFIG_BOOT_RETRY_TIME          30
  45 #define CONFIG_CMDLINE_EDITING
  46
  47 #define CONFIG_SYS_CBSIZE       512             /* Console I/O Buffer Size */
  48 #define CONFIG_SYS_MAXARGS      32              /* max number of command args */
  49 #define CONFIG_SYS_PBSIZE       \
  50         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  51
  52 /*
  53  * ARM asynchronous clock
  54  */
  55
  56 #define AT91C_MAIN_CLOCK        179404800       /* from 12.288 MHz * 73 / 5 */
  57 #define AT91C_MASTER_CLOCK      (AT91C_MAIN_CLOCK / 3)
  58 #define CONFIG_SYS_HZ_CLOCK     (AT91C_MASTER_CLOCK / 2)
  59
  60 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock */
  61
  62 #define CONFIG_CMDLINE_TAG              1
  63 #define CONFIG_SETUP_MEMORY_TAGS        1
  64 #define CONFIG_INITRD_TAG               1
  65
  66 #define CONFIG_SYS_USE_MAIN_OSCILLATOR  1
  67 /* flash */
  68 #define CONFIG_SYS_EBI_CFGR_VAL         0x00000000
  69 #define CONFIG_SYS_SMC_CSR0_VAL         0x00003284 /* 16bit, 2 TDF, 4 WS */
  70
  71 /* clocks */
  72 #define CONFIG_SYS_PLLAR_VAL            0x20483E05 /* 179.4048 MHz for PCK */
  73 #define CONFIG_SYS_PLLBR_VAL            0x104C3E0A /* 47.3088 MHz (for USB) */
  74 #define CONFIG_SYS_MCKR_VAL             0x00000202 /* PCK/3 = MCK Clock */
  75
  76 /*
  77  * Size of malloc() pool
  78  */
  79
  80 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
  81
  82 /*
  83  * sdram
  84  */
  85
  86 #define CONFIG_NR_DRAM_BANKS            1
  87
  88 #define CONFIG_SYS_SDRAM_BASE           0x20000000
  89 #define CONFIG_SYS_SDRAM_SIZE           0x04000000  /* 64 megs */
  90 #define CONFIG_SYS_INIT_SP_ADDR         0x00204000  /* use internal SRAM */
  91
  92 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
  93 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
  94                                         CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \
  95                                         CONFIG_SYS_MALLOC_LEN)
  96
  97 #define CONFIG_SYS_PIOC_ASR_VAL         0xFFFF0000 /* PIOC as D16/D31 */
  98 #define CONFIG_SYS_PIOC_BSR_VAL         0x00000000
  99 #define CONFIG_SYS_PIOC_PDR_VAL         0xFFFF0000
 100 #define CONFIG_SYS_EBI_CSA_VAL          0x00000002 /* CS1=SDRAM */
 101 #define CONFIG_SYS_SDRC_CR_VAL          0x2188c159 /* set up the SDRAM */
 102 #define CONFIG_SYS_SDRAM                0x20000000 /* address of the SDRAM */
 103 #define CONFIG_SYS_SDRAM1               0x20000080 /* address of the SDRAM */
 104 #define CONFIG_SYS_SDRAM_VAL            0x00000000 /* value written to SDRAM */
 105 #define CONFIG_SYS_SDRC_MR_VAL          0x00000002 /* Precharge All */
 106 #define CONFIG_SYS_SDRC_MR_VAL1         0x00000004 /* refresh */
 107 #define CONFIG_SYS_SDRC_MR_VAL2         0x00000003 /* Load Mode Register */
 108 #define CONFIG_SYS_SDRC_MR_VAL3         0x00000000 /* Normal Mode */
 109 #define CONFIG_SYS_SDRC_TR_VAL          0x000002E0 /* Write refresh rate */
 110
 111 /*
 112  * Command line configuration
 113  */
 114 #define CONFIG_CMD_BMP
 115 #define CONFIG_CMD_DATE
 116 #define CONFIG_CMD_DHCP
 117 #define CONFIG_CMD_I2C
 118 #define CONFIG_CMD_MII
 119 #define CONFIG_CMD_NAND
 120 #define CONFIG_CMD_PING
 121 #define CONFIG_I2C_CMD_TREE
 122 #define CONFIG_CMD_USB
 123 #define CONFIG_CMD_FAT
 124 #define CONFIG_CMD_UBI
 125 #define CONFIG_CMD_MTDPARTS
 126 #define CONFIG_CMD_UBIFS
 127
 128 #define CONFIG_SYS_LONGHELP
 129
 130 /*
 131  * MTD defines
 132  */
 133
 134 #define CONFIG_FLASH_CFI_MTD
 135 #define CONFIG_MTD_DEVICE
 136 #define CONFIG_MTD_PARTITIONS
 137 #define CONFIG_RBTREE
 138 #define CONFIG_LZO
 139
 140 #define MTDIDS_DEFAULT          "nor0=physmap-flash.0,nand0=atmel_nand"
 141 #define MTDPARTS_DEFAULT        "mtdparts="                             \
 142                                         "physmap-flash.0:"              \
 143                                                 "512k(U-Boot),"         \
 144                                                 "128k(Env),"            \
 145                                                 "128k(Splash),"         \
 146                                                 "4M(Kernel),"           \
 147                                                 "384k(MiniFS),"         \
 148                                                 "-(FS)"                 \
 149                                         ";"                             \
 150                                         "atmel_nand:"                   \
 151                                                 "1M(emergency),"        \
 152                                                 "-(data)"
 153 /*
 154  * Hardware drivers
 155  */
 156 #define CONFIG_USB_ATMEL
 157 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 158 #define CONFIG_USB_OHCI_NEW
 159 #define CONFIG_AT91C_PQFP_UHPBUG
 160 #define CONFIG_USB_STORAGE
 161 #define CONFIG_DOS_PARTITION
 162 #define CONFIG_ISO_PARTITION
 163 #define CONFIG_EFI_PARTITION
 164
 165 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      1
 166 #define CONFIG_SYS_USB_OHCI_CPU_INIT
 167 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00300000
 168 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91rm9200"
 169
 170 /*
 171  * UART/CONSOLE
 172  */
 173
 174 #define CONFIG_BAUDRATE 115200
 175 #define CONFIG_ATMEL_USART
 176 #define CONFIG_USART_BASE       ATMEL_BASE_DBGU
 177 #define CONFIG_USART_ID         0/* ignored in arm */
 178
 179 /*
 180  * network
 181  */
 182
 183 #define CONFIG_NET_RETRY_COUNT          10
 184 #define CONFIG_RESET_PHY_R              1
 185
 186 #define CONFIG_DRIVER_AT91EMAC          1
 187 #define CONFIG_DRIVER_AT91EMAC_QUIET    1
 188 #define CONFIG_SYS_RX_ETH_BUFFER        8
 189 #define CONFIG_MII                      1
 190
 191 /*
 192  * BOOTP options
 193  */
 194 #define CONFIG_BOOTP_BOOTFILESIZE
 195 #define CONFIG_BOOTP_BOOTPATH
 196 #define CONFIG_BOOTP_GATEWAY
 197 #define CONFIG_BOOTP_HOSTNAME
 198
 199 /*
 200  * I2C-Bus
 201  */
 202
 203 #define CONFIG_SYS_I2C
 204 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
 205 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
 206 #define CONFIG_SYS_I2C_SOFT_SLAVE       0
 207
 208 /* Software  I2C driver configuration */
 209
 210 #define AT91_PIN_SDA                    (1<<25)         /* AT91C_PIO_PA25 */
 211 #define AT91_PIN_SCL                    (1<<26)         /* AT91C_PIO_PA26 */
 212
 213 #define CONFIG_SYS_I2C_INIT_BOARD
 214
 215 #define I2C_INIT        i2c_init_board();
 216 #define I2C_ACTIVE      writel(ATMEL_PMX_AA_TWD, &pio->pioa.mddr);
 217 #define I2C_TRISTATE    writel(ATMEL_PMX_AA_TWD, &pio->pioa.mder);
 218 #define I2C_READ        ((readl(&pio->pioa.pdsr) & ATMEL_PMX_AA_TWD) != 0)
 219 #define I2C_SDA(bit)                                            \
 220         if (bit)                                                \
 221                 writel(ATMEL_PMX_AA_TWD, &pio->pioa.sodr);      \
 222         else                                                    \
 223                 writel(ATMEL_PMX_AA_TWD, &pio->pioa.codr);
 224 #define I2C_SCL(bit)                                            \
 225         if (bit)                                                \
 226                 writel(ATMEL_PMX_AA_TWCK, &pio->pioa.sodr);     \
 227         else                                                    \
 228                 writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr);
 229
 230 #define I2C_DELAY       udelay(2500000/CONFIG_SYS_I2C_SOFT_SPEED)
 231
 232 /* I2C-RTC */
 233
 234 #ifdef CONFIG_CMD_DATE
 235 #define CONFIG_RTC_DS1338
 236 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 237 #endif
 238
 239 /* EEPROM */
 240
 241 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 242 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 243
 244 /* FLASH organization */
 245
 246 /*  NOR-FLASH */
 247 #define CONFIG_FLASH_SHOW_PROGRESS      45
 248
 249 #define CONFIG_FLASH_CFI_DRIVER 1
 250
 251 #define PHYS_FLASH_1                    0x10000000
 252 #define PHYS_FLASH_SIZE                 0x01000000  /* 16 megs main flash */
 253 #define CONFIG_SYS_FLASH_CFI            1
 254 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 255
 256 #define CONFIG_SYS_FLASH_PROTECTION     1
 257 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 258 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 259 #define CONFIG_SYS_MAX_FLASH_SECT       512
 260 #define CONFIG_SYS_FLASH_ERASE_TOUT     6000
 261 #define CONFIG_SYS_FLASH_WRITE_TOUT     2000
 262
 263 /* NAND */
 264
 265 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 266 #define CONFIG_SYS_NAND_BASE            0x40000000
 267 #define CONFIG_SYS_NAND_DBW_8           1
 268
 269 /* Status LED's */
 270
 271 #define CONFIG_STATUS_LED               1
 272 #define CONFIG_BOARD_SPECIFIC_LED       1
 273
 274 #define STATUS_LED_BOOT                 1
 275 #define STATUS_LED_ACTIVE               0
 276
 277 #define STATUS_LED_BIT                  1       /* AT91C_PIO_PD0 green LED */
 278 #define STATUS_LED_PERIOD               (CONFIG_SYS_HZ / 2)
 279 #define STATUS_LED_STATE                STATUS_LED_OFF          /* BLINKING */
 280 #define STATUS_LED_BIT1                 2       /* AT91C_PIO_PD1  red LED */
 281 #define STATUS_LED_STATE1               STATUS_LED_ON           /* BLINKING */
 282 #define STATUS_LED_PERIOD1              (CONFIG_SYS_HZ / 4)
 283
 284 #define CONFIG_VIDEO                    1
 285
 286 /* Options */
 287
 288 #ifdef CONFIG_VIDEO
 289
 290 #define CONFIG_VIDEO_VCXK                       1
 291
 292 #define CONFIG_SPLASH_SCREEN                    1
 293
 294 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN       4
 295 #define CONFIG_SYS_VCXK_BASE    0x30000000
 296
 297 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN         (1<<3)
 298 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT        piob
 299 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR         odr
 300
 301 #define CONFIG_SYS_VCXK_ENABLE_PIN              (1<<5)
 302 #define CONFIG_SYS_VCXK_ENABLE_PORT             piob
 303 #define CONFIG_SYS_VCXK_ENABLE_DDR              oer
 304
 305 #define CONFIG_SYS_VCXK_REQUEST_PIN             (1<<2)
 306 #define CONFIG_SYS_VCXK_REQUEST_PORT            piob
 307 #define CONFIG_SYS_VCXK_REQUEST_DDR             oer
 308
 309 #define CONFIG_SYS_VCXK_INVERT_PIN              (1<<4)
 310 #define CONFIG_SYS_VCXK_INVERT_PORT             piob
 311 #define CONFIG_SYS_VCXK_INVERT_DDR              oer
 312
 313 #define CONFIG_SYS_VCXK_RESET_PIN               (1<<6)
 314 #define CONFIG_SYS_VCXK_RESET_PORT              piob
 315 #define CONFIG_SYS_VCXK_RESET_DDR               oer
 316
 317 #endif  /* CONFIG_VIDEO */
 318
 319 /* Environment */
 320
 321 #define CONFIG_BOOTDELAY                5
 322
 323 #define CONFIG_ENV_IS_IN_FLASH          1
 324 #define CONFIG_ENV_ADDR                 (PHYS_FLASH_1 + 0x80000)
 325 #define CONFIG_ENV_SIZE                 0x20000 /* sectors are 128K here */
 326
 327 #define CONFIG_BAUDRATE                 115200
 328
 329 #define CONFIG_BOOTCOMMAND              "run nfsboot"
 330
 331 #define CONFIG_NFSBOOTCOMMAND                                           \
 332                 "dhcp $(copy_addr) uImage_cpux9k2;"                     \
 333                 "run bootargsdefaults;"                                 \
 334                 "set bootargs $(bootargs) boot=nfs "                    \
 335                 ";echo $(bootargs)"                                     \
 336         ";bootm"
 337
 338 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 339         "displaywidth=256\0"                                            \
 340         "displayheight=512\0"                                           \
 341         "displaybsteps=1023\0"                                          \
 342         "ubootaddr=10000000\0"                                          \
 343         "splashimage=100A0000\0"                                        \
 344         "kerneladdr=100C0000\0"                                         \
 345         "kernelsize=00400000\0"                                         \
 346         "rootfsaddr=10520000\0"                                         \
 347         "copy_addr=21200000\0"                                          \
 348         "rootfssize=00AE0000\0"                                         \
 349         "mtdids=" MTDIDS_DEFAULT "\0"                                   \
 350         "mtdparts=" MTDPARTS_DEFAULT "\0"                               \
 351         "bootargsdefaults=set bootargs "                                \
 352                 "console=ttyS0,115200 "                                 \
 353                 "video=vcxk_fb:xres:${displaywidth},"                   \
 354                         "yres:${displayheight},"                        \
 355                         "bres:${displaybsteps} "                        \
 356                 "mem=62M "                                              \
 357                 "panic=10 "                                             \
 358                 "uboot=\\\"${ver}\\\" "                                 \
 359                 "\0"                                                    \
 360         "update_kernel=protect off $(kerneladdr) +$(kernelsize);"       \
 361                 "dhcp $(copy_addr) uImage_cpux9k2;"                     \
 362                 "erase $(kerneladdr) +$(kernelsize);"                   \
 363                 "cp.b $(fileaddr) $(kerneladdr) $(filesize);"           \
 364                 "protect on $(kerneladdr) +$(kernelsize)"               \
 365                 "\0"                                                    \
 366         "update_root=protect off $(rootfsaddr) +$(rootfssize);"         \
 367                 "dhcp $(copy_addr) rfs;"                                \
 368                 "erase $(rootfsaddr) +$(rootfssize);"                   \
 369                 "cp.b $(fileaddr) $(rootfsaddr) $(filesize);"           \
 370                 "\0"                                                    \
 371         "update_uboot=protect off 10000000 1007FFFF;"                   \
 372                 "dhcp $(copy_addr) u-boot_eb_cpux9k2;"                  \
 373                 "erase 10000000 1007FFFF;"                              \
 374                 "cp.b $(fileaddr) $(ubootaddr) $(filesize);"            \
 375                 "protect on 10000000 1007FFFF;reset\0"                  \
 376         "update_splash=protect off $(splashimage) +20000;"              \
 377                 "dhcp $(copy_addr) splash_eb_cpux9k2.bmp;"              \
 378                 "erase $(splashimage) +20000;"                          \
 379                 "cp.b $(fileaddr) $(splashimage) $(filesize);"          \
 380                 "protect on $(splashimage) +20000;reset\0"              \
 381         "emergency=run bootargsdefaults;"                               \
 382                 "set bootargs $(bootargs) root=initramfs boot=emergency " \
 383                 ";bootm $(kerneladdr)\0"                                \
 384         "netemergency=run bootargsdefaults;"                            \
 385                 "dhcp $(copy_addr) uImage_cpux9k2;"                     \
 386                 "set bootargs $(bootargs) root=initramfs boot=emergency " \
 387                 ";bootm $(copy_addr)\0"                                 \
 388         "norboot=run bootargsdefaults;"                                 \
 389                 "set bootargs $(bootargs) root=initramfs boot=local "   \
 390                 ";bootm $(kerneladdr)\0"                                \
 391         "nandboot=run bootargsdefaults;"                                \
 392                 "set bootargs $(bootargs) root=initramfs boot=nand "    \
 393                 ";bootm $(kerneladdr)\0"                                \
 394         " "
 395
 396 /*--------------------------------------------------------------------------*/
 397
 398 #endif
 399
 400 /* EOF */