include/configs/ecovec.h

   1 /*
   2  * Configuation settings for the Renesas Solutions ECOVEC board
   3  *
   4  * Copyright (C) 2009 - 2011 Renesas Solutions Corp.
   5  * Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com>
   6  * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __ECOVEC_H
  12 #define __ECOVEC_H
  13
  14 /*
  15  *  Address      Interface        BusWidth
  16  *-----------------------------------------
  17  *  0x0000_0000  U-Boot           16bit
  18  *  0x0004_0000  Linux romImage   16bit
  19  *  0x0014_0000  MTD for Linux    16bit
  20  *  0x0400_0000  Internal I/O     16/32bit
  21  *  0x0800_0000  DRAM             32bit
  22  *  0x1800_0000  MFI              16bit
  23  */
  24
  25 #define CONFIG_CPU_SH7724       1
  26 #define CONFIG_ECOVEC           1
  27
  28 #define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000
  29 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000
  30
  31 #define CONFIG_CMD_SDRAM
  32
  33 #define CONFIG_BOOTARGS         "console=ttySC0,115200"
  34
  35 #define CONFIG_DISPLAY_BOARDINFO
  36 #undef  CONFIG_SHOW_BOOT_PROGRESS
  37
  38 /* I2C */
  39 #define CONFIG_SYS_I2C
  40 #define CONFIG_SYS_I2C_SH
  41 #define CONFIG_SYS_I2C_SLAVE    0x7F
  42 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 2
  43 #define CONFIG_SYS_I2C_SH_BASE0 0xA4470000
  44 #define CONFIG_SYS_I2C_SH_SPEED0        100000
  45 #define CONFIG_SYS_I2C_SH_BASE1 0xA4750000
  46 #define CONFIG_SYS_I2C_SH_SPEED1        100000
  47 #define CONFIG_SH_I2C_DATA_HIGH 4
  48 #define CONFIG_SH_I2C_DATA_LOW  5
  49 #define CONFIG_SH_I2C_CLOCK     41666666
  50
  51 /* Ether */
  52 #define CONFIG_SH_ETHER 1
  53 #define CONFIG_SH_ETHER_USE_PORT (0)
  54 #define CONFIG_SH_ETHER_PHY_ADDR (0x1f)
  55 #define CONFIG_PHY_SMSC 1
  56 #define CONFIG_BITBANGMII
  57 #define CONFIG_BITBANGMII_MULTI
  58 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
  59
  60 /* USB / R8A66597 */
  61 #define CONFIG_USB_R8A66597_HCD
  62 #define CONFIG_R8A66597_BASE_ADDR   0xA4D80000
  63 #define CONFIG_R8A66597_XTAL        0x0000  /* 12MHz */
  64 #define CONFIG_R8A66597_LDRV        0x8000  /* 3.3V */
  65 #define CONFIG_R8A66597_ENDIAN      0x0000  /* little */
  66 #define CONFIG_SUPERH_ON_CHIP_R8A66597
  67
  68 /* undef to save memory */
  69 #define CONFIG_SYS_LONGHELP
  70 /* Monitor Command Prompt */
  71 /* Buffer size for input from the Console */
  72 #define CONFIG_SYS_CBSIZE               256
  73 /* Buffer size for Console output */
  74 #define CONFIG_SYS_PBSIZE               256
  75 /* max args accepted for monitor commands */
  76 #define CONFIG_SYS_MAXARGS              16
  77 /* Buffer size for Boot Arguments passed to kernel */
  78 #define CONFIG_SYS_BARGSIZE     512
  79 /* List of legal baudrate settings for this board */
  80 #define CONFIG_SYS_BAUDRATE_TABLE       { 115200 }
  81
  82 /* SCIF */
  83 #define CONFIG_SCIF             1
  84 #define CONFIG_CONS_SCIF0       1
  85
  86 /* Suppress display of console information at boot */
  87
  88 /* SDRAM */
  89 #define CONFIG_SYS_SDRAM_BASE   (0x88000000)
  90 #define CONFIG_SYS_SDRAM_SIZE   (256 * 1024 * 1024)
  91 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
  92
  93 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
  94 #define CONFIG_SYS_MEMTEST_END   (CONFIG_SYS_MEMTEST_START + 200 * 1024 * 1024)
  95 /* Enable alternate, more extensive, memory test */
  96 #undef  CONFIG_SYS_ALT_MEMTEST
  97 /* Scratch address used by the alternate memory test */
  98 #undef  CONFIG_SYS_MEMTEST_SCRATCH
  99
 100 /* Enable temporary baudrate change while serial download */
 101 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE
 102
 103 /* FLASH */
 104 #define CONFIG_FLASH_CFI_DRIVER 1
 105 #define CONFIG_SYS_FLASH_CFI
 106 #undef  CONFIG_SYS_FLASH_QUIET_TEST
 107 #define CONFIG_SYS_FLASH_EMPTY_INFO
 108 #define CONFIG_SYS_FLASH_BASE   (0xA0000000)
 109 #define CONFIG_SYS_MAX_FLASH_SECT       512
 110
 111 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */
 112 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 113 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 114
 115 /* Timeout for Flash erase operations (in ms) */
 116 #define CONFIG_SYS_FLASH_ERASE_TOUT     (3 * 1000)
 117 /* Timeout for Flash write operations (in ms) */
 118 #define CONFIG_SYS_FLASH_WRITE_TOUT     (3 * 1000)
 119 /* Timeout for Flash set sector lock bit operations (in ms) */
 120 #define CONFIG_SYS_FLASH_LOCK_TOUT      (3 * 1000)
 121 /* Timeout for Flash clear lock bit operations (in ms) */
 122 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (3 * 1000)
 123
 124 /*
 125  * Use hardware flash sectors protection instead
 126  * of U-Boot software protection
 127  */
 128 #undef  CONFIG_SYS_FLASH_PROTECTION
 129 #undef  CONFIG_SYS_DIRECT_FLASH_TFTP
 130
 131 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
 132 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
 133 /* Monitor size */
 134 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)
 135 /* Size of DRAM reserved for malloc() use */
 136 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)
 137 #define CONFIG_SYS_BOOTMAPSZ    (8 * 1024 * 1024)
 138
 139 /* ENV setting */
 140 #define CONFIG_ENV_OVERWRITE    1
 141 #define CONFIG_ENV_SECT_SIZE    (128 * 1024)
 142 #define CONFIG_ENV_SIZE         (CONFIG_ENV_SECT_SIZE)
 143 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 144 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
 145 #define CONFIG_ENV_OFFSET       (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
 146 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SECT_SIZE)
 147
 148 /* Board Clock */
 149 #define CONFIG_SYS_CLK_FREQ 41666666
 150 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 151 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 152 #define CONFIG_SYS_TMU_CLK_DIV      4
 153
 154 #endif  /* __ECOVEC_H */