include/configs/ep8248.h

   1 /*
   2  * Copyright (C) 2004 Arabella Software Ltd.
   3  * Yuli Barcohen <yuli@arabellasw.com>
   4  *
   5  * U-Boot configuration for Embedded Planet EP8248 boards.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 #define CONFIG_MPC8248
  30 #define CPU_ID_STR              "MPC8248"
  31
  32 #define CONFIG_EP8248                   /* Embedded Planet EP8248 board */
  33
  34 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  35
  36 /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
  37 #define CONFIG_ENV_OVERWRITE
  38
  39 /*
  40  * Select serial console configuration
  41  *
  42  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  43  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  44  * for SCC).
  45  */
  46 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
  47 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
  48 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
  49 #define CONFIG_CONS_INDEX       1       /* SMC1 is used for console  */
  50
  51 #define CONFIG_SYS_BCSR         0xFA000000
  52
  53 /*
  54  * Select ethernet configuration
  55  *
  56  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
  57  * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
  58  * SCC, 1-3 for FCC)
  59  *
  60  * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
  61  * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
  62  * must be unset.
  63  */
  64 #undef  CONFIG_ETHER_ON_SCC             /* Ethernet is not on SCC */
  65 #define CONFIG_ETHER_ON_FCC             /* Ethernet is on FCC     */
  66 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
  67
  68 #ifdef CONFIG_ETHER_ON_FCC
  69
  70 #define CONFIG_ETHER_INDEX      1       /* FCC1 is used for Ethernet */
  71
  72 #if   (CONFIG_ETHER_INDEX == 1)
  73
  74 /* - Rx clock is CLK10
  75  * - Tx clock is CLK11
  76  * - BDs/buffers on 60x bus
  77  * - Full duplex
  78  */
  79 #define CONFIG_SYS_CMXFCR_MASK  (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
  80 #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)
  81 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
  82 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
  83
  84 #elif (CONFIG_ETHER_INDEX == 2)
  85
  86 /* - Rx clock is CLK13
  87  * - Tx clock is CLK14
  88  * - BDs/buffers on 60x bus
  89  * - Full duplex
  90  */
  91 #define CONFIG_SYS_CMXFCR_MASK  (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  92 #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  93 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
  94 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
  95
  96 #endif /* CONFIG_ETHER_INDEX */
  97
  98 #define CONFIG_MII                      /* MII PHY management        */
  99 #define CONFIG_BITBANGMII               /* Bit-banged MDIO interface */
 100 /*
 101  * GPIO pins used for bit-banged MII communications
 102  */
 103 #define MDIO_PORT               0       /* Not used - implemented in BCSR */
 104 #define MDIO_ACTIVE             (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
 105 #define MDIO_TRISTATE           (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
 106 #define MDIO_READ               (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
 107
 108 #define MDIO(bit)               if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
 109                                 else    *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE
 110
 111 #define MDC(bit)                if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
 112                                 else    *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD
 113
 114 #define MIIDELAY                udelay(1)
 115
 116 #endif /* CONFIG_ETHER_ON_FCC */
 117
 118 #ifndef CONFIG_8260_CLKIN
 119 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
 120 #endif
 121
 122 #define CONFIG_BAUDRATE         38400
 123
 124
 125 /*
 126  * BOOTP options
 127  */
 128 #define CONFIG_BOOTP_BOOTFILESIZE
 129 #define CONFIG_BOOTP_BOOTPATH
 130 #define CONFIG_BOOTP_GATEWAY
 131 #define CONFIG_BOOTP_HOSTNAME
 132
 133
 134 /*
 135  * Command line configuration.
 136  */
 137 #include <config_cmd_default.h>
 138
 139 #define CONFIG_CMD_DHCP
 140 #define CONFIG_CMD_ECHO
 141 #define CONFIG_CMD_I2C
 142 #define CONFIG_CMD_IMMAP
 143 #define CONFIG_CMD_MII
 144 #define CONFIG_CMD_PING
 145
 146
 147 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 148 #define CONFIG_BOOTCOMMAND      "bootm FF860000"        /* autoboot command */
 149 #define CONFIG_BOOTARGS         "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"
 150
 151 #if defined(CONFIG_CMD_KGDB)
 152 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 153 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 154 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 155 #define CONFIG_KGDB_INDEX       1       /* which serial channel for kgdb */
 156 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 157 #endif
 158
 159 #define CONFIG_BZIP2    /* include support for bzip2 compressed images */
 160 #undef  CONFIG_WATCHDOG                 /* disable platform specific watchdog */
 161
 162 /*
 163  * Miscellaneous configurable options
 164  */
 165 #define CONFIG_SYS_HUSH_PARSER
 166 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 167 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 168 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
 169 #if defined(CONFIG_CMD_KGDB)
 170 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 171 #else
 172 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 173 #endif
 174 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size  */
 175 #define CONFIG_SYS_MAXARGS              16              /* max number of command args */
 176 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size  */
 177
 178 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 179 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 180
 181 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 182
 183 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 184
 185 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 186
 187 #define CONFIG_SYS_FLASH_BASE           0xFF800000
 188 #define CONFIG_SYS_FLASH_CFI
 189 #define CONFIG_FLASH_CFI_DRIVER
 190 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks       */
 191 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max num of sects on one chip */
 192
 193 #define CONFIG_SYS_DIRECT_FLASH_TFTP
 194
 195 #if defined(CONFIG_CMD_JFFS2)
 196 #define CONFIG_SYS_JFFS2_FIRST_BANK     0
 197 #define CONFIG_SYS_JFFS2_NUM_BANKS      CONFIG_SYS_MAX_FLASH_BANKS
 198 #define CONFIG_SYS_JFFS2_FIRST_SECTOR  0
 199 #define CONFIG_SYS_JFFS2_LAST_SECTOR   62
 200 #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
 201 #define CONFIG_SYS_JFFS_CUSTOM_PART
 202 #endif
 203
 204 #if defined(CONFIG_CMD_I2C)
 205 #define CONFIG_HARD_I2C         1       /* To enable I2C support        */
 206 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed                    */
 207 #define CONFIG_SYS_I2C_SLAVE            0x7F    /* I2C slave address            */
 208 #endif
 209
 210 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
 211 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 212 #define CONFIG_SYS_RAMBOOT
 213 #endif
 214
 215 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256KB for Monitor */
 216
 217 #define CONFIG_ENV_IS_IN_FLASH
 218
 219 #ifdef CONFIG_ENV_IS_IN_FLASH
 220 #define CONFIG_ENV_SECT_SIZE    0x20000
 221 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 222 #endif /* CONFIG_ENV_IS_IN_FLASH */
 223
 224 #define CONFIG_SYS_DEFAULT_IMMR 0x00010000
 225
 226 #define CONFIG_SYS_IMMR         0xF0000000
 227
 228 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 229 #define CONFIG_SYS_INIT_RAM_END 0x2000  /* End of used area in DPRAM    */
 230 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* size in bytes reserved for initial data */
 231 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 232 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 233
 234 /* Hard reset configuration word */
 235 #define CONFIG_SYS_HRCW_MASTER          0x0C40025A /* Not used - provided by FPGA */
 236 /* No slaves */
 237 #define CONFIG_SYS_HRCW_SLAVE1          0
 238 #define CONFIG_SYS_HRCW_SLAVE2          0
 239 #define CONFIG_SYS_HRCW_SLAVE3          0
 240 #define CONFIG_SYS_HRCW_SLAVE4          0
 241 #define CONFIG_SYS_HRCW_SLAVE5          0
 242 #define CONFIG_SYS_HRCW_SLAVE6          0
 243 #define CONFIG_SYS_HRCW_SLAVE7          0
 244
 245 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
 246 #define BOOTFLAG_WARM           0x02    /* Software reboot                  */
 247
 248 #define CONFIG_SYS_MALLOC_LEN           (4096 << 10)    /* Reserve 4 MB for malloc()    */
 249 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 250
 251 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPUs */
 252 #if defined(CONFIG_CMD_KGDB)
 253 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 254 #endif
 255
 256 #define CONFIG_SYS_HID0_INIT            0
 257 #define CONFIG_SYS_HID0_FINAL           (HID0_ICE | HID0_IFEM | HID0_ABE)
 258
 259 #define CONFIG_SYS_HID2         0
 260
 261 #define CONFIG_SYS_SIUMCR               0x01240200
 262 #define CONFIG_SYS_SYPCR                0xFFFF0683
 263 #define CONFIG_SYS_BCR                  0x00000000
 264 #define CONFIG_SYS_SCCR         SCCR_DFBRG01
 265
 266 #define CONFIG_SYS_RMR                  RMR_CSRE
 267 #define CONFIG_SYS_TMCNTSC              (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 268 #define CONFIG_SYS_PISCR                (PISCR_PS|PISCR_PTF|PISCR_PTE)
 269 #define CONFIG_SYS_RCCR         0
 270
 271 #define CONFIG_SYS_MPTPR                0x1300
 272 #define CONFIG_SYS_PSDMR                0x82672522
 273 #define CONFIG_SYS_PSRT         0x4B
 274
 275 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 276 #define CONFIG_SYS_SDRAM_BR             (CONFIG_SYS_SDRAM_BASE | 0x00001841)
 277 #define CONFIG_SYS_SDRAM_OR             0xFF0030C0
 278
 279 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | 0x00001801)
 280 #define CONFIG_SYS_OR0_PRELIM           0xFF8008C2
 281 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_BCSR | 0x00000801)
 282 #define CONFIG_SYS_OR2_PRELIM           0xFFF00864
 283
 284 #define CONFIG_SYS_RESET_ADDRESS        0xC0000000
 285
 286 #endif /* __CONFIG_H */