include/configs/ep8260.h

   1 /*
   2  * (C) Copyright 2002
   3  * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
   4  *
   5  * This file is based on similar values for other boards found in other
   6  * U-Boot config files, and some that I found in the EP8260 manual.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * board/config.h - configuration options, board specific
  29  *
  30  * Note: my board is a "SBC 8260 H, V.1.1"
  31  *      - 64M 60x Bus SDRAM
  32  *      - 32M Local Bus SDRAM
  33  *      - 16M Flash (4 x AM29DL323DB90WDI)
  34  *      - 128k NVRAM with RTC
  35  */
  36
  37 #ifndef __CONFIG_H
  38 #define __CONFIG_H
  39
  40 /* What is the oscillator's (UX2) frequency in Hz? */
  41 #define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
  42
  43 /*-----------------------------------------------------------------------
  44  * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
  45  *-----------------------------------------------------------------------
  46  * What should MODCK_H be? It is dependent on the oscillator
  47  * frequency, MODCK[1-3], and desired CPM and core frequencies.
  48  * Here are some example values (all frequencies are in MHz):
  49  *
  50  * MODCK_H   MODCK[1-3]  Osc    CPM    Core
  51  * -------   ----------  ---    ---    ----
  52  * 0x2       0x2         33     133    133
  53  * 0x2       0x3         33     133    166
  54  * 0x2       0x4         33     133    200
  55  * 0x2       0x5         33     133    233
  56  * 0x2       0x6         33     133    266
  57  *
  58  * 0x5       0x5         66     133    133
  59  * 0x5       0x6         66     133    166
  60  * 0x5       0x7         66     133    200 *
  61  * 0x6       0x0         66     133    233
  62  * 0x6       0x1         66     133    266
  63  * 0x6       0x2         66     133    300
  64  */
  65 #define CFG_SBC_MODCK_H 0x05
  66
  67 /* Define this if you want to boot from 0x00000100. If you don't define
  68  * this, you will need to program the bootloader to 0xfff00000, and
  69  * get the hardware reset config words at 0xfe000000. The simplest
  70  * way to do that is to program the bootloader at both addresses.
  71  * It is suggested that you just let U-Boot live at 0x00000000.
  72  */
  73 /* #define CFG_SBC_BOOT_LOW 1 */        /* only for HRCW */
  74 /* #undef CFG_SBC_BOOT_LOW */
  75
  76 /* The reset command will not work as expected if the reset address does
  77  * not point to the correct address.
  78  */
  79
  80 #define CFG_RESET_ADDRESS       0xFFF00100
  81
  82 /* What should the base address of the main FLASH be and how big is
  83  * it (in MBytes)? This must contain TEXT_BASE from board/ep8260/config.mk
  84  * The main FLASH is whichever is connected to *CS0. U-Boot expects
  85  * this to be the SIMM.
  86  */
  87 #define CFG_FLASH0_BASE 0xFF000000
  88 #define CFG_FLASH0_SIZE 16
  89
  90 /* What should the base address of the secondary FLASH be and how big
  91  * is it (in Mbytes)? The secondary FLASH is whichever is connected
  92  * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
  93  * want it enabled, don't define these constants.
  94  */
  95 #define CFG_FLASH1_BASE 0
  96 #define CFG_FLASH1_SIZE 0
  97 #undef CFG_FLASH1_BASE
  98 #undef CFG_FLASH1_SIZE
  99
 100 /* What should be the base address of SDRAM DIMM (60x bus) and how big is
 101  * it (in Mbytes)?
 102 */
 103 #define CFG_SDRAM0_BASE 0x00000000
 104 #define CFG_SDRAM0_SIZE 64
 105
 106 /* define CFG_LSDRAM if you want to enable the 32M SDRAM on the
 107  * local bus (8260 local bus is NOT cacheable!)
 108 */
 109 /* #define CFG_LSDRAM */
 110 #undef CFG_LSDRAM
 111
 112 #ifdef CFG_LSDRAM
 113 /* What should be the base address of SDRAM DIMM (local bus) and how big is
 114  * it (in Mbytes)?
 115 */
 116   #define CFG_SDRAM1_BASE 0x04000000
 117   #define CFG_SDRAM1_SIZE 32
 118 #else
 119   #define CFG_SDRAM1_BASE 0
 120   #define CFG_SDRAM1_SIZE 0
 121   #undef CFG_SDRAM1_BASE
 122   #undef CFG_SDRAM1_SIZE
 123 #endif /* CFG_LSDRAM */
 124
 125 /* What should be the base address of NVRAM and how big is
 126  * it (in Bytes)
 127  */
 128 #define CFG_NVRAM_BASE_ADDR  0xFa080000
 129 #define CFG_NVRAM_SIZE       (128*1024)-16
 130
 131 /* The RTC is a Dallas DS1556
 132  */
 133 #define CONFIG_RTC_DS1556
 134
 135 /* What should be the base address of the LEDs and switch S0?
 136  * If you don't want them enabled, don't define this.
 137  */
 138 #define CFG_LED_BASE 0x00000000
 139 #undef CFG_LED_BASE
 140
 141 /*
 142  * select serial console configuration
 143  *
 144  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 145  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 146  * for SCC).
 147  *
 148  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 149  * defined elsewhere.
 150  */
 151 #define CONFIG_CONS_ON_SMC          /* define if console on SMC */
 152 #undef  CONFIG_CONS_ON_SCC          /* define if console on SCC */
 153 #undef  CONFIG_CONS_NONE            /* define if console on neither */
 154 #define CONFIG_CONS_INDEX    1      /* which SMC/SCC channel for console */
 155
 156 /*
 157  * select ethernet configuration
 158  *
 159  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 160  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 161  * for FCC)
 162  *
 163  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 164  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
 165  * from CONFIG_COMMANDS to remove support for networking.
 166  */
 167 #undef  CONFIG_ETHER_ON_SCC           /* define if ethernet on SCC    */
 168 #define CONFIG_ETHER_ON_FCC           /* define if ethernet on FCC    */
 169 #undef  CONFIG_ETHER_NONE             /* define if ethernet on neither */
 170 #define CONFIG_ETHER_INDEX      3     /* which SCC/FCC channel for ethernet */
 171
 172 #if ( CONFIG_ETHER_INDEX == 3 )
 173
 174 /*
 175  * - Rx-CLK is CLK15
 176  * - Tx-CLK is CLK16
 177  * - RAM for BD/Buffers is on the local Bus (see 28-13)
 178  * - Enable Half Duplex in FSMR
 179  */
 180 # define CFG_CMXFCR_MASK        (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
 181 # define CFG_CMXFCR_VALUE       (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
 182
 183 /*
 184  * - RAM for BD/Buffers is on the local Bus (see 28-13)
 185  */
 186 #ifdef CFG_LSDRAM
 187   #define CFG_CPMFCR_RAMTYPE    3
 188 #else /* CFG_LSDRAM */
 189   #define CFG_CPMFCR_RAMTYPE    0
 190 #endif /* CFG_LSDRAM */
 191
 192 /* - Enable Half Duplex in FSMR */
 193 /* # define CFG_FCC_PSMR                (FCC_PSMR_FDE|FCC_PSMR_LPB) */
 194 # define CFG_FCC_PSMR           0
 195
 196 #else /* CONFIG_ETHER_INDEX */
 197 # error "on EP8260 ethernet must be FCC3"
 198 #endif /* CONFIG_ETHER_INDEX */
 199
 200 /*
 201  * select i2c support configuration
 202  *
 203  * Supported configurations are {none, software, hardware} drivers.
 204  * If the software driver is chosen, there are some additional
 205  * configuration items that the driver uses to drive the port pins.
 206  */
 207 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 208 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 209 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 210 #define CFG_I2C_SLAVE           0x7F
 211
 212 /*
 213  * Software (bit-bang) I2C driver configuration
 214  */
 215 #ifdef CONFIG_SOFT_I2C
 216 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 217 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 218 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 219 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 220 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 221                         else    iop->pdat &= ~0x00010000
 222 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 223                         else    iop->pdat &= ~0x00020000
 224 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 225 #endif /* CONFIG_SOFT_I2C */
 226
 227 /* #define CONFIG_RTC_DS174x */
 228
 229 /* Define this to reserve an entire FLASH sector (256 KB) for
 230  * environment variables. Otherwise, the environment will be
 231  * put in the same sector as U-Boot, and changing variables
 232  * will erase U-Boot temporarily
 233  */
 234 #define CFG_ENV_IN_OWN_SECT
 235
 236 /* Define to allow the user to overwrite serial and ethaddr */
 237 #define CONFIG_ENV_OVERWRITE
 238
 239 /* What should the console's baud rate be? */
 240 /* #define CONFIG_BAUDRATE         57600 */
 241 #define CONFIG_BAUDRATE         115200
 242
 243 /* Ethernet MAC address */
 244 #define CONFIG_ETHADDR          00:10:EC:00:30:8C
 245
 246 #define CONFIG_IPADDR           192.168.254.130
 247 #define CONFIG_SERVERIP         192.168.254.49
 248
 249 /* Set to a positive value to delay for running BOOTCOMMAND */
 250 #define CONFIG_BOOTDELAY        -1
 251
 252 /* undef this to save memory */
 253 #define CFG_LONGHELP
 254
 255 /* Monitor Command Prompt       */
 256 #define CFG_PROMPT              "=> "
 257
 258 /* Define this variable to enable the "hush" shell (from
 259    Busybox) as command line interpreter, thus enabling
 260    powerful command line syntax like
 261    if...then...else...fi conditionals or `&&' and '||'
 262    constructs ("shell scripts").
 263    If undefined, you get the old, much simpler behaviour
 264    with a somewhat smapper memory footprint.
 265 */
 266 #define CFG_HUSH_PARSER
 267 #define CFG_PROMPT_HUSH_PS2     "> "
 268
 269 /* What U-Boot subsytems do you want enabled? */
 270 /*
 271 */
 272 #define CONFIG_COMMANDS         ( CFG_CMD_ALL     & \
 273                                   ~(    CFG_CMD_BMP     | \
 274                                         CFG_CMD_BSP     | \
 275                                         CFG_CMD_DCR     | \
 276                                         CFG_CMD_DHCP    | \
 277                                         CFG_CMD_DOC     | \
 278                                         CFG_CMD_DTT     | \
 279                                         CFG_CMD_EEPROM  | \
 280                                         CFG_CMD_EXT2    | \
 281                                         CFG_CMD_FDC     | \
 282                                         CFG_CMD_FDOS    | \
 283                                         CFG_CMD_HWFLOW  | \
 284                                         CFG_CMD_IDE     | \
 285                                         CFG_CMD_JFFS2   | \
 286                                         CFG_CMD_KGDB    | \
 287                                         CFG_CMD_MII     | \
 288                                         CFG_CMD_MMC     | \
 289                                         CFG_CMD_NAND    | \
 290                                         CFG_CMD_PCI     | \
 291                                         CFG_CMD_PCMCIA  | \
 292                                         CFG_CMD_REISER  | \
 293                                         CFG_CMD_SCSI    | \
 294                                         CFG_CMD_SPI     | \
 295                                         CFG_CMD_UNIVERSE| \
 296                                         CFG_CMD_USB     | \
 297                                         CFG_CMD_VFD     | \
 298                                         CFG_CMD_XIMG    ) )
 299
 300 /* Where do the internal registers live? */
 301 #define CFG_IMMR               0xF0000000
 302 #define CFG_DEFAULT_IMMR       0x00010000
 303
 304 /* Where do the on board registers (CS4) live? */
 305 #define CFG_REGS_BASE          0xFA000000
 306
 307 /*****************************************************************************
 308  *
 309  * You should not have to modify any of the following settings
 310  *
 311  *****************************************************************************/
 312
 313 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
 314 #define CONFIG_EP8260           11      /* on an Embedded Planet EP8260 Board, Rev. 11 */
 315
 316 #define CONFIG_BOARD_EARLY_INIT_F 1         /* Call board_early_init_f  */
 317
 318 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 319 #include <cmd_confdefs.h>
 320
 321 /*
 322  * Miscellaneous configurable options
 323  */
 324 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 325 #  define CFG_CBSIZE              1024       /* Console I/O Buffer Size      */
 326 #else
 327 #  define CFG_CBSIZE              256        /* Console I/O Buffer Size      */
 328 #endif
 329
 330 /* Print Buffer Size */
 331 #define CFG_PBSIZE        (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
 332
 333 #define CFG_MAXARGS       8            /* max number of command args   */
 334
 335 #define CFG_BARGSIZE      CFG_CBSIZE   /* Boot Argument Buffer Size    */
 336
 337 #ifdef CFG_LSDRAM
 338   #define CFG_MEMTEST_START 0x04000000   /* memtest works on  */
 339   #define CFG_MEMTEST_END   0x06000000   /* 64-96 MB in SDRAM */
 340 #else
 341   #define CFG_MEMTEST_START 0x00000000   /* memtest works on  */
 342   #define CFG_MEMTEST_END   0x02000000   /* 0-32 MB in SDRAM */
 343 #endif /* CFG_LSDRAM */
 344
 345 #define CONFIG_CLOCKS_IN_MHZ    1      /* clocks passsed to Linux in MHz */
 346
 347 #define CFG_LOAD_ADDR     0x00100000   /* default load address */
 348 #define CFG_TFTP_LOADADDR 0x00100000   /* default load address for network file downloads */
 349
 350 #define CFG_HZ            1000         /* decrementer freq: 1 ms ticks */
 351
 352 /* valid baudrates */
 353 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 354
 355 /*
 356  * Low Level Configuration Settings
 357  * (address mappings, register initial values, etc.)
 358  * You should know what you are doing if you make changes here.
 359  */
 360
 361 #define CFG_FLASH_BASE    CFG_FLASH0_BASE
 362 #define CFG_SDRAM_BASE    CFG_SDRAM0_BASE
 363
 364 /*-----------------------------------------------------------------------
 365  * Hard Reset Configuration Words
 366  */
 367
 368 #if defined(CFG_SBC_BOOT_LOW)
 369 #  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 370 #else
 371 #  define  CFG_SBC_HRCW_BOOT_FLAGS  (0x00000000)
 372 #endif /* defined(CFG_SBC_BOOT_LOW) */
 373
 374 /* get the HRCW ISB field from CFG_IMMR */
 375 /*
 376 #define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
 377                             ((CFG_IMMR & 0x01000000) >> 7)  |\
 378                             ((CFG_IMMR & 0x00100000) >> 4) )
 379
 380 #define CFG_HRCW_MASTER (HRCW_EBM                |\
 381                          HRCW_L2CPC01            |\
 382                          CFG_SBC_HRCW_IMMR       |\
 383                          HRCW_APPC10             |\
 384                          HRCW_CS10PC01           |\
 385                          HRCW_MODCK_H0101        |\
 386                          CFG_SBC_HRCW_BOOT_FLAGS)
 387 */
 388 #define CFG_HRCW_MASTER 0x10400245
 389
 390 /* no slaves */
 391 #define CFG_HRCW_SLAVE1 0
 392 #define CFG_HRCW_SLAVE2 0
 393 #define CFG_HRCW_SLAVE3 0
 394 #define CFG_HRCW_SLAVE4 0
 395 #define CFG_HRCW_SLAVE5 0
 396 #define CFG_HRCW_SLAVE6 0
 397 #define CFG_HRCW_SLAVE7 0
 398
 399 /*-----------------------------------------------------------------------
 400  * Definitions for initial stack pointer and data area (in DPRAM)
 401  */
 402 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 403 #define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
 404 #define CFG_GBL_DATA_SIZE      128     /* bytes reserved for initial data */
 405 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 406 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 407
 408 /*-----------------------------------------------------------------------
 409  * Start addresses for the final memory configuration
 410  * (Set up by the startup code)
 411  * Please note that CFG_SDRAM_BASE _must_ start at 0
 412  * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
 413  */
 414 #define CFG_MONITOR_BASE          TEXT_BASE
 415
 416
 417 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 418 #  define CFG_RAMBOOT
 419 #endif
 420
 421 #define CFG_MONITOR_LEN      (256 << 10)     /* Reserve 256 kB for Monitor   */
 422 #define CFG_MALLOC_LEN       (128 << 10)     /* Reserve 128 kB for malloc()  */
 423
 424 /*
 425  * For booting Linux, the board info and command line data
 426  * have to be in the first 8 MB of memory, since this is
 427  * the maximum mapped by the Linux kernel during initialization.
 428  */
 429 #define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 430
 431 /*-----------------------------------------------------------------------
 432  * FLASH and environment organization
 433  */
 434 #define CFG_MAX_FLASH_BANKS   1       /* max number of memory banks         */
 435 #define CFG_MAX_FLASH_SECT    71      /* max number of sectors on one chip  */
 436
 437 #define CFG_FLASH_ERASE_TOUT  8000    /* Timeout for Flash Erase (in ms)    */
 438 #define CFG_FLASH_WRITE_TOUT  1       /* Timeout for Flash Write (in ms)    */
 439
 440 #ifndef CFG_RAMBOOT
 441 #  define CFG_ENV_IS_IN_FLASH  1
 442
 443 #  ifdef CFG_ENV_IN_OWN_SECT
 444 #    define CFG_ENV_ADDR       (CFG_MONITOR_BASE + 0x40000)
 445 #    define CFG_ENV_SECT_SIZE  0x40000
 446 #  else
 447 #    define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
 448 #    define CFG_ENV_SIZE       0x1000  /* Total Size of Environment Sector */
 449 #    define CFG_ENV_SECT_SIZE  0x10000 /* see README - env sect real size */
 450 #  endif /* CFG_ENV_IN_OWN_SECT */
 451 #else
 452 #  define CFG_ENV_IS_IN_NVRAM  1
 453 #  define CFG_ENV_ADDR         (CFG_MONITOR_BASE - 0x1000)
 454 #  define CFG_ENV_SIZE         0x200
 455 #endif /* CFG_RAMBOOT */
 456
 457 /*-----------------------------------------------------------------------
 458  * Cache Configuration
 459  */
 460 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU */
 461
 462 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 463 #  define CFG_CACHELINE_SHIFT     5     /* log base 2 of the above value */
 464 #endif
 465
 466 /*-----------------------------------------------------------------------
 467  * HIDx - Hardware Implementation-dependent Registers                    2-11
 468  *-----------------------------------------------------------------------
 469  * HID0 also contains cache control - initially enable both caches and
 470  * invalidate contents, then the final state leaves only the instruction
 471  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 472  * but Soft reset does not.
 473  *
 474  * HID1 has only read-only information - nothing to set.
 475  */
 476 #define CFG_HID0_INIT   (HID0_ICE  |\
 477                          HID0_DCE  |\
 478                          HID0_ICFI |\
 479                          HID0_DCI  |\
 480                          HID0_IFEM |\
 481                          HID0_ABE)
 482 #ifdef CFG_LSDRAM
 483 /* 8260 local bus is NOT cacheable */
 484 #define CFG_HID0_FINAL  (/*HID0_ICE  |*/\
 485                          HID0_IFEM |\
 486                          HID0_ABE  |\
 487                          HID0_EMCP)
 488 #else /* !CFG_LSDRAM */
 489 #define CFG_HID0_FINAL  (HID0_ICE  |\
 490                          HID0_IFEM |\
 491                          HID0_ABE  |\
 492                          HID0_EMCP)
 493 #endif /* CFG_LSDRAM */
 494
 495 #define CFG_HID2        0
 496
 497 /*-----------------------------------------------------------------------
 498  * RMR - Reset Mode Register
 499  *-----------------------------------------------------------------------
 500  */
 501 #define CFG_RMR         0
 502
 503 /*-----------------------------------------------------------------------
 504  * BCR - Bus Configuration                                       4-25
 505  *-----------------------------------------------------------------------
 506  */
 507 /*#define CFG_BCR         (BCR_EBM   |\
 508                          BCR_PLDP  |\
 509                          BCR_EAV   |\
 510                          BCR_NPQM1)
 511 */
 512 #define CFG_BCR  0x80C08000
 513 /*-----------------------------------------------------------------------
 514  * SIUMCR - SIU Module Configuration                             4-31
 515  *-----------------------------------------------------------------------
 516  */
 517
 518 #define CFG_SIUMCR      (SIUMCR_L2CPC01 |\
 519                          SIUMCR_APPC10  |\
 520                          SIUMCR_CS10PC01)
 521
 522
 523 /*-----------------------------------------------------------------------
 524  * SYPCR - System Protection Control                            11-9
 525  * SYPCR can only be written once after reset!
 526  *-----------------------------------------------------------------------
 527  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 528  */
 529 #ifdef CFG_LSDRAM
 530 #define CFG_SYPCR       (SYPCR_SWTC |\
 531                          SYPCR_BMT  |\
 532                          SYPCR_PBME |\
 533                          SYPCR_LBME |\
 534                          SYPCR_SWP)
 535 #else
 536 #define CFG_SYPCR       (SYPCR_SWTC |\
 537                          SYPCR_BMT  |\
 538                          SYPCR_PBME |\
 539                          SYPCR_SWP)
 540 #endif
 541 /*-----------------------------------------------------------------------
 542  * TMCNTSC - Time Counter Status and Control                     4-40
 543  *-----------------------------------------------------------------------
 544  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 545  * and enable Time Counter
 546  */
 547 #define CFG_TMCNTSC     (TMCNTSC_SEC |\
 548                          TMCNTSC_ALR |\
 549                          TMCNTSC_TCF |\
 550                          TMCNTSC_TCE)
 551
 552 /*-----------------------------------------------------------------------
 553  * PISCR - Periodic Interrupt Status and Control                 4-42
 554  *-----------------------------------------------------------------------
 555  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 556  * Periodic timer
 557  */
 558 /*#define CFG_PISCR       (PISCR_PS  |\
 559                          PISCR_PTF |\
 560                          PISCR_PTE)*/
 561 #define CFG_PISCR       0
 562 /*-----------------------------------------------------------------------
 563  * SCCR - System Clock Control                                   9-8
 564  *-----------------------------------------------------------------------
 565  */
 566 #define CFG_SCCR        (SCCR_DFBRG01)
 567
 568 /*-----------------------------------------------------------------------
 569  * RCCR - RISC Controller Configuration                         13-7
 570  *-----------------------------------------------------------------------
 571  */
 572 #define CFG_RCCR        0
 573
 574 /*-----------------------------------------------------------------------
 575  * MPTPR - Memory Refresh Timer Prescale Register               10-32
 576  *-----------------------------------------------------------------------
 577  */
 578 #define CFG_MPTPR       (0x0A00 & MPTPR_PTP_MSK)
 579
 580 /*
 581  * Init Memory Controller:
 582  *
 583  * Bank Bus     Machine PortSz  Device
 584  * ---- ---     ------- ------  ------
 585  *  0   60x     GPCM    64 bit  FLASH (BGA - 16MB AMD AM29DL323DB90WDI)
 586  *  1   60x     SDRAM   64 bit  SDRAM (BGA - 64MB Micron 48LC8M16A2TG)
 587  *  2   Local   SDRAM   32 bit  SDRAM (BGA - 32MB Micron 48LC8M16A2TG)
 588  *  3   unused
 589  *  4   60x     GPCM     8 bit  Board Regs, NVRTC
 590  *  5   unused
 591  *  6   unused
 592  *  7   unused
 593  *  8   PCMCIA
 594  *  9   unused
 595  * 10   unused
 596  * 11   unused
 597 */
 598
 599 /*-----------------------------------------------------------------------
 600  * BRx - Base Register
 601  *     Ref: Section 10.3.1 on page 10-14
 602  * ORx - Option Register
 603  *     Ref: Section 10.3.2 on page 10-18
 604  *-----------------------------------------------------------------------
 605  */
 606
 607 /* Bank 0 - FLASH
 608  *
 609  */
 610 #define CFG_BR0_PRELIM  ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
 611                          BRx_PS_64                      |\
 612                          BRx_DECC_NONE                  |\
 613                          BRx_MS_GPCM_P                  |\
 614                          BRx_V)
 615
 616 #define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH0_SIZE)     |\
 617                          ORxG_CSNT                      |\
 618                          ORxG_ACS_DIV1                  |\
 619                          ORxG_SCY_6_CLK                 |\
 620                          ORxG_EHTR)
 621
 622 /* Bank 1 - SDRAM
 623  * PSDRAM
 624  */
 625 #define CFG_BR1_PRELIM  ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
 626                          BRx_PS_64                      |\
 627                          BRx_MS_SDRAM_P                 |\
 628                          BRx_V)
 629
 630 #define CFG_OR1_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE)     |\
 631                          ORxS_BPD_4                     |\
 632                          ORxS_ROWST_PBI1_A6             |\
 633                          ORxS_NUMR_12)
 634
 635 #define CFG_PSDMR       0xC34E2462
 636 #define CFG_PSRT        0x64
 637
 638
 639 #ifdef CFG_LSDRAM
 640 /* Bank 2 - SDRAM
 641  * LSDRAM
 642  */
 643
 644   #define CFG_BR2_PRELIM  ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
 645                            BRx_PS_32                      |\
 646                            BRx_MS_SDRAM_L                 |\
 647                            BRx_V)
 648
 649   #define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM1_SIZE)     |\
 650                            ORxS_BPD_4                     |\
 651                            ORxS_ROWST_PBI0_A9             |\
 652                            ORxS_NUMR_12)
 653
 654   #define CFG_LSDMR       0x416A2562
 655   #define CFG_LSRT      0x64
 656 #else
 657   #define CFG_LSRT      0x0
 658 #endif /* CFG_LSDRAM */
 659
 660 /* Bank 4 - On board registers
 661  * NVRTC and BCSR
 662  */
 663 #define CFG_BR4_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
 664                            BRx_PS_8                     |\
 665                            BRx_MS_GPCM_P                |\
 666                            BRx_V)
 667 /*
 668 #define CFG_OR4_PRELIM    (ORxG_AM_MSK                 |\
 669                            ORxG_CSNT                   |\
 670                            ORxG_ACS_DIV1               |\
 671                            ORxG_SCY_10_CLK              |\
 672                            ORxG_TRLX)
 673 */
 674 #define CFG_OR4_PRELIM 0xfff00854
 675
 676 /* Bank 8 - On board registers
 677  * PCMCIA (currently not working!)
 678  */
 679 #define CFG_BR8_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
 680                            BRx_PS_16                     |\
 681                            BRx_MS_GPCM_P                |\
 682                            BRx_V)
 683
 684 #define CFG_OR8_PRELIM    (ORxG_AM_MSK                 |\
 685                            ORxG_CSNT                   |\
 686                            ORxG_ACS_DIV1               |\
 687                            ORxG_SETA                   |\
 688                            ORxG_SCY_10_CLK)
 689
 690 /*
 691  * Internal Definitions
 692  *
 693  * Boot Flags
 694  */
 695 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
 696 #define BOOTFLAG_WARM   0x02    /* Software reboot                   */
 697
 698 #endif  /* __CONFIG_H */