include/configs/ep8260.h

   1 /*
   2  * (C) Copyright 2002
   3  * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
   4  *
   5  * This file is based on similar values for other boards found in other
   6  * U-Boot config files, and some that I found in the EP8260 manual.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /*
  12  * board/config.h - configuration options, board specific
  13  *
  14  * "EP8260 H, V.1.1"
  15  *      - 64M 60x Bus SDRAM
  16  *      - 32M Local Bus SDRAM
  17  *      - 16M Flash (4 x AM29DL323DB90WDI)
  18  *      - 128k NVRAM with RTC
  19  *
  20  * "EP8260 H2, V.1.3" (CONFIG_SYS_EP8260_H2)
  21  *      - 300MHz/133MHz/66MHz
  22  *      - 64M 60x Bus SDRAM
  23  *      - 32M Local Bus SDRAM
  24  *      - 32M Flash
  25  *      - 128k NVRAM with RTC
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /* Define this to enable support the EP8260 H2 version */
  32 #define CONFIG_SYS_EP8260_H2    1
  33 /* #undef CONFIG_SYS_EP8260_H2  */
  34
  35 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  36
  37 #define CONFIG_CPM2             1       /* Has a CPM2 */
  38
  39 /* What is the oscillator's (UX2) frequency in Hz? */
  40 #define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
  41
  42 /*-----------------------------------------------------------------------
  43  * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
  44  *-----------------------------------------------------------------------
  45  * What should MODCK_H be? It is dependent on the oscillator
  46  * frequency, MODCK[1-3], and desired CPM and core frequencies.
  47  * Here are some example values (all frequencies are in MHz):
  48  *
  49  * MODCK_H   MODCK[1-3]  Osc    CPM    Core
  50  * -------   ----------  ---    ---    ----
  51  * 0x2       0x2         33     133    133
  52  * 0x2       0x3         33     133    166
  53  * 0x2       0x4         33     133    200
  54  * 0x2       0x5         33     133    233
  55  * 0x2       0x6         33     133    266
  56  *
  57  * 0x5       0x5         66     133    133
  58  * 0x5       0x6         66     133    166
  59  * 0x5       0x7         66     133    200 *
  60  * 0x6       0x0         66     133    233
  61  * 0x6       0x1         66     133    266
  62  * 0x6       0x2         66     133    300
  63  */
  64 #ifdef CONFIG_SYS_EP8260_H2
  65 #define CONFIG_SYS_SBC_MODCK_H  (HRCW_MODCK_H0110)
  66 #else
  67 #define CONFIG_SYS_SBC_MODCK_H  (HRCW_MODCK_H0110)
  68 #endif
  69
  70 /* Define this if you want to boot from 0x00000100. If you don't define
  71  * this, you will need to program the bootloader to 0xfff00000, and
  72  * get the hardware reset config words at 0xfe000000. The simplest
  73  * way to do that is to program the bootloader at both addresses.
  74  * It is suggested that you just let U-Boot live at 0x00000000.
  75  */
  76 /* #define CONFIG_SYS_SBC_BOOT_LOW 1 */ /* only for HRCW */
  77 /* #undef CONFIG_SYS_SBC_BOOT_LOW */
  78
  79 /* The reset command will not work as expected if the reset address does
  80  * not point to the correct address.
  81  */
  82
  83 #define CONFIG_SYS_RESET_ADDRESS        0xFFF00100
  84
  85 /* What should the base address of the main FLASH be and how big is
  86  * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ep8260/config.mk
  87  * The main FLASH is whichever is connected to *CS0. U-Boot expects
  88  * this to be the SIMM.
  89  */
  90 #ifdef CONFIG_SYS_EP8260_H2
  91 #define CONFIG_SYS_FLASH0_BASE 0xFE000000
  92 #define CONFIG_SYS_FLASH0_SIZE 32
  93 #else
  94 #define CONFIG_SYS_FLASH0_BASE 0xFF000000
  95 #define CONFIG_SYS_FLASH0_SIZE 16
  96 #endif
  97
  98 /* What should the base address of the secondary FLASH be and how big
  99  * is it (in Mbytes)? The secondary FLASH is whichever is connected
 100  * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
 101  * want it enabled, don't define these constants.
 102  */
 103 #define CONFIG_SYS_FLASH1_BASE 0
 104 #define CONFIG_SYS_FLASH1_SIZE 0
 105 #undef CONFIG_SYS_FLASH1_BASE
 106 #undef CONFIG_SYS_FLASH1_SIZE
 107
 108 /* What should be the base address of SDRAM DIMM (60x bus) and how big is
 109  * it (in Mbytes)?
 110 */
 111 #define CONFIG_SYS_SDRAM0_BASE 0x00000000
 112 #define CONFIG_SYS_SDRAM0_SIZE 64
 113
 114 /* define CONFIG_SYS_LSDRAM if you want to enable the 32M SDRAM on the
 115  * local bus (8260 local bus is NOT cacheable!)
 116 */
 117 /* #define CONFIG_SYS_LSDRAM */
 118 #undef CONFIG_SYS_LSDRAM
 119
 120 #ifdef CONFIG_SYS_LSDRAM
 121 /* What should be the base address of SDRAM DIMM (local bus) and how big is
 122  * it (in Mbytes)?
 123 */
 124   #define CONFIG_SYS_SDRAM1_BASE 0x04000000
 125   #define CONFIG_SYS_SDRAM1_SIZE 32
 126 #else
 127   #define CONFIG_SYS_SDRAM1_BASE 0
 128   #define CONFIG_SYS_SDRAM1_SIZE 0
 129   #undef CONFIG_SYS_SDRAM1_BASE
 130   #undef CONFIG_SYS_SDRAM1_SIZE
 131 #endif /* CONFIG_SYS_LSDRAM */
 132
 133 /* What should be the base address of NVRAM and how big is
 134  * it (in Bytes)
 135  */
 136 #define CONFIG_SYS_NVRAM_BASE_ADDR  0xFA080000
 137 #define CONFIG_SYS_NVRAM_SIZE       (128*1024)-16
 138
 139 /* The RTC is a Dallas DS1556
 140  */
 141 #define CONFIG_RTC_DS1556
 142
 143 /* What should be the base address of the LEDs and switch S0?
 144  * If you don't want them enabled, don't define this.
 145  */
 146 #define CONFIG_SYS_LED_BASE 0x00000000
 147 #undef CONFIG_SYS_LED_BASE
 148
 149 /*
 150  * select serial console configuration
 151  *
 152  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 153  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 154  * for SCC).
 155  *
 156  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 157  * defined elsewhere.
 158  */
 159 #define CONFIG_CONS_ON_SMC          /* define if console on SMC */
 160 #undef  CONFIG_CONS_ON_SCC          /* define if console on SCC */
 161 #undef  CONFIG_CONS_NONE            /* define if console on neither */
 162 #define CONFIG_CONS_INDEX    1      /* which SMC/SCC channel for console */
 163
 164 /*
 165  * select ethernet configuration
 166  *
 167  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 168  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 169  * for FCC)
 170  *
 171  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 172  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 173  */
 174 #undef  CONFIG_ETHER_ON_SCC           /* define if ethernet on SCC    */
 175 #define CONFIG_ETHER_ON_FCC           /* define if ethernet on FCC    */
 176 #undef  CONFIG_ETHER_NONE             /* define if ethernet on neither */
 177 #define CONFIG_ETHER_INDEX      3     /* which SCC/FCC channel for ethernet */
 178
 179 #if ( CONFIG_ETHER_INDEX == 3 )
 180
 181 /*
 182  * - Rx-CLK is CLK15
 183  * - Tx-CLK is CLK16
 184  * - RAM for BD/Buffers is on the local Bus (see 28-13)
 185  * - Enable Half Duplex in FSMR
 186  */
 187 # define CONFIG_SYS_CMXFCR_MASK3        (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
 188 # define CONFIG_SYS_CMXFCR_VALUE3       (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
 189
 190 /*
 191  * - RAM for BD/Buffers is on the local Bus (see 28-13)
 192  */
 193 #ifdef CONFIG_SYS_LSDRAM
 194   #define CONFIG_SYS_CPMFCR_RAMTYPE     3
 195 #else /* CONFIG_SYS_LSDRAM */
 196   #define CONFIG_SYS_CPMFCR_RAMTYPE     0
 197 #endif /* CONFIG_SYS_LSDRAM */
 198
 199 /* - Enable Half Duplex in FSMR */
 200 /* # define CONFIG_SYS_FCC_PSMR         (FCC_PSMR_FDE|FCC_PSMR_LPB) */
 201 # define CONFIG_SYS_FCC_PSMR            0
 202
 203 #else /* CONFIG_ETHER_INDEX */
 204 # error "on EP8260 ethernet must be FCC3"
 205 #endif /* CONFIG_ETHER_INDEX */
 206
 207 /*
 208  * select i2c support configuration
 209  *
 210  * Supported configurations are {none, software, hardware} drivers.
 211  * If the software driver is chosen, there are some additional
 212  * configuration items that the driver uses to drive the port pins.
 213  */
 214 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
 215
 216 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
 217 #define CONFIG_SYS_I2C_SLAVE            0x7F    /* This is for HARD, must go */
 218
 219 /*
 220  * Software (bit-bang) I2C driver configuration
 221  */
 222 #ifdef CONFIG_SYS_I2C_SOFT
 223 #define CONFIG_SYS_I2C
 224 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
 225 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
 226 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 227 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 228 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 229 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 230 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 231                         else    iop->pdat &= ~0x00010000
 232 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 233                         else    iop->pdat &= ~0x00020000
 234 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 235 #endif /* CONFIG_SYS_I2C_SOFT */
 236
 237 /* #define CONFIG_RTC_DS174x */
 238
 239 /* Define this to reserve an entire FLASH sector (256 KB) for
 240  * environment variables. Otherwise, the environment will be
 241  * put in the same sector as U-Boot, and changing variables
 242  * will erase U-Boot temporarily
 243  */
 244 #define CONFIG_ENV_IN_OWN_SECT
 245
 246 /* Define to allow the user to overwrite serial and ethaddr */
 247 #define CONFIG_ENV_OVERWRITE
 248
 249 /* What should the console's baud rate be? */
 250 #ifdef CONFIG_SYS_EP8260_H2
 251 #define CONFIG_BAUDRATE         9600
 252 #else
 253 #define CONFIG_BAUDRATE         115200
 254 #endif
 255
 256 /* Ethernet MAC address */
 257 #define CONFIG_ETHADDR          00:10:EC:00:30:8C
 258
 259 #define CONFIG_IPADDR           192.168.254.130
 260 #define CONFIG_SERVERIP         192.168.254.49
 261
 262 /* Set to a positive value to delay for running BOOTCOMMAND */
 263 #define CONFIG_BOOTDELAY        -1
 264
 265 /* undef this to save memory */
 266 #define CONFIG_SYS_LONGHELP
 267
 268 /* Monitor Command Prompt       */
 269
 270 /* Define this variable to enable the "hush" shell (from
 271    Busybox) as command line interpreter, thus enabling
 272    powerful command line syntax like
 273    if...then...else...fi conditionals or `&&' and '||'
 274    constructs ("shell scripts").
 275    If undefined, you get the old, much simpler behaviour
 276    with a somewhat smapper memory footprint.
 277 */
 278 #define CONFIG_SYS_HUSH_PARSER
 279
 280
 281 /*
 282  * BOOTP options
 283  */
 284 #define CONFIG_BOOTP_BOOTFILESIZE
 285 #define CONFIG_BOOTP_BOOTPATH
 286 #define CONFIG_BOOTP_GATEWAY
 287 #define CONFIG_BOOTP_HOSTNAME
 288
 289
 290 /*
 291  * Command line configuration.
 292  */
 293 #include <config_cmd_default.h>
 294
 295 #define CONFIG_CMD_ASKENV
 296 #define CONFIG_CMD_BEDBUG
 297 #define CONFIG_CMD_CACHE
 298 #define CONFIG_CMD_CDP
 299 #define CONFIG_CMD_DATE
 300 #define CONFIG_CMD_DIAG
 301 #define CONFIG_CMD_ELF
 302 #define CONFIG_CMD_FAT
 303 #define CONFIG_CMD_I2C
 304 #define CONFIG_CMD_IMMAP
 305 #define CONFIG_CMD_IRQ
 306 #define CONFIG_CMD_PING
 307 #define CONFIG_CMD_PORTIO
 308 #define CONFIG_CMD_REGINFO
 309 #define CONFIG_CMD_SAVES
 310 #define CONFIG_CMD_SDRAM
 311 #define CONFIG_CMD_SNTP
 312
 313 #undef CONFIG_CMD_XIMG
 314
 315 /* Where do the internal registers live? */
 316 #define CONFIG_SYS_IMMR               0xF0000000
 317 #define CONFIG_SYS_DEFAULT_IMMR       0x00010000
 318
 319 /* Where do the on board registers (CS4) live? */
 320 #define CONFIG_SYS_REGS_BASE          0xFA000000
 321
 322 /*****************************************************************************
 323  *
 324  * You should not have to modify any of the following settings
 325  *
 326  *****************************************************************************/
 327
 328 #define CONFIG_EP8260           11      /* on an Embedded Planet EP8260 Board, Rev. 11 */
 329
 330 #define CONFIG_BOARD_EARLY_INIT_F 1         /* Call board_early_init_f  */
 331
 332 /*
 333  * Miscellaneous configurable options
 334  */
 335 #if defined(CONFIG_CMD_KGDB)
 336 #  define CONFIG_SYS_CBSIZE              1024       /* Console I/O Buffer Size      */
 337 #else
 338 #  define CONFIG_SYS_CBSIZE              256        /* Console I/O Buffer Size      */
 339 #endif
 340
 341 /* Print Buffer Size */
 342 #define CONFIG_SYS_PBSIZE        (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
 343
 344 #define CONFIG_SYS_MAXARGS       8            /* max number of command args   */
 345
 346 #define CONFIG_SYS_BARGSIZE      CONFIG_SYS_CBSIZE   /* Boot Argument Buffer Size    */
 347
 348 #ifdef CONFIG_SYS_LSDRAM
 349   #define CONFIG_SYS_MEMTEST_START 0x04000000   /* memtest works on  */
 350   #define CONFIG_SYS_MEMTEST_END   0x06000000   /* 64-96 MB in SDRAM */
 351 #else
 352   #define CONFIG_SYS_MEMTEST_START 0x00000000   /* memtest works on  */
 353   #define CONFIG_SYS_MEMTEST_END   0x02000000   /* 0-32 MB in SDRAM */
 354 #endif /* CONFIG_SYS_LSDRAM */
 355
 356 #define CONFIG_CLOCKS_IN_MHZ    1      /* clocks passsed to Linux in MHz */
 357
 358 #define CONFIG_SYS_LOAD_ADDR     0x00100000   /* default load address */
 359
 360 /*
 361  * Low Level Configuration Settings
 362  * (address mappings, register initial values, etc.)
 363  * You should know what you are doing if you make changes here.
 364  */
 365
 366 #define CONFIG_SYS_FLASH_BASE    CONFIG_SYS_FLASH0_BASE
 367 #define CONFIG_SYS_SDRAM_BASE    CONFIG_SYS_SDRAM0_BASE
 368
 369 /*-----------------------------------------------------------------------
 370  * Hard Reset Configuration Words
 371  */
 372
 373 #if defined(CONFIG_SYS_SBC_BOOT_LOW)
 374 #  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 375 #else
 376 #  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (0x00000000)
 377 #endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
 378
 379 #ifdef CONFIG_SYS_EP8260_H2
 380 /* get the HRCW ISB field from CONFIG_SYS_DEFAULT_IMMR */
 381 #define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_DEFAULT_IMMR & 0x10000000) >> 10) |\
 382                             ((CONFIG_SYS_DEFAULT_IMMR & 0x01000000) >> 7)  |\
 383                             ((CONFIG_SYS_DEFAULT_IMMR & 0x00100000) >> 4) )
 384
 385 #define CONFIG_SYS_HRCW_MASTER (HRCW_EBM                |\
 386                          HRCW_L2CPC01            |\
 387                          CONFIG_SYS_SBC_HRCW_IMMR       |\
 388                          HRCW_APPC10             |\
 389                          HRCW_CS10PC01           |\
 390                          CONFIG_SYS_SBC_MODCK_H  |\
 391                          CONFIG_SYS_SBC_HRCW_BOOT_FLAGS)
 392 #else
 393 #define CONFIG_SYS_HRCW_MASTER 0x10400245
 394 #endif
 395
 396 /* no slaves */
 397 #define CONFIG_SYS_HRCW_SLAVE1 0
 398 #define CONFIG_SYS_HRCW_SLAVE2 0
 399 #define CONFIG_SYS_HRCW_SLAVE3 0
 400 #define CONFIG_SYS_HRCW_SLAVE4 0
 401 #define CONFIG_SYS_HRCW_SLAVE5 0
 402 #define CONFIG_SYS_HRCW_SLAVE6 0
 403 #define CONFIG_SYS_HRCW_SLAVE7 0
 404
 405 /*-----------------------------------------------------------------------
 406  * Definitions for initial stack pointer and data area (in DPRAM)
 407  */
 408 #define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_IMMR
 409 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM    */
 410 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 411 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 412
 413 /*-----------------------------------------------------------------------
 414  * Start addresses for the final memory configuration
 415  * (Set up by the startup code)
 416  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 417  * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
 418  */
 419 #define CONFIG_SYS_MONITOR_BASE          CONFIG_SYS_TEXT_BASE
 420
 421
 422 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 423 #  define CONFIG_SYS_RAMBOOT
 424 #endif
 425
 426 #define CONFIG_SYS_MONITOR_LEN      (256 << 10)     /* Reserve 256 kB for Monitor   */
 427 #define CONFIG_SYS_MALLOC_LEN       (128 << 10)     /* Reserve 128 kB for malloc()  */
 428
 429 /*
 430  * For booting Linux, the board info and command line data
 431  * have to be in the first 8 MB of memory, since this is
 432  * the maximum mapped by the Linux kernel during initialization.
 433  */
 434 #define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 435
 436 /*-----------------------------------------------------------------------
 437  * FLASH and environment organization
 438  */
 439 #define CONFIG_SYS_MAX_FLASH_BANKS   1       /* max number of memory banks         */
 440 #ifdef CONFIG_SYS_EP8260_H2
 441 #define CONFIG_SYS_MAX_FLASH_SECT    128      /* max number of sectors on one chip  */
 442 #else
 443 #define CONFIG_SYS_MAX_FLASH_SECT    71      /* max number of sectors on one chip  */
 444 #endif
 445
 446 #ifdef CONFIG_SYS_EP8260_H2
 447 #define CONFIG_SYS_FLASH_ERASE_TOUT  240000  /* Timeout for Flash Erase (in ms)    */
 448 #define CONFIG_SYS_FLASH_WRITE_TOUT  500     /* Timeout for Flash Write (in ms)    */
 449 #else
 450 #define CONFIG_SYS_FLASH_ERASE_TOUT  8000    /* Timeout for Flash Erase (in ms)    */
 451 #define CONFIG_SYS_FLASH_WRITE_TOUT  1       /* Timeout for Flash Write (in ms)    */
 452 #endif
 453
 454 #ifndef CONFIG_SYS_RAMBOOT
 455 #  define CONFIG_ENV_IS_IN_FLASH  1
 456
 457 #  ifdef CONFIG_ENV_IN_OWN_SECT
 458 #    define CONFIG_ENV_ADDR       (CONFIG_SYS_MONITOR_BASE + 0x40000)
 459 #    define CONFIG_ENV_SECT_SIZE  0x40000
 460 #  else
 461 #    define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
 462 #    define CONFIG_ENV_SIZE       0x1000  /* Total Size of Environment Sector */
 463 #    define CONFIG_ENV_SECT_SIZE  0x10000 /* see README - env sect real size */
 464 #  endif /* CONFIG_ENV_IN_OWN_SECT */
 465 #else
 466 #  define CONFIG_ENV_IS_IN_NVRAM  1
 467 #  define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 468 #  define CONFIG_ENV_SIZE         0x200
 469 #endif /* CONFIG_SYS_RAMBOOT */
 470
 471 /*-----------------------------------------------------------------------
 472  * Cache Configuration
 473  */
 474 #define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU */
 475
 476 #if defined(CONFIG_CMD_KGDB)
 477 #  define CONFIG_SYS_CACHELINE_SHIFT     5     /* log base 2 of the above value */
 478 #endif
 479
 480 /*-----------------------------------------------------------------------
 481  * HIDx - Hardware Implementation-dependent Registers                    2-11
 482  *-----------------------------------------------------------------------
 483  * HID0 also contains cache control - initially enable both caches and
 484  * invalidate contents, then the final state leaves only the instruction
 485  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 486  * but Soft reset does not.
 487  *
 488  * HID1 has only read-only information - nothing to set.
 489  */
 490 #define CONFIG_SYS_HID0_INIT   (HID0_ICE  |\
 491                          HID0_DCE  |\
 492                          HID0_ICFI |\
 493                          HID0_DCI  |\
 494                          HID0_IFEM |\
 495                          HID0_ABE)
 496 #ifdef CONFIG_SYS_LSDRAM
 497 /* 8260 local bus is NOT cacheable */
 498 #define CONFIG_SYS_HID0_FINAL  (/*HID0_ICE  |*/\
 499                          HID0_IFEM |\
 500                          HID0_ABE  |\
 501                          HID0_EMCP)
 502 #else /* !CONFIG_SYS_LSDRAM */
 503 #define CONFIG_SYS_HID0_FINAL  (HID0_ICE  |\
 504                          HID0_IFEM |\
 505                          HID0_ABE  |\
 506                          HID0_EMCP)
 507 #endif /* CONFIG_SYS_LSDRAM */
 508
 509 #define CONFIG_SYS_HID2        0
 510
 511 /*-----------------------------------------------------------------------
 512  * RMR - Reset Mode Register
 513  *-----------------------------------------------------------------------
 514  */
 515 #define CONFIG_SYS_RMR         0
 516
 517 /*-----------------------------------------------------------------------
 518  * BCR - Bus Configuration                                       4-25
 519  *-----------------------------------------------------------------------
 520  */
 521 #define CONFIG_SYS_BCR         (BCR_EBM   |\
 522                          BCR_PLDP  |\
 523                          BCR_EAV   |\
 524                          BCR_NPQM0)
 525
 526 /*-----------------------------------------------------------------------
 527  * SIUMCR - SIU Module Configuration                             4-31
 528  *-----------------------------------------------------------------------
 529  */
 530 #define CONFIG_SYS_SIUMCR      (SIUMCR_L2CPC01 |\
 531                          SIUMCR_APPC10  |\
 532                          SIUMCR_CS10PC01)
 533
 534 /*-----------------------------------------------------------------------
 535  * SYPCR - System Protection Control                            11-9
 536  * SYPCR can only be written once after reset!
 537  *-----------------------------------------------------------------------
 538  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 539  */
 540 #ifdef CONFIG_SYS_EP8260_H2
 541 /* TBD: Find out why setting the BMT to 0xff causes the FCC to
 542  * generate TX buffer underrun errors for large packets under
 543  * Linux
 544  */
 545 #define CONFIG_SYS_SYPCR_BMT    0x00000600
 546 #else
 547 #define CONFIG_SYS_SYPCR_BMT    SYPCR_BMT
 548 #endif
 549
 550 #ifdef CONFIG_SYS_LSDRAM
 551 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC |\
 552                          CONFIG_SYS_SYPCR_BMT  |\
 553                          SYPCR_PBME |\
 554                          SYPCR_LBME |\
 555                          SYPCR_SWP)
 556 #else
 557 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC |\
 558                          CONFIG_SYS_SYPCR_BMT  |\
 559                          SYPCR_PBME |\
 560                          SYPCR_SWP)
 561 #endif
 562
 563 /*-----------------------------------------------------------------------
 564  * TMCNTSC - Time Counter Status and Control                     4-40
 565  *-----------------------------------------------------------------------
 566  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 567  * and enable Time Counter
 568  */
 569 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC |\
 570                          TMCNTSC_ALR |\
 571                          TMCNTSC_TCF |\
 572                          TMCNTSC_TCE)
 573
 574 /*-----------------------------------------------------------------------
 575  * PISCR - Periodic Interrupt Status and Control                 4-42
 576  *-----------------------------------------------------------------------
 577  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 578  * Periodic timer
 579  */
 580 #ifdef CONFIG_SYS_EP8260_H2
 581 #define CONFIG_SYS_PISCR       (PISCR_PS  |\
 582                          PISCR_PTF |\
 583                          PISCR_PTE)
 584 #else
 585 #define CONFIG_SYS_PISCR        0
 586 #endif
 587
 588 /*-----------------------------------------------------------------------
 589  * SCCR - System Clock Control                                   9-8
 590  *-----------------------------------------------------------------------
 591  */
 592 #ifdef CONFIG_SYS_EP8260_H2
 593 #define CONFIG_SYS_SCCR        (SCCR_DFBRG00)
 594 #else
 595 #define CONFIG_SYS_SCCR        (SCCR_DFBRG01)
 596 #endif
 597
 598 /*-----------------------------------------------------------------------
 599  * RCCR - RISC Controller Configuration                         13-7
 600  *-----------------------------------------------------------------------
 601  */
 602 #define CONFIG_SYS_RCCR        0
 603
 604 /*-----------------------------------------------------------------------
 605  * MPTPR - Memory Refresh Timer Prescale Register               10-32
 606  *-----------------------------------------------------------------------
 607  */
 608 #define CONFIG_SYS_MPTPR        (0x0A00 & MPTPR_PTP_MSK)
 609
 610 /*
 611  * Init Memory Controller:
 612  *
 613  * Bank Bus     Machine PortSz  Device
 614  * ---- ---     ------- ------  ------
 615  *  0   60x     GPCM    64 bit  FLASH (BGA - 16MB AMD AM29DL323DB90WDI)
 616  *  1   60x     SDRAM   64 bit  SDRAM (BGA - 64MB Micron 48LC8M16A2TG)
 617  *  2   Local   SDRAM   32 bit  SDRAM (BGA - 32MB Micron 48LC8M16A2TG)
 618  *  3   unused
 619  *  4   60x     GPCM     8 bit  Board Regs, NVRTC
 620  *  5   unused
 621  *  6   unused
 622  *  7   unused
 623  *  8   PCMCIA
 624  *  9   unused
 625  * 10   unused
 626  * 11   unused
 627 */
 628
 629 /*-----------------------------------------------------------------------
 630  * BRx - Base Register
 631  *     Ref: Section 10.3.1 on page 10-14
 632  * ORx - Option Register
 633  *     Ref: Section 10.3.2 on page 10-18
 634  *-----------------------------------------------------------------------
 635  */
 636
 637 /* Bank 0 - FLASH
 638  *
 639  */
 640 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
 641                          BRx_PS_64                      |\
 642                          BRx_DECC_NONE                  |\
 643                          BRx_MS_GPCM_P                  |\
 644                          BRx_V)
 645
 646 #define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE)     |\
 647                          ORxG_CSNT                      |\
 648                          ORxG_ACS_DIV1                  |\
 649                          ORxG_SCY_8_CLK                 |\
 650                          ORxG_EHTR)
 651
 652 /* Bank 1 - SDRAM
 653  * PSDRAM
 654  */
 655 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
 656                          BRx_PS_64                      |\
 657                          BRx_MS_SDRAM_P                 |\
 658                          BRx_V)
 659
 660 #define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE)     |\
 661                          ORxS_BPD_4                     |\
 662                          ORxS_ROWST_PBI1_A6             |\
 663                          ORxS_NUMR_12)
 664
 665 #ifdef CONFIG_SYS_EP8260_H2
 666 #define CONFIG_SYS_PSDMR       0xC34E246E
 667 #else
 668 #define CONFIG_SYS_PSDMR       0xC34E2462
 669 #endif
 670
 671 #define CONFIG_SYS_PSRT 0x64
 672
 673 #ifdef CONFIG_SYS_LSDRAM
 674 /* Bank 2 - SDRAM
 675  * LSDRAM
 676  */
 677
 678   #define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
 679                            BRx_PS_32                      |\
 680                            BRx_MS_SDRAM_L                 |\
 681                            BRx_V)
 682
 683   #define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE)     |\
 684                            ORxS_BPD_4                     |\
 685                            ORxS_ROWST_PBI0_A9             |\
 686                            ORxS_NUMR_12)
 687
 688   #define CONFIG_SYS_LSDMR      0x416A2562
 689   #define CONFIG_SYS_LSRT       0x64
 690 #else
 691   #define CONFIG_SYS_LSRT       0x0
 692 #endif /* CONFIG_SYS_LSDRAM */
 693
 694 /* Bank 4 - On board registers
 695  * NVRTC and BCSR
 696  */
 697 #define CONFIG_SYS_BR4_PRELIM   ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK)  |\
 698                            BRx_PS_8                     |\
 699                            BRx_MS_GPCM_P                |\
 700                            BRx_V)
 701 /*
 702 #define CONFIG_SYS_OR4_PRELIM    (ORxG_AM_MSK                 |\
 703                            ORxG_CSNT                   |\
 704                            ORxG_ACS_DIV1               |\
 705                            ORxG_SCY_10_CLK              |\
 706                            ORxG_TRLX)
 707 */
 708 #define CONFIG_SYS_OR4_PRELIM 0xfff00854
 709
 710 #ifdef _NOT_USED_SINCE_NOT_WORKING_
 711 /* Bank 8 - On board registers
 712  * PCMCIA (currently not working!)
 713  */
 714 #define CONFIG_SYS_BR8_PRELIM   ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK)  |\
 715                            BRx_PS_16                     |\
 716                            BRx_MS_GPCM_P                |\
 717                            BRx_V)
 718
 719 #define CONFIG_SYS_OR8_PRELIM    (ORxG_AM_MSK                 |\
 720                            ORxG_CSNT                   |\
 721                            ORxG_ACS_DIV1               |\
 722                            ORxG_SETA                   |\
 723                            ORxG_SCY_10_CLK)
 724 #endif
 725
 726 /*
 727  * JFFS2 partitions
 728  *
 729  */
 730 /* No command line, one static partition, whole device */
 731 #undef CONFIG_CMD_MTDPARTS
 732 #define CONFIG_JFFS2_DEV                "nor0"
 733 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 734 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 735
 736 /* mtdparts command line support */
 737 /* Note: fake mtd_id used, no linux mtd map file */
 738 /*
 739 #define CONFIG_CMD_MTDPARTS
 740 #define MTDIDS_DEFAULT          ""
 741 #define MTDPARTS_DEFAULT        ""
 742 */
 743
 744 #endif  /* __CONFIG_H */