include/configs/ep8260.h

   1 /*
   2  * (C) Copyright 2002
   3  * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
   4  *
   5  * This file is based on similar values for other boards found in other
   6  * U-Boot config files, and some that I found in the EP8260 manual.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * board/config.h - configuration options, board specific
  29  *
  30  * "EP8260 H, V.1.1"
  31  *      - 64M 60x Bus SDRAM
  32  *      - 32M Local Bus SDRAM
  33  *      - 16M Flash (4 x AM29DL323DB90WDI)
  34  *      - 128k NVRAM with RTC
  35  *
  36  * "EP8260 H2, V.1.3" (CFG_EP8260_H2)
  37  *      - 300MHz/133MHz/66MHz
  38  *      - 64M 60x Bus SDRAM
  39  *      - 32M Local Bus SDRAM
  40  *      - 32M Flash
  41  *      - 128k NVRAM with RTC
  42  */
  43
  44 #ifndef __CONFIG_H
  45 #define __CONFIG_H
  46
  47 /* Define this to enable support the EP8260 H2 version */
  48 #define CFG_EP8260_H2   1
  49 /* #undef CFG_EP8260_H2  */
  50
  51 #define CONFIG_CPM2             1       /* Has a CPM2 */
  52
  53 /* What is the oscillator's (UX2) frequency in Hz? */
  54 #define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
  55
  56 /*-----------------------------------------------------------------------
  57  * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
  58  *-----------------------------------------------------------------------
  59  * What should MODCK_H be? It is dependent on the oscillator
  60  * frequency, MODCK[1-3], and desired CPM and core frequencies.
  61  * Here are some example values (all frequencies are in MHz):
  62  *
  63  * MODCK_H   MODCK[1-3]  Osc    CPM    Core
  64  * -------   ----------  ---    ---    ----
  65  * 0x2       0x2         33     133    133
  66  * 0x2       0x3         33     133    166
  67  * 0x2       0x4         33     133    200
  68  * 0x2       0x5         33     133    233
  69  * 0x2       0x6         33     133    266
  70  *
  71  * 0x5       0x5         66     133    133
  72  * 0x5       0x6         66     133    166
  73  * 0x5       0x7         66     133    200 *
  74  * 0x6       0x0         66     133    233
  75  * 0x6       0x1         66     133    266
  76  * 0x6       0x2         66     133    300
  77  */
  78 #ifdef CFG_EP8260_H2
  79 #define CFG_SBC_MODCK_H  (HRCW_MODCK_H0110)
  80 #else
  81 #define CFG_SBC_MODCK_H  (HRCW_MODCK_H0110)
  82 #endif
  83
  84 /* Define this if you want to boot from 0x00000100. If you don't define
  85  * this, you will need to program the bootloader to 0xfff00000, and
  86  * get the hardware reset config words at 0xfe000000. The simplest
  87  * way to do that is to program the bootloader at both addresses.
  88  * It is suggested that you just let U-Boot live at 0x00000000.
  89  */
  90 /* #define CFG_SBC_BOOT_LOW 1 */        /* only for HRCW */
  91 /* #undef CFG_SBC_BOOT_LOW */
  92
  93 /* The reset command will not work as expected if the reset address does
  94  * not point to the correct address.
  95  */
  96
  97 #define CFG_RESET_ADDRESS       0xFFF00100
  98
  99 /* What should the base address of the main FLASH be and how big is
 100  * it (in MBytes)? This must contain TEXT_BASE from board/ep8260/config.mk
 101  * The main FLASH is whichever is connected to *CS0. U-Boot expects
 102  * this to be the SIMM.
 103  */
 104 #ifdef CFG_EP8260_H2
 105 #define CFG_FLASH0_BASE 0xFE000000
 106 #define CFG_FLASH0_SIZE 32
 107 #else
 108 #define CFG_FLASH0_BASE 0xFF000000
 109 #define CFG_FLASH0_SIZE 16
 110 #endif
 111
 112 /* What should the base address of the secondary FLASH be and how big
 113  * is it (in Mbytes)? The secondary FLASH is whichever is connected
 114  * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
 115  * want it enabled, don't define these constants.
 116  */
 117 #define CFG_FLASH1_BASE 0
 118 #define CFG_FLASH1_SIZE 0
 119 #undef CFG_FLASH1_BASE
 120 #undef CFG_FLASH1_SIZE
 121
 122 /* What should be the base address of SDRAM DIMM (60x bus) and how big is
 123  * it (in Mbytes)?
 124 */
 125 #define CFG_SDRAM0_BASE 0x00000000
 126 #define CFG_SDRAM0_SIZE 64
 127
 128 /* define CFG_LSDRAM if you want to enable the 32M SDRAM on the
 129  * local bus (8260 local bus is NOT cacheable!)
 130 */
 131 /* #define CFG_LSDRAM */
 132 #undef CFG_LSDRAM
 133
 134 #ifdef CFG_LSDRAM
 135 /* What should be the base address of SDRAM DIMM (local bus) and how big is
 136  * it (in Mbytes)?
 137 */
 138   #define CFG_SDRAM1_BASE 0x04000000
 139   #define CFG_SDRAM1_SIZE 32
 140 #else
 141   #define CFG_SDRAM1_BASE 0
 142   #define CFG_SDRAM1_SIZE 0
 143   #undef CFG_SDRAM1_BASE
 144   #undef CFG_SDRAM1_SIZE
 145 #endif /* CFG_LSDRAM */
 146
 147 /* What should be the base address of NVRAM and how big is
 148  * it (in Bytes)
 149  */
 150 #define CFG_NVRAM_BASE_ADDR  0xFA080000
 151 #define CFG_NVRAM_SIZE       (128*1024)-16
 152
 153 /* The RTC is a Dallas DS1556
 154  */
 155 #define CONFIG_RTC_DS1556
 156
 157 /* What should be the base address of the LEDs and switch S0?
 158  * If you don't want them enabled, don't define this.
 159  */
 160 #define CFG_LED_BASE 0x00000000
 161 #undef CFG_LED_BASE
 162
 163 /*
 164  * select serial console configuration
 165  *
 166  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 167  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 168  * for SCC).
 169  *
 170  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 171  * defined elsewhere.
 172  */
 173 #define CONFIG_CONS_ON_SMC          /* define if console on SMC */
 174 #undef  CONFIG_CONS_ON_SCC          /* define if console on SCC */
 175 #undef  CONFIG_CONS_NONE            /* define if console on neither */
 176 #define CONFIG_CONS_INDEX    1      /* which SMC/SCC channel for console */
 177
 178 /*
 179  * select ethernet configuration
 180  *
 181  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 182  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 183  * for FCC)
 184  *
 185  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 186  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 187  */
 188 #undef  CONFIG_ETHER_ON_SCC           /* define if ethernet on SCC    */
 189 #define CONFIG_ETHER_ON_FCC           /* define if ethernet on FCC    */
 190 #undef  CONFIG_ETHER_NONE             /* define if ethernet on neither */
 191 #define CONFIG_ETHER_INDEX      3     /* which SCC/FCC channel for ethernet */
 192
 193 #if ( CONFIG_ETHER_INDEX == 3 )
 194
 195 /*
 196  * - Rx-CLK is CLK15
 197  * - Tx-CLK is CLK16
 198  * - RAM for BD/Buffers is on the local Bus (see 28-13)
 199  * - Enable Half Duplex in FSMR
 200  */
 201 # define CFG_CMXFCR_MASK        (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
 202 # define CFG_CMXFCR_VALUE       (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
 203
 204 /*
 205  * - RAM for BD/Buffers is on the local Bus (see 28-13)
 206  */
 207 #ifdef CFG_LSDRAM
 208   #define CFG_CPMFCR_RAMTYPE    3
 209 #else /* CFG_LSDRAM */
 210   #define CFG_CPMFCR_RAMTYPE    0
 211 #endif /* CFG_LSDRAM */
 212
 213 /* - Enable Half Duplex in FSMR */
 214 /* # define CFG_FCC_PSMR                (FCC_PSMR_FDE|FCC_PSMR_LPB) */
 215 # define CFG_FCC_PSMR           0
 216
 217 #else /* CONFIG_ETHER_INDEX */
 218 # error "on EP8260 ethernet must be FCC3"
 219 #endif /* CONFIG_ETHER_INDEX */
 220
 221 /*
 222  * select i2c support configuration
 223  *
 224  * Supported configurations are {none, software, hardware} drivers.
 225  * If the software driver is chosen, there are some additional
 226  * configuration items that the driver uses to drive the port pins.
 227  */
 228 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 229 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 230 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 231 #define CFG_I2C_SLAVE           0x7F
 232
 233 /*
 234  * Software (bit-bang) I2C driver configuration
 235  */
 236 #ifdef CONFIG_SOFT_I2C
 237 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 238 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 239 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 240 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 241 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 242                         else    iop->pdat &= ~0x00010000
 243 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 244                         else    iop->pdat &= ~0x00020000
 245 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 246 #endif /* CONFIG_SOFT_I2C */
 247
 248 /* #define CONFIG_RTC_DS174x */
 249
 250 /* Define this to reserve an entire FLASH sector (256 KB) for
 251  * environment variables. Otherwise, the environment will be
 252  * put in the same sector as U-Boot, and changing variables
 253  * will erase U-Boot temporarily
 254  */
 255 #define CFG_ENV_IN_OWN_SECT
 256
 257 /* Define to allow the user to overwrite serial and ethaddr */
 258 #define CONFIG_ENV_OVERWRITE
 259
 260 /* What should the console's baud rate be? */
 261 #ifdef CFG_EP8260_H2
 262 #define CONFIG_BAUDRATE         9600
 263 #else
 264 #define CONFIG_BAUDRATE         115200
 265 #endif
 266
 267 /* Ethernet MAC address */
 268 #define CONFIG_ETHADDR          00:10:EC:00:30:8C
 269
 270 #define CONFIG_IPADDR           192.168.254.130
 271 #define CONFIG_SERVERIP         192.168.254.49
 272
 273 /* Set to a positive value to delay for running BOOTCOMMAND */
 274 #define CONFIG_BOOTDELAY        -1
 275
 276 /* undef this to save memory */
 277 #define CFG_LONGHELP
 278
 279 /* Monitor Command Prompt       */
 280 #define CFG_PROMPT              "=> "
 281
 282 /* Define this variable to enable the "hush" shell (from
 283    Busybox) as command line interpreter, thus enabling
 284    powerful command line syntax like
 285    if...then...else...fi conditionals or `&&' and '||'
 286    constructs ("shell scripts").
 287    If undefined, you get the old, much simpler behaviour
 288    with a somewhat smapper memory footprint.
 289 */
 290 #define CFG_HUSH_PARSER
 291 #define CFG_PROMPT_HUSH_PS2     "> "
 292
 293
 294 /*
 295  * Command line configuration.
 296  */
 297 #include <config_cmd_all.h>
 298
 299 #undef CONFIG_CMD_BMP
 300 #undef CONFIG_CMD_BSP
 301 #undef CONFIG_CMD_DCR
 302 #undef CONFIG_CMD_DHCP
 303 #undef CONFIG_CMD_DISPLAY
 304 #undef CONFIG_CMD_DOC
 305 #undef CONFIG_CMD_DTT
 306 #undef CONFIG_CMD_EEPROM
 307 #undef CONFIG_CMD_EXT2
 308 #undef CONFIG_CMD_FDC
 309 #undef CONFIG_CMD_FDOS
 310 #undef CONFIG_CMD_HWFLOW
 311 #undef CONFIG_CMD_IDE
 312 #undef CONFIG_CMD_JFFS2
 313 #undef CONFIG_CMD_KGDB
 314 #undef CONFIG_CMD_MII
 315 #undef CONFIG_CMD_MMC
 316 #undef CONFIG_CMD_NAND
 317 #undef CONFIG_CMD_PCI
 318 #undef CONFIG_CMD_PCMCIA
 319 #undef CONFIG_CMD_REISER
 320 #undef CONFIG_CMD_SCSI
 321 #undef CONFIG_CMD_SPI
 322 #undef CONFIG_CMD_UNIVERSE
 323 #undef CONFIG_CMD_USB
 324 #undef CONFIG_CMD_VFD
 325 #undef CONFIG_CMD_XIMG
 326
 327
 328 /* Where do the internal registers live? */
 329 #define CFG_IMMR               0xF0000000
 330 #define CFG_DEFAULT_IMMR       0x00010000
 331
 332 /* Where do the on board registers (CS4) live? */
 333 #define CFG_REGS_BASE          0xFA000000
 334
 335 /*****************************************************************************
 336  *
 337  * You should not have to modify any of the following settings
 338  *
 339  *****************************************************************************/
 340
 341 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
 342 #define CONFIG_EP8260           11      /* on an Embedded Planet EP8260 Board, Rev. 11 */
 343
 344 #define CONFIG_BOARD_EARLY_INIT_F 1         /* Call board_early_init_f  */
 345
 346 /*
 347  * Miscellaneous configurable options
 348  */
 349 #if defined(CONFIG_CMD_KGDB)
 350 #  define CFG_CBSIZE              1024       /* Console I/O Buffer Size      */
 351 #else
 352 #  define CFG_CBSIZE              256        /* Console I/O Buffer Size      */
 353 #endif
 354
 355 /* Print Buffer Size */
 356 #define CFG_PBSIZE        (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
 357
 358 #define CFG_MAXARGS       8            /* max number of command args   */
 359
 360 #define CFG_BARGSIZE      CFG_CBSIZE   /* Boot Argument Buffer Size    */
 361
 362 #ifdef CFG_LSDRAM
 363   #define CFG_MEMTEST_START 0x04000000   /* memtest works on  */
 364   #define CFG_MEMTEST_END   0x06000000   /* 64-96 MB in SDRAM */
 365 #else
 366   #define CFG_MEMTEST_START 0x00000000   /* memtest works on  */
 367   #define CFG_MEMTEST_END   0x02000000   /* 0-32 MB in SDRAM */
 368 #endif /* CFG_LSDRAM */
 369
 370 #define CONFIG_CLOCKS_IN_MHZ    1      /* clocks passsed to Linux in MHz */
 371
 372 #define CFG_LOAD_ADDR     0x00100000   /* default load address */
 373 #define CFG_TFTP_LOADADDR 0x00100000   /* default load address for network file downloads */
 374
 375 #define CFG_HZ            1000         /* decrementer freq: 1 ms ticks */
 376
 377 /* valid baudrates */
 378 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 379
 380 /*
 381  * Low Level Configuration Settings
 382  * (address mappings, register initial values, etc.)
 383  * You should know what you are doing if you make changes here.
 384  */
 385
 386 #define CFG_FLASH_BASE    CFG_FLASH0_BASE
 387 #define CFG_SDRAM_BASE    CFG_SDRAM0_BASE
 388
 389 /*-----------------------------------------------------------------------
 390  * Hard Reset Configuration Words
 391  */
 392
 393 #if defined(CFG_SBC_BOOT_LOW)
 394 #  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 395 #else
 396 #  define  CFG_SBC_HRCW_BOOT_FLAGS  (0x00000000)
 397 #endif /* defined(CFG_SBC_BOOT_LOW) */
 398
 399 #ifdef CFG_EP8260_H2
 400 /* get the HRCW ISB field from CFG_DEFAULT_IMMR */
 401 #define CFG_SBC_HRCW_IMMR ( ((CFG_DEFAULT_IMMR & 0x10000000) >> 10) |\
 402                             ((CFG_DEFAULT_IMMR & 0x01000000) >> 7)  |\
 403                             ((CFG_DEFAULT_IMMR & 0x00100000) >> 4) )
 404
 405 #define CFG_HRCW_MASTER (HRCW_EBM                |\
 406                          HRCW_L2CPC01            |\
 407                          CFG_SBC_HRCW_IMMR       |\
 408                          HRCW_APPC10             |\
 409                          HRCW_CS10PC01           |\
 410                          CFG_SBC_MODCK_H         |\
 411                          CFG_SBC_HRCW_BOOT_FLAGS)
 412 #else
 413 #define CFG_HRCW_MASTER 0x10400245
 414 #endif
 415
 416 /* no slaves */
 417 #define CFG_HRCW_SLAVE1 0
 418 #define CFG_HRCW_SLAVE2 0
 419 #define CFG_HRCW_SLAVE3 0
 420 #define CFG_HRCW_SLAVE4 0
 421 #define CFG_HRCW_SLAVE5 0
 422 #define CFG_HRCW_SLAVE6 0
 423 #define CFG_HRCW_SLAVE7 0
 424
 425 /*-----------------------------------------------------------------------
 426  * Definitions for initial stack pointer and data area (in DPRAM)
 427  */
 428 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 429 #define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
 430 #define CFG_GBL_DATA_SIZE      128     /* bytes reserved for initial data */
 431 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 432 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 433
 434 /*-----------------------------------------------------------------------
 435  * Start addresses for the final memory configuration
 436  * (Set up by the startup code)
 437  * Please note that CFG_SDRAM_BASE _must_ start at 0
 438  * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
 439  */
 440 #define CFG_MONITOR_BASE          TEXT_BASE
 441
 442
 443 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 444 #  define CFG_RAMBOOT
 445 #endif
 446
 447 #define CFG_MONITOR_LEN      (256 << 10)     /* Reserve 256 kB for Monitor   */
 448 #define CFG_MALLOC_LEN       (128 << 10)     /* Reserve 128 kB for malloc()  */
 449
 450 /*
 451  * For booting Linux, the board info and command line data
 452  * have to be in the first 8 MB of memory, since this is
 453  * the maximum mapped by the Linux kernel during initialization.
 454  */
 455 #define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 456
 457 /*-----------------------------------------------------------------------
 458  * FLASH and environment organization
 459  */
 460 #define CFG_MAX_FLASH_BANKS   1       /* max number of memory banks         */
 461 #ifdef CFG_EP8260_H2
 462 #define CFG_MAX_FLASH_SECT    128      /* max number of sectors on one chip  */
 463 #else
 464 #define CFG_MAX_FLASH_SECT    71      /* max number of sectors on one chip  */
 465 #endif
 466
 467 #ifdef CFG_EP8260_H2
 468 #define CFG_FLASH_ERASE_TOUT  240000  /* Timeout for Flash Erase (in ms)    */
 469 #define CFG_FLASH_WRITE_TOUT  500     /* Timeout for Flash Write (in ms)    */
 470 #else
 471 #define CFG_FLASH_ERASE_TOUT  8000    /* Timeout for Flash Erase (in ms)    */
 472 #define CFG_FLASH_WRITE_TOUT  1       /* Timeout for Flash Write (in ms)    */
 473 #endif
 474
 475 #ifndef CFG_RAMBOOT
 476 #  define CFG_ENV_IS_IN_FLASH  1
 477
 478 #  ifdef CFG_ENV_IN_OWN_SECT
 479 #    define CFG_ENV_ADDR       (CFG_MONITOR_BASE + 0x40000)
 480 #    define CFG_ENV_SECT_SIZE  0x40000
 481 #  else
 482 #    define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
 483 #    define CFG_ENV_SIZE       0x1000  /* Total Size of Environment Sector */
 484 #    define CFG_ENV_SECT_SIZE  0x10000 /* see README - env sect real size */
 485 #  endif /* CFG_ENV_IN_OWN_SECT */
 486 #else
 487 #  define CFG_ENV_IS_IN_NVRAM  1
 488 #  define CFG_ENV_ADDR         (CFG_MONITOR_BASE - 0x1000)
 489 #  define CFG_ENV_SIZE         0x200
 490 #endif /* CFG_RAMBOOT */
 491
 492 /*-----------------------------------------------------------------------
 493  * Cache Configuration
 494  */
 495 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU */
 496
 497 #if defined(CONFIG_CMD_KGDB)
 498 #  define CFG_CACHELINE_SHIFT     5     /* log base 2 of the above value */
 499 #endif
 500
 501 /*-----------------------------------------------------------------------
 502  * HIDx - Hardware Implementation-dependent Registers                    2-11
 503  *-----------------------------------------------------------------------
 504  * HID0 also contains cache control - initially enable both caches and
 505  * invalidate contents, then the final state leaves only the instruction
 506  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 507  * but Soft reset does not.
 508  *
 509  * HID1 has only read-only information - nothing to set.
 510  */
 511 #define CFG_HID0_INIT   (HID0_ICE  |\
 512                          HID0_DCE  |\
 513                          HID0_ICFI |\
 514                          HID0_DCI  |\
 515                          HID0_IFEM |\
 516                          HID0_ABE)
 517 #ifdef CFG_LSDRAM
 518 /* 8260 local bus is NOT cacheable */
 519 #define CFG_HID0_FINAL  (/*HID0_ICE  |*/\
 520                          HID0_IFEM |\
 521                          HID0_ABE  |\
 522                          HID0_EMCP)
 523 #else /* !CFG_LSDRAM */
 524 #define CFG_HID0_FINAL  (HID0_ICE  |\
 525                          HID0_IFEM |\
 526                          HID0_ABE  |\
 527                          HID0_EMCP)
 528 #endif /* CFG_LSDRAM */
 529
 530 #define CFG_HID2        0
 531
 532 /*-----------------------------------------------------------------------
 533  * RMR - Reset Mode Register
 534  *-----------------------------------------------------------------------
 535  */
 536 #define CFG_RMR         0
 537
 538 /*-----------------------------------------------------------------------
 539  * BCR - Bus Configuration                                       4-25
 540  *-----------------------------------------------------------------------
 541  */
 542 #define CFG_BCR         (BCR_EBM   |\
 543                          BCR_PLDP  |\
 544                          BCR_EAV   |\
 545                          BCR_NPQM0)
 546
 547 /*-----------------------------------------------------------------------
 548  * SIUMCR - SIU Module Configuration                             4-31
 549  *-----------------------------------------------------------------------
 550  */
 551 #define CFG_SIUMCR      (SIUMCR_L2CPC01 |\
 552                          SIUMCR_APPC10  |\
 553                          SIUMCR_CS10PC01)
 554
 555 /*-----------------------------------------------------------------------
 556  * SYPCR - System Protection Control                            11-9
 557  * SYPCR can only be written once after reset!
 558  *-----------------------------------------------------------------------
 559  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 560  */
 561 #ifdef CFG_EP8260_H2
 562 /* TBD: Find out why setting the BMT to 0xff causes the FCC to
 563  * generate TX buffer underrun errors for large packets under
 564  * Linux
 565  */
 566 #define CFG_SYPCR_BMT   0x00000600
 567 #else
 568 #define CFG_SYPCR_BMT   SYPCR_BMT
 569 #endif
 570
 571 #ifdef CFG_LSDRAM
 572 #define CFG_SYPCR       (SYPCR_SWTC |\
 573                          CFG_SYPCR_BMT  |\
 574                          SYPCR_PBME |\
 575                          SYPCR_LBME |\
 576                          SYPCR_SWP)
 577 #else
 578 #define CFG_SYPCR       (SYPCR_SWTC |\
 579                          CFG_SYPCR_BMT  |\
 580                          SYPCR_PBME |\
 581                          SYPCR_SWP)
 582 #endif
 583
 584 /*-----------------------------------------------------------------------
 585  * TMCNTSC - Time Counter Status and Control                     4-40
 586  *-----------------------------------------------------------------------
 587  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 588  * and enable Time Counter
 589  */
 590 #define CFG_TMCNTSC     (TMCNTSC_SEC |\
 591                          TMCNTSC_ALR |\
 592                          TMCNTSC_TCF |\
 593                          TMCNTSC_TCE)
 594
 595 /*-----------------------------------------------------------------------
 596  * PISCR - Periodic Interrupt Status and Control                 4-42
 597  *-----------------------------------------------------------------------
 598  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 599  * Periodic timer
 600  */
 601 #ifdef CFG_EP8260_H2
 602 #define CFG_PISCR       (PISCR_PS  |\
 603                          PISCR_PTF |\
 604                          PISCR_PTE)
 605 #else
 606 #define CFG_PISCR       0
 607 #endif
 608
 609 /*-----------------------------------------------------------------------
 610  * SCCR - System Clock Control                                   9-8
 611  *-----------------------------------------------------------------------
 612  */
 613 #ifdef CFG_EP8260_H2
 614 #define CFG_SCCR        (SCCR_DFBRG00)
 615 #else
 616 #define CFG_SCCR        (SCCR_DFBRG01)
 617 #endif
 618
 619 /*-----------------------------------------------------------------------
 620  * RCCR - RISC Controller Configuration                         13-7
 621  *-----------------------------------------------------------------------
 622  */
 623 #define CFG_RCCR        0
 624
 625 /*-----------------------------------------------------------------------
 626  * MPTPR - Memory Refresh Timer Prescale Register               10-32
 627  *-----------------------------------------------------------------------
 628  */
 629 #define CFG_MPTPR       (0x0A00 & MPTPR_PTP_MSK)
 630
 631 /*
 632  * Init Memory Controller:
 633  *
 634  * Bank Bus     Machine PortSz  Device
 635  * ---- ---     ------- ------  ------
 636  *  0   60x     GPCM    64 bit  FLASH (BGA - 16MB AMD AM29DL323DB90WDI)
 637  *  1   60x     SDRAM   64 bit  SDRAM (BGA - 64MB Micron 48LC8M16A2TG)
 638  *  2   Local   SDRAM   32 bit  SDRAM (BGA - 32MB Micron 48LC8M16A2TG)
 639  *  3   unused
 640  *  4   60x     GPCM     8 bit  Board Regs, NVRTC
 641  *  5   unused
 642  *  6   unused
 643  *  7   unused
 644  *  8   PCMCIA
 645  *  9   unused
 646  * 10   unused
 647  * 11   unused
 648 */
 649
 650 /*-----------------------------------------------------------------------
 651  * BRx - Base Register
 652  *     Ref: Section 10.3.1 on page 10-14
 653  * ORx - Option Register
 654  *     Ref: Section 10.3.2 on page 10-18
 655  *-----------------------------------------------------------------------
 656  */
 657
 658 /* Bank 0 - FLASH
 659  *
 660  */
 661 #define CFG_BR0_PRELIM  ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
 662                          BRx_PS_64                      |\
 663                          BRx_DECC_NONE                  |\
 664                          BRx_MS_GPCM_P                  |\
 665                          BRx_V)
 666
 667 #define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH0_SIZE)     |\
 668                          ORxG_CSNT                      |\
 669                          ORxG_ACS_DIV1                  |\
 670                          ORxG_SCY_8_CLK                 |\
 671                          ORxG_EHTR)
 672
 673 /* Bank 1 - SDRAM
 674  * PSDRAM
 675  */
 676 #define CFG_BR1_PRELIM  ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
 677                          BRx_PS_64                      |\
 678                          BRx_MS_SDRAM_P                 |\
 679                          BRx_V)
 680
 681 #define CFG_OR1_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE)     |\
 682                          ORxS_BPD_4                     |\
 683                          ORxS_ROWST_PBI1_A6             |\
 684                          ORxS_NUMR_12)
 685
 686 #ifdef CFG_EP8260_H2
 687 #define CFG_PSDMR       0xC34E246E
 688 #else
 689 #define CFG_PSDMR       0xC34E2462
 690 #endif
 691
 692 #define CFG_PSRT        0x64
 693
 694 #ifdef CFG_LSDRAM
 695 /* Bank 2 - SDRAM
 696  * LSDRAM
 697  */
 698
 699   #define CFG_BR2_PRELIM  ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
 700                            BRx_PS_32                      |\
 701                            BRx_MS_SDRAM_L                 |\
 702                            BRx_V)
 703
 704   #define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM1_SIZE)     |\
 705                            ORxS_BPD_4                     |\
 706                            ORxS_ROWST_PBI0_A9             |\
 707                            ORxS_NUMR_12)
 708
 709   #define CFG_LSDMR      0x416A2562
 710   #define CFG_LSRT      0x64
 711 #else
 712   #define CFG_LSRT      0x0
 713 #endif /* CFG_LSDRAM */
 714
 715 /* Bank 4 - On board registers
 716  * NVRTC and BCSR
 717  */
 718 #define CFG_BR4_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
 719                            BRx_PS_8                     |\
 720                            BRx_MS_GPCM_P                |\
 721                            BRx_V)
 722 /*
 723 #define CFG_OR4_PRELIM    (ORxG_AM_MSK                 |\
 724                            ORxG_CSNT                   |\
 725                            ORxG_ACS_DIV1               |\
 726                            ORxG_SCY_10_CLK              |\
 727                            ORxG_TRLX)
 728 */
 729 #define CFG_OR4_PRELIM 0xfff00854
 730
 731 #ifdef _NOT_USED_SINCE_NOT_WORKING_
 732 /* Bank 8 - On board registers
 733  * PCMCIA (currently not working!)
 734  */
 735 #define CFG_BR8_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
 736                            BRx_PS_16                     |\
 737                            BRx_MS_GPCM_P                |\
 738                            BRx_V)
 739
 740 #define CFG_OR8_PRELIM    (ORxG_AM_MSK                 |\
 741                            ORxG_CSNT                   |\
 742                            ORxG_ACS_DIV1               |\
 743                            ORxG_SETA                   |\
 744                            ORxG_SCY_10_CLK)
 745 #endif
 746
 747 /*
 748  * Internal Definitions
 749  *
 750  * Boot Flags
 751  */
 752 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
 753 #define BOOTFLAG_WARM   0x02    /* Software reboot                   */
 754
 755 /*
 756  * JFFS2 partitions
 757  *
 758  */
 759 /* No command line, one static partition, whole device */
 760 #undef CONFIG_JFFS2_CMDLINE
 761 #define CONFIG_JFFS2_DEV                "nor0"
 762 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 763 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 764
 765 /* mtdparts command line support */
 766 /* Note: fake mtd_id used, no linux mtd map file */
 767 /*
 768 #define CONFIG_JFFS2_CMDLINE
 769 #define MTDIDS_DEFAULT          ""
 770 #define MTDPARTS_DEFAULT        ""
 771 */
 772
 773 #endif  /* __CONFIG_H */