include/configs/ep8260.h

   1 /*
   2  * (C) Copyright 2002
   3  * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
   4  *
   5  * This file is based on similar values for other boards found in other
   6  * U-Boot config files, and some that I found in the EP8260 manual.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * board/config.h - configuration options, board specific
  29  *
  30  * "EP8260 H, V.1.1"
  31  *      - 64M 60x Bus SDRAM
  32  *      - 32M Local Bus SDRAM
  33  *      - 16M Flash (4 x AM29DL323DB90WDI)
  34  *      - 128k NVRAM with RTC
  35  *
  36  * "EP8260 H2, V.1.3" (CFG_EP8260_H2)
  37  *      - 300MHz/133MHz/66MHz
  38  *      - 64M 60x Bus SDRAM
  39  *      - 32M Local Bus SDRAM
  40  *      - 32M Flash
  41  *      - 128k NVRAM with RTC
  42  */
  43
  44 #ifndef __CONFIG_H
  45 #define __CONFIG_H
  46
  47 /* Define this to enable support the EP8260 H2 version */
  48 #define CFG_EP8260_H2   1
  49 /* #undef CFG_EP8260_H2  */
  50
  51 /* What is the oscillator's (UX2) frequency in Hz? */
  52 #define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
  53
  54 /*-----------------------------------------------------------------------
  55  * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
  56  *-----------------------------------------------------------------------
  57  * What should MODCK_H be? It is dependent on the oscillator
  58  * frequency, MODCK[1-3], and desired CPM and core frequencies.
  59  * Here are some example values (all frequencies are in MHz):
  60  *
  61  * MODCK_H   MODCK[1-3]  Osc    CPM    Core
  62  * -------   ----------  ---    ---    ----
  63  * 0x2       0x2         33     133    133
  64  * 0x2       0x3         33     133    166
  65  * 0x2       0x4         33     133    200
  66  * 0x2       0x5         33     133    233
  67  * 0x2       0x6         33     133    266
  68  *
  69  * 0x5       0x5         66     133    133
  70  * 0x5       0x6         66     133    166
  71  * 0x5       0x7         66     133    200 *
  72  * 0x6       0x0         66     133    233
  73  * 0x6       0x1         66     133    266
  74  * 0x6       0x2         66     133    300
  75  */
  76 #ifdef CFG_EP8260_H2
  77 #define CFG_SBC_MODCK_H  (HRCW_MODCK_H0110)
  78 #else
  79 #define CFG_SBC_MODCK_H  (HRCW_MODCK_H0110)
  80 #endif
  81
  82 /* Define this if you want to boot from 0x00000100. If you don't define
  83  * this, you will need to program the bootloader to 0xfff00000, and
  84  * get the hardware reset config words at 0xfe000000. The simplest
  85  * way to do that is to program the bootloader at both addresses.
  86  * It is suggested that you just let U-Boot live at 0x00000000.
  87  */
  88 /* #define CFG_SBC_BOOT_LOW 1 */        /* only for HRCW */
  89 /* #undef CFG_SBC_BOOT_LOW */
  90
  91 /* The reset command will not work as expected if the reset address does
  92  * not point to the correct address.
  93  */
  94
  95 #define CFG_RESET_ADDRESS       0xFFF00100
  96
  97 /* What should the base address of the main FLASH be and how big is
  98  * it (in MBytes)? This must contain TEXT_BASE from board/ep8260/config.mk
  99  * The main FLASH is whichever is connected to *CS0. U-Boot expects
 100  * this to be the SIMM.
 101  */
 102 #ifdef CFG_EP8260_H2
 103 #define CFG_FLASH0_BASE 0xFE000000
 104 #define CFG_FLASH0_SIZE 32
 105 #else
 106 #define CFG_FLASH0_BASE 0xFF000000
 107 #define CFG_FLASH0_SIZE 16
 108 #endif
 109
 110 /* What should the base address of the secondary FLASH be and how big
 111  * is it (in Mbytes)? The secondary FLASH is whichever is connected
 112  * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
 113  * want it enabled, don't define these constants.
 114  */
 115 #define CFG_FLASH1_BASE 0
 116 #define CFG_FLASH1_SIZE 0
 117 #undef CFG_FLASH1_BASE
 118 #undef CFG_FLASH1_SIZE
 119
 120 /* What should be the base address of SDRAM DIMM (60x bus) and how big is
 121  * it (in Mbytes)?
 122 */
 123 #define CFG_SDRAM0_BASE 0x00000000
 124 #define CFG_SDRAM0_SIZE 64
 125
 126 /* define CFG_LSDRAM if you want to enable the 32M SDRAM on the
 127  * local bus (8260 local bus is NOT cacheable!)
 128 */
 129 /* #define CFG_LSDRAM */
 130 #undef CFG_LSDRAM
 131
 132 #ifdef CFG_LSDRAM
 133 /* What should be the base address of SDRAM DIMM (local bus) and how big is
 134  * it (in Mbytes)?
 135 */
 136   #define CFG_SDRAM1_BASE 0x04000000
 137   #define CFG_SDRAM1_SIZE 32
 138 #else
 139   #define CFG_SDRAM1_BASE 0
 140   #define CFG_SDRAM1_SIZE 0
 141   #undef CFG_SDRAM1_BASE
 142   #undef CFG_SDRAM1_SIZE
 143 #endif /* CFG_LSDRAM */
 144
 145 /* What should be the base address of NVRAM and how big is
 146  * it (in Bytes)
 147  */
 148 #define CFG_NVRAM_BASE_ADDR  0xFA080000
 149 #define CFG_NVRAM_SIZE       (128*1024)-16
 150
 151 /* The RTC is a Dallas DS1556
 152  */
 153 #define CONFIG_RTC_DS1556
 154
 155 /* What should be the base address of the LEDs and switch S0?
 156  * If you don't want them enabled, don't define this.
 157  */
 158 #define CFG_LED_BASE 0x00000000
 159 #undef CFG_LED_BASE
 160
 161 /*
 162  * select serial console configuration
 163  *
 164  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 165  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 166  * for SCC).
 167  *
 168  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 169  * defined elsewhere.
 170  */
 171 #define CONFIG_CONS_ON_SMC          /* define if console on SMC */
 172 #undef  CONFIG_CONS_ON_SCC          /* define if console on SCC */
 173 #undef  CONFIG_CONS_NONE            /* define if console on neither */
 174 #define CONFIG_CONS_INDEX    1      /* which SMC/SCC channel for console */
 175
 176 /*
 177  * select ethernet configuration
 178  *
 179  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 180  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 181  * for FCC)
 182  *
 183  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 184  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
 185  * from CONFIG_COMMANDS to remove support for networking.
 186  */
 187 #undef  CONFIG_ETHER_ON_SCC           /* define if ethernet on SCC    */
 188 #define CONFIG_ETHER_ON_FCC           /* define if ethernet on FCC    */
 189 #undef  CONFIG_ETHER_NONE             /* define if ethernet on neither */
 190 #define CONFIG_ETHER_INDEX      3     /* which SCC/FCC channel for ethernet */
 191
 192 #if ( CONFIG_ETHER_INDEX == 3 )
 193
 194 /*
 195  * - Rx-CLK is CLK15
 196  * - Tx-CLK is CLK16
 197  * - RAM for BD/Buffers is on the local Bus (see 28-13)
 198  * - Enable Half Duplex in FSMR
 199  */
 200 # define CFG_CMXFCR_MASK        (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
 201 # define CFG_CMXFCR_VALUE       (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
 202
 203 /*
 204  * - RAM for BD/Buffers is on the local Bus (see 28-13)
 205  */
 206 #ifdef CFG_LSDRAM
 207   #define CFG_CPMFCR_RAMTYPE    3
 208 #else /* CFG_LSDRAM */
 209   #define CFG_CPMFCR_RAMTYPE    0
 210 #endif /* CFG_LSDRAM */
 211
 212 /* - Enable Half Duplex in FSMR */
 213 /* # define CFG_FCC_PSMR                (FCC_PSMR_FDE|FCC_PSMR_LPB) */
 214 # define CFG_FCC_PSMR           0
 215
 216 #else /* CONFIG_ETHER_INDEX */
 217 # error "on EP8260 ethernet must be FCC3"
 218 #endif /* CONFIG_ETHER_INDEX */
 219
 220 /*
 221  * select i2c support configuration
 222  *
 223  * Supported configurations are {none, software, hardware} drivers.
 224  * If the software driver is chosen, there are some additional
 225  * configuration items that the driver uses to drive the port pins.
 226  */
 227 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 228 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 229 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 230 #define CFG_I2C_SLAVE           0x7F
 231
 232 /*
 233  * Software (bit-bang) I2C driver configuration
 234  */
 235 #ifdef CONFIG_SOFT_I2C
 236 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 237 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 238 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 239 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 240 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 241                         else    iop->pdat &= ~0x00010000
 242 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 243                         else    iop->pdat &= ~0x00020000
 244 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 245 #endif /* CONFIG_SOFT_I2C */
 246
 247 /* #define CONFIG_RTC_DS174x */
 248
 249 /* Define this to reserve an entire FLASH sector (256 KB) for
 250  * environment variables. Otherwise, the environment will be
 251  * put in the same sector as U-Boot, and changing variables
 252  * will erase U-Boot temporarily
 253  */
 254 #define CFG_ENV_IN_OWN_SECT
 255
 256 /* Define to allow the user to overwrite serial and ethaddr */
 257 #define CONFIG_ENV_OVERWRITE
 258
 259 /* What should the console's baud rate be? */
 260 #ifdef CFG_EP8260_H2
 261 #define CONFIG_BAUDRATE         9600
 262 #else
 263 #define CONFIG_BAUDRATE         115200
 264 #endif
 265
 266 /* Ethernet MAC address */
 267 #define CONFIG_ETHADDR          00:10:EC:00:30:8C
 268
 269 #define CONFIG_IPADDR           192.168.254.130
 270 #define CONFIG_SERVERIP         192.168.254.49
 271
 272 /* Set to a positive value to delay for running BOOTCOMMAND */
 273 #define CONFIG_BOOTDELAY        -1
 274
 275 /* undef this to save memory */
 276 #define CFG_LONGHELP
 277
 278 /* Monitor Command Prompt       */
 279 #define CFG_PROMPT              "=> "
 280
 281 /* Define this variable to enable the "hush" shell (from
 282    Busybox) as command line interpreter, thus enabling
 283    powerful command line syntax like
 284    if...then...else...fi conditionals or `&&' and '||'
 285    constructs ("shell scripts").
 286    If undefined, you get the old, much simpler behaviour
 287    with a somewhat smapper memory footprint.
 288 */
 289 #define CFG_HUSH_PARSER
 290 #define CFG_PROMPT_HUSH_PS2     "> "
 291
 292 /* What U-Boot subsytems do you want enabled? */
 293 /*
 294 */
 295 #define CONFIG_COMMANDS         ( CFG_CMD_ALL     & \
 296                                   ~(    CFG_CMD_BMP     | \
 297                                         CFG_CMD_BSP     | \
 298                                         CFG_CMD_DCR     | \
 299                                         CFG_CMD_DHCP    | \
 300                                         CFG_CMD_DOC     | \
 301                                         CFG_CMD_DTT     | \
 302                                         CFG_CMD_EEPROM  | \
 303                                         CFG_CMD_EXT2    | \
 304                                         CFG_CMD_FDC     | \
 305                                         CFG_CMD_FDOS    | \
 306                                         CFG_CMD_HWFLOW  | \
 307                                         CFG_CMD_IDE     | \
 308                                         CFG_CMD_JFFS2   | \
 309                                         CFG_CMD_KGDB    | \
 310                                         CFG_CMD_MII     | \
 311                                         CFG_CMD_MMC     | \
 312                                         CFG_CMD_NAND    | \
 313                                         CFG_CMD_PCI     | \
 314                                         CFG_CMD_PCMCIA  | \
 315                                         CFG_CMD_REISER  | \
 316                                         CFG_CMD_SCSI    | \
 317                                         CFG_CMD_SPI     | \
 318                                         CFG_CMD_UNIVERSE| \
 319                                         CFG_CMD_USB     | \
 320                                         CFG_CMD_VFD     | \
 321                                         CFG_CMD_XIMG    ) )
 322
 323
 324 /* Where do the internal registers live? */
 325 #define CFG_IMMR               0xF0000000
 326 #define CFG_DEFAULT_IMMR       0x00010000
 327
 328 /* Where do the on board registers (CS4) live? */
 329 #define CFG_REGS_BASE          0xFA000000
 330
 331 /*****************************************************************************
 332  *
 333  * You should not have to modify any of the following settings
 334  *
 335  *****************************************************************************/
 336
 337 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
 338 #define CONFIG_EP8260           11      /* on an Embedded Planet EP8260 Board, Rev. 11 */
 339
 340 #define CONFIG_BOARD_EARLY_INIT_F 1         /* Call board_early_init_f  */
 341
 342 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 343 #include <cmd_confdefs.h>
 344
 345 /*
 346  * Miscellaneous configurable options
 347  */
 348 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 349 #  define CFG_CBSIZE              1024       /* Console I/O Buffer Size      */
 350 #else
 351 #  define CFG_CBSIZE              256        /* Console I/O Buffer Size      */
 352 #endif
 353
 354 /* Print Buffer Size */
 355 #define CFG_PBSIZE        (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
 356
 357 #define CFG_MAXARGS       8            /* max number of command args   */
 358
 359 #define CFG_BARGSIZE      CFG_CBSIZE   /* Boot Argument Buffer Size    */
 360
 361 #ifdef CFG_LSDRAM
 362   #define CFG_MEMTEST_START 0x04000000   /* memtest works on  */
 363   #define CFG_MEMTEST_END   0x06000000   /* 64-96 MB in SDRAM */
 364 #else
 365   #define CFG_MEMTEST_START 0x00000000   /* memtest works on  */
 366   #define CFG_MEMTEST_END   0x02000000   /* 0-32 MB in SDRAM */
 367 #endif /* CFG_LSDRAM */
 368
 369 #define CONFIG_CLOCKS_IN_MHZ    1      /* clocks passsed to Linux in MHz */
 370
 371 #define CFG_LOAD_ADDR     0x00100000   /* default load address */
 372 #define CFG_TFTP_LOADADDR 0x00100000   /* default load address for network file downloads */
 373
 374 #define CFG_HZ            1000         /* decrementer freq: 1 ms ticks */
 375
 376 /* valid baudrates */
 377 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 378
 379 /*
 380  * Low Level Configuration Settings
 381  * (address mappings, register initial values, etc.)
 382  * You should know what you are doing if you make changes here.
 383  */
 384
 385 #define CFG_FLASH_BASE    CFG_FLASH0_BASE
 386 #define CFG_SDRAM_BASE    CFG_SDRAM0_BASE
 387
 388 /*-----------------------------------------------------------------------
 389  * Hard Reset Configuration Words
 390  */
 391
 392 #if defined(CFG_SBC_BOOT_LOW)
 393 #  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 394 #else
 395 #  define  CFG_SBC_HRCW_BOOT_FLAGS  (0x00000000)
 396 #endif /* defined(CFG_SBC_BOOT_LOW) */
 397
 398 #ifdef CFG_EP8260_H2
 399 /* get the HRCW ISB field from CFG_DEFAULT_IMMR */
 400 #define CFG_SBC_HRCW_IMMR ( ((CFG_DEFAULT_IMMR & 0x10000000) >> 10) |\
 401                             ((CFG_DEFAULT_IMMR & 0x01000000) >> 7)  |\
 402                             ((CFG_DEFAULT_IMMR & 0x00100000) >> 4) )
 403
 404 #define CFG_HRCW_MASTER (HRCW_EBM                |\
 405                          HRCW_L2CPC01            |\
 406                          CFG_SBC_HRCW_IMMR       |\
 407                          HRCW_APPC10             |\
 408                          HRCW_CS10PC01           |\
 409                          CFG_SBC_MODCK_H         |\
 410                          CFG_SBC_HRCW_BOOT_FLAGS)
 411 #else
 412 #define CFG_HRCW_MASTER 0x10400245
 413 #endif
 414
 415 /* no slaves */
 416 #define CFG_HRCW_SLAVE1 0
 417 #define CFG_HRCW_SLAVE2 0
 418 #define CFG_HRCW_SLAVE3 0
 419 #define CFG_HRCW_SLAVE4 0
 420 #define CFG_HRCW_SLAVE5 0
 421 #define CFG_HRCW_SLAVE6 0
 422 #define CFG_HRCW_SLAVE7 0
 423
 424 /*-----------------------------------------------------------------------
 425  * Definitions for initial stack pointer and data area (in DPRAM)
 426  */
 427 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 428 #define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
 429 #define CFG_GBL_DATA_SIZE      128     /* bytes reserved for initial data */
 430 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 431 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 432
 433 /*-----------------------------------------------------------------------
 434  * Start addresses for the final memory configuration
 435  * (Set up by the startup code)
 436  * Please note that CFG_SDRAM_BASE _must_ start at 0
 437  * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
 438  */
 439 #define CFG_MONITOR_BASE          TEXT_BASE
 440
 441
 442 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 443 #  define CFG_RAMBOOT
 444 #endif
 445
 446 #define CFG_MONITOR_LEN      (256 << 10)     /* Reserve 256 kB for Monitor   */
 447 #define CFG_MALLOC_LEN       (128 << 10)     /* Reserve 128 kB for malloc()  */
 448
 449 /*
 450  * For booting Linux, the board info and command line data
 451  * have to be in the first 8 MB of memory, since this is
 452  * the maximum mapped by the Linux kernel during initialization.
 453  */
 454 #define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 455
 456 /*-----------------------------------------------------------------------
 457  * FLASH and environment organization
 458  */
 459 #define CFG_MAX_FLASH_BANKS   1       /* max number of memory banks         */
 460 #ifdef CFG_EP8260_H2
 461 #define CFG_MAX_FLASH_SECT    128      /* max number of sectors on one chip  */
 462 #else
 463 #define CFG_MAX_FLASH_SECT    71      /* max number of sectors on one chip  */
 464 #endif
 465
 466 #define CFG_FLASH_ERASE_TOUT  8000    /* Timeout for Flash Erase (in ms)    */
 467 #define CFG_FLASH_WRITE_TOUT  1       /* Timeout for Flash Write (in ms)    */
 468
 469 #ifndef CFG_RAMBOOT
 470 #  define CFG_ENV_IS_IN_FLASH  1
 471
 472 #  ifdef CFG_ENV_IN_OWN_SECT
 473 #    define CFG_ENV_ADDR       (CFG_MONITOR_BASE + 0x40000)
 474 #    define CFG_ENV_SECT_SIZE  0x40000
 475 #  else
 476 #    define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
 477 #    define CFG_ENV_SIZE       0x1000  /* Total Size of Environment Sector */
 478 #    define CFG_ENV_SECT_SIZE  0x10000 /* see README - env sect real size */
 479 #  endif /* CFG_ENV_IN_OWN_SECT */
 480 #else
 481 #  define CFG_ENV_IS_IN_NVRAM  1
 482 #  define CFG_ENV_ADDR         (CFG_MONITOR_BASE - 0x1000)
 483 #  define CFG_ENV_SIZE         0x200
 484 #endif /* CFG_RAMBOOT */
 485
 486 /*-----------------------------------------------------------------------
 487  * Cache Configuration
 488  */
 489 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU */
 490
 491 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 492 #  define CFG_CACHELINE_SHIFT     5     /* log base 2 of the above value */
 493 #endif
 494
 495 /*-----------------------------------------------------------------------
 496  * HIDx - Hardware Implementation-dependent Registers                    2-11
 497  *-----------------------------------------------------------------------
 498  * HID0 also contains cache control - initially enable both caches and
 499  * invalidate contents, then the final state leaves only the instruction
 500  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 501  * but Soft reset does not.
 502  *
 503  * HID1 has only read-only information - nothing to set.
 504  */
 505 #define CFG_HID0_INIT   (HID0_ICE  |\
 506                          HID0_DCE  |\
 507                          HID0_ICFI |\
 508                          HID0_DCI  |\
 509                          HID0_IFEM |\
 510                          HID0_ABE)
 511 #ifdef CFG_LSDRAM
 512 /* 8260 local bus is NOT cacheable */
 513 #define CFG_HID0_FINAL  (/*HID0_ICE  |*/\
 514                          HID0_IFEM |\
 515                          HID0_ABE  |\
 516                          HID0_EMCP)
 517 #else /* !CFG_LSDRAM */
 518 #define CFG_HID0_FINAL  (HID0_ICE  |\
 519                          HID0_IFEM |\
 520                          HID0_ABE  |\
 521                          HID0_EMCP)
 522 #endif /* CFG_LSDRAM */
 523
 524 #define CFG_HID2        0
 525
 526 /*-----------------------------------------------------------------------
 527  * RMR - Reset Mode Register
 528  *-----------------------------------------------------------------------
 529  */
 530 #define CFG_RMR         0
 531
 532 /*-----------------------------------------------------------------------
 533  * BCR - Bus Configuration                                       4-25
 534  *-----------------------------------------------------------------------
 535  */
 536 #define CFG_BCR         (BCR_EBM   |\
 537                          BCR_PLDP  |\
 538                          BCR_EAV   |\
 539                          BCR_NPQM0)
 540
 541 /*-----------------------------------------------------------------------
 542  * SIUMCR - SIU Module Configuration                             4-31
 543  *-----------------------------------------------------------------------
 544  */
 545 #define CFG_SIUMCR      (SIUMCR_L2CPC01 |\
 546                          SIUMCR_APPC10  |\
 547                          SIUMCR_CS10PC01)
 548
 549 /*-----------------------------------------------------------------------
 550  * SYPCR - System Protection Control                            11-9
 551  * SYPCR can only be written once after reset!
 552  *-----------------------------------------------------------------------
 553  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 554  */
 555 #ifdef CFG_EP8260_H2
 556 /* TBD: Find out why setting the BMT to 0xff causes the FCC to
 557  * generate TX buffer underrun errors for large packets under
 558  * Linux
 559  */
 560 #define CFG_SYPCR_BMT   0x00000600
 561 #else
 562 #define CFG_SYPCR_BMT   SYPCR_BMT
 563 #endif
 564
 565 #ifdef CFG_LSDRAM
 566 #define CFG_SYPCR       (SYPCR_SWTC |\
 567                          CFG_SYPCR_BMT  |\
 568                          SYPCR_PBME |\
 569                          SYPCR_LBME |\
 570                          SYPCR_SWP)
 571 #else
 572 #define CFG_SYPCR       (SYPCR_SWTC |\
 573                          CFG_SYPCR_BMT  |\
 574                          SYPCR_PBME |\
 575                          SYPCR_SWP)
 576 #endif
 577
 578 /*-----------------------------------------------------------------------
 579  * TMCNTSC - Time Counter Status and Control                     4-40
 580  *-----------------------------------------------------------------------
 581  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 582  * and enable Time Counter
 583  */
 584 #define CFG_TMCNTSC     (TMCNTSC_SEC |\
 585                          TMCNTSC_ALR |\
 586                          TMCNTSC_TCF |\
 587                          TMCNTSC_TCE)
 588
 589 /*-----------------------------------------------------------------------
 590  * PISCR - Periodic Interrupt Status and Control                 4-42
 591  *-----------------------------------------------------------------------
 592  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 593  * Periodic timer
 594  */
 595 #ifdef CFG_EP8260_H2
 596 #define CFG_PISCR       (PISCR_PS  |\
 597                          PISCR_PTF |\
 598                          PISCR_PTE)
 599 #else
 600 #define CFG_PISCR       0
 601 #endif
 602
 603 /*-----------------------------------------------------------------------
 604  * SCCR - System Clock Control                                   9-8
 605  *-----------------------------------------------------------------------
 606  */
 607 #define CFG_SCCR        (SCCR_DFBRG01)
 608
 609 /*-----------------------------------------------------------------------
 610  * RCCR - RISC Controller Configuration                         13-7
 611  *-----------------------------------------------------------------------
 612  */
 613 #define CFG_RCCR        0
 614
 615 /*-----------------------------------------------------------------------
 616  * MPTPR - Memory Refresh Timer Prescale Register               10-32
 617  *-----------------------------------------------------------------------
 618  */
 619 #define CFG_MPTPR       (0x0A00 & MPTPR_PTP_MSK)
 620
 621 /*
 622  * Init Memory Controller:
 623  *
 624  * Bank Bus     Machine PortSz  Device
 625  * ---- ---     ------- ------  ------
 626  *  0   60x     GPCM    64 bit  FLASH (BGA - 16MB AMD AM29DL323DB90WDI)
 627  *  1   60x     SDRAM   64 bit  SDRAM (BGA - 64MB Micron 48LC8M16A2TG)
 628  *  2   Local   SDRAM   32 bit  SDRAM (BGA - 32MB Micron 48LC8M16A2TG)
 629  *  3   unused
 630  *  4   60x     GPCM     8 bit  Board Regs, NVRTC
 631  *  5   unused
 632  *  6   unused
 633  *  7   unused
 634  *  8   PCMCIA
 635  *  9   unused
 636  * 10   unused
 637  * 11   unused
 638 */
 639
 640 /*-----------------------------------------------------------------------
 641  * BRx - Base Register
 642  *     Ref: Section 10.3.1 on page 10-14
 643  * ORx - Option Register
 644  *     Ref: Section 10.3.2 on page 10-18
 645  *-----------------------------------------------------------------------
 646  */
 647
 648 /* Bank 0 - FLASH
 649  *
 650  */
 651 #define CFG_BR0_PRELIM  ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
 652                          BRx_PS_64                      |\
 653                          BRx_DECC_NONE                  |\
 654                          BRx_MS_GPCM_P                  |\
 655                          BRx_V)
 656
 657 #define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH0_SIZE)     |\
 658                          ORxG_CSNT                      |\
 659                          ORxG_ACS_DIV1                  |\
 660                          ORxG_SCY_8_CLK                 |\
 661                          ORxG_EHTR)
 662
 663 /* Bank 1 - SDRAM
 664  * PSDRAM
 665  */
 666 #define CFG_BR1_PRELIM  ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
 667                          BRx_PS_64                      |\
 668                          BRx_MS_SDRAM_P                 |\
 669                          BRx_V)
 670
 671 #define CFG_OR1_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE)     |\
 672                          ORxS_BPD_4                     |\
 673                          ORxS_ROWST_PBI1_A6             |\
 674                          ORxS_NUMR_12)
 675
 676 #ifdef CFG_EP8260_H2
 677 #define CFG_PSDMR       0xC34E246E
 678 #else
 679 #define CFG_PSDMR       0xC34E2462
 680 #endif
 681
 682 #define CFG_PSRT        0x64
 683
 684 #ifdef CFG_LSDRAM
 685 /* Bank 2 - SDRAM
 686  * LSDRAM
 687  */
 688
 689   #define CFG_BR2_PRELIM  ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
 690                            BRx_PS_32                      |\
 691                            BRx_MS_SDRAM_L                 |\
 692                            BRx_V)
 693
 694   #define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM1_SIZE)     |\
 695                            ORxS_BPD_4                     |\
 696                            ORxS_ROWST_PBI0_A9             |\
 697                            ORxS_NUMR_12)
 698
 699   #define CFG_LSDMR      0x416A2562
 700   #define CFG_LSRT      0x64
 701 #else
 702   #define CFG_LSRT      0x0
 703 #endif /* CFG_LSDRAM */
 704
 705 /* Bank 4 - On board registers
 706  * NVRTC and BCSR
 707  */
 708 #define CFG_BR4_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
 709                            BRx_PS_8                     |\
 710                            BRx_MS_GPCM_P                |\
 711                            BRx_V)
 712 /*
 713 #define CFG_OR4_PRELIM    (ORxG_AM_MSK                 |\
 714                            ORxG_CSNT                   |\
 715                            ORxG_ACS_DIV1               |\
 716                            ORxG_SCY_10_CLK              |\
 717                            ORxG_TRLX)
 718 */
 719 #define CFG_OR4_PRELIM 0xfff00854
 720
 721 #ifdef _NOT_USED_SINCE_NOT_WORKING_
 722 /* Bank 8 - On board registers
 723  * PCMCIA (currently not working!)
 724  */
 725 #define CFG_BR8_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
 726                            BRx_PS_16                     |\
 727                            BRx_MS_GPCM_P                |\
 728                            BRx_V)
 729
 730 #define CFG_OR8_PRELIM    (ORxG_AM_MSK                 |\
 731                            ORxG_CSNT                   |\
 732                            ORxG_ACS_DIV1               |\
 733                            ORxG_SETA                   |\
 734                            ORxG_SCY_10_CLK)
 735 #endif
 736
 737 /*
 738  * Internal Definitions
 739  *
 740  * Boot Flags
 741  */
 742 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
 743 #define BOOTFLAG_WARM   0x02    /* Software reboot                   */
 744
 745 #endif  /* __CONFIG_H */