include/configs/ep8260.h

   1 /*
   2  * (C) Copyright 2002
   3  * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
   4  *
   5  * This file is based on similar values for other boards found in other
   6  * U-Boot config files, and some that I found in the EP8260 manual.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * board/config.h - configuration options, board specific
  29  *
  30  * "EP8260 H, V.1.1"
  31  *      - 64M 60x Bus SDRAM
  32  *      - 32M Local Bus SDRAM
  33  *      - 16M Flash (4 x AM29DL323DB90WDI)
  34  *      - 128k NVRAM with RTC
  35  *
  36  * "EP8260 H2, V.1.3" (CONFIG_SYS_EP8260_H2)
  37  *      - 300MHz/133MHz/66MHz
  38  *      - 64M 60x Bus SDRAM
  39  *      - 32M Local Bus SDRAM
  40  *      - 32M Flash
  41  *      - 128k NVRAM with RTC
  42  */
  43
  44 #ifndef __CONFIG_H
  45 #define __CONFIG_H
  46
  47 /* Define this to enable support the EP8260 H2 version */
  48 #define CONFIG_SYS_EP8260_H2    1
  49 /* #undef CONFIG_SYS_EP8260_H2  */
  50
  51 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  52
  53 #define CONFIG_CPM2             1       /* Has a CPM2 */
  54
  55 /* What is the oscillator's (UX2) frequency in Hz? */
  56 #define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
  57
  58 /*-----------------------------------------------------------------------
  59  * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
  60  *-----------------------------------------------------------------------
  61  * What should MODCK_H be? It is dependent on the oscillator
  62  * frequency, MODCK[1-3], and desired CPM and core frequencies.
  63  * Here are some example values (all frequencies are in MHz):
  64  *
  65  * MODCK_H   MODCK[1-3]  Osc    CPM    Core
  66  * -------   ----------  ---    ---    ----
  67  * 0x2       0x2         33     133    133
  68  * 0x2       0x3         33     133    166
  69  * 0x2       0x4         33     133    200
  70  * 0x2       0x5         33     133    233
  71  * 0x2       0x6         33     133    266
  72  *
  73  * 0x5       0x5         66     133    133
  74  * 0x5       0x6         66     133    166
  75  * 0x5       0x7         66     133    200 *
  76  * 0x6       0x0         66     133    233
  77  * 0x6       0x1         66     133    266
  78  * 0x6       0x2         66     133    300
  79  */
  80 #ifdef CONFIG_SYS_EP8260_H2
  81 #define CONFIG_SYS_SBC_MODCK_H  (HRCW_MODCK_H0110)
  82 #else
  83 #define CONFIG_SYS_SBC_MODCK_H  (HRCW_MODCK_H0110)
  84 #endif
  85
  86 /* Define this if you want to boot from 0x00000100. If you don't define
  87  * this, you will need to program the bootloader to 0xfff00000, and
  88  * get the hardware reset config words at 0xfe000000. The simplest
  89  * way to do that is to program the bootloader at both addresses.
  90  * It is suggested that you just let U-Boot live at 0x00000000.
  91  */
  92 /* #define CONFIG_SYS_SBC_BOOT_LOW 1 */ /* only for HRCW */
  93 /* #undef CONFIG_SYS_SBC_BOOT_LOW */
  94
  95 /* The reset command will not work as expected if the reset address does
  96  * not point to the correct address.
  97  */
  98
  99 #define CONFIG_SYS_RESET_ADDRESS        0xFFF00100
 100
 101 /* What should the base address of the main FLASH be and how big is
 102  * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ep8260/config.mk
 103  * The main FLASH is whichever is connected to *CS0. U-Boot expects
 104  * this to be the SIMM.
 105  */
 106 #ifdef CONFIG_SYS_EP8260_H2
 107 #define CONFIG_SYS_FLASH0_BASE 0xFE000000
 108 #define CONFIG_SYS_FLASH0_SIZE 32
 109 #else
 110 #define CONFIG_SYS_FLASH0_BASE 0xFF000000
 111 #define CONFIG_SYS_FLASH0_SIZE 16
 112 #endif
 113
 114 /* What should the base address of the secondary FLASH be and how big
 115  * is it (in Mbytes)? The secondary FLASH is whichever is connected
 116  * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
 117  * want it enabled, don't define these constants.
 118  */
 119 #define CONFIG_SYS_FLASH1_BASE 0
 120 #define CONFIG_SYS_FLASH1_SIZE 0
 121 #undef CONFIG_SYS_FLASH1_BASE
 122 #undef CONFIG_SYS_FLASH1_SIZE
 123
 124 /* What should be the base address of SDRAM DIMM (60x bus) and how big is
 125  * it (in Mbytes)?
 126 */
 127 #define CONFIG_SYS_SDRAM0_BASE 0x00000000
 128 #define CONFIG_SYS_SDRAM0_SIZE 64
 129
 130 /* define CONFIG_SYS_LSDRAM if you want to enable the 32M SDRAM on the
 131  * local bus (8260 local bus is NOT cacheable!)
 132 */
 133 /* #define CONFIG_SYS_LSDRAM */
 134 #undef CONFIG_SYS_LSDRAM
 135
 136 #ifdef CONFIG_SYS_LSDRAM
 137 /* What should be the base address of SDRAM DIMM (local bus) and how big is
 138  * it (in Mbytes)?
 139 */
 140   #define CONFIG_SYS_SDRAM1_BASE 0x04000000
 141   #define CONFIG_SYS_SDRAM1_SIZE 32
 142 #else
 143   #define CONFIG_SYS_SDRAM1_BASE 0
 144   #define CONFIG_SYS_SDRAM1_SIZE 0
 145   #undef CONFIG_SYS_SDRAM1_BASE
 146   #undef CONFIG_SYS_SDRAM1_SIZE
 147 #endif /* CONFIG_SYS_LSDRAM */
 148
 149 /* What should be the base address of NVRAM and how big is
 150  * it (in Bytes)
 151  */
 152 #define CONFIG_SYS_NVRAM_BASE_ADDR  0xFA080000
 153 #define CONFIG_SYS_NVRAM_SIZE       (128*1024)-16
 154
 155 /* The RTC is a Dallas DS1556
 156  */
 157 #define CONFIG_RTC_DS1556
 158
 159 /* What should be the base address of the LEDs and switch S0?
 160  * If you don't want them enabled, don't define this.
 161  */
 162 #define CONFIG_SYS_LED_BASE 0x00000000
 163 #undef CONFIG_SYS_LED_BASE
 164
 165 /*
 166  * select serial console configuration
 167  *
 168  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 169  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 170  * for SCC).
 171  *
 172  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 173  * defined elsewhere.
 174  */
 175 #define CONFIG_CONS_ON_SMC          /* define if console on SMC */
 176 #undef  CONFIG_CONS_ON_SCC          /* define if console on SCC */
 177 #undef  CONFIG_CONS_NONE            /* define if console on neither */
 178 #define CONFIG_CONS_INDEX    1      /* which SMC/SCC channel for console */
 179
 180 /*
 181  * select ethernet configuration
 182  *
 183  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 184  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 185  * for FCC)
 186  *
 187  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 188  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 189  */
 190 #undef  CONFIG_ETHER_ON_SCC           /* define if ethernet on SCC    */
 191 #define CONFIG_ETHER_ON_FCC           /* define if ethernet on FCC    */
 192 #undef  CONFIG_ETHER_NONE             /* define if ethernet on neither */
 193 #define CONFIG_ETHER_INDEX      3     /* which SCC/FCC channel for ethernet */
 194
 195 #if ( CONFIG_ETHER_INDEX == 3 )
 196
 197 /*
 198  * - Rx-CLK is CLK15
 199  * - Tx-CLK is CLK16
 200  * - RAM for BD/Buffers is on the local Bus (see 28-13)
 201  * - Enable Half Duplex in FSMR
 202  */
 203 # define CONFIG_SYS_CMXFCR_MASK3        (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
 204 # define CONFIG_SYS_CMXFCR_VALUE3       (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
 205
 206 /*
 207  * - RAM for BD/Buffers is on the local Bus (see 28-13)
 208  */
 209 #ifdef CONFIG_SYS_LSDRAM
 210   #define CONFIG_SYS_CPMFCR_RAMTYPE     3
 211 #else /* CONFIG_SYS_LSDRAM */
 212   #define CONFIG_SYS_CPMFCR_RAMTYPE     0
 213 #endif /* CONFIG_SYS_LSDRAM */
 214
 215 /* - Enable Half Duplex in FSMR */
 216 /* # define CONFIG_SYS_FCC_PSMR         (FCC_PSMR_FDE|FCC_PSMR_LPB) */
 217 # define CONFIG_SYS_FCC_PSMR            0
 218
 219 #else /* CONFIG_ETHER_INDEX */
 220 # error "on EP8260 ethernet must be FCC3"
 221 #endif /* CONFIG_ETHER_INDEX */
 222
 223 /*
 224  * select i2c support configuration
 225  *
 226  * Supported configurations are {none, software, hardware} drivers.
 227  * If the software driver is chosen, there are some additional
 228  * configuration items that the driver uses to drive the port pins.
 229  */
 230 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
 231
 232 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
 233 #define CONFIG_SYS_I2C_SLAVE            0x7F    /* This is for HARD, must go */
 234
 235 /*
 236  * Software (bit-bang) I2C driver configuration
 237  */
 238 #ifdef CONFIG_SYS_I2C_SOFT
 239 #define CONFIG_SYS_I2C
 240 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
 241 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
 242 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 243 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 244 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 245 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 246 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 247                         else    iop->pdat &= ~0x00010000
 248 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 249                         else    iop->pdat &= ~0x00020000
 250 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 251 #endif /* CONFIG_SYS_I2C_SOFT */
 252
 253 /* #define CONFIG_RTC_DS174x */
 254
 255 /* Define this to reserve an entire FLASH sector (256 KB) for
 256  * environment variables. Otherwise, the environment will be
 257  * put in the same sector as U-Boot, and changing variables
 258  * will erase U-Boot temporarily
 259  */
 260 #define CONFIG_ENV_IN_OWN_SECT
 261
 262 /* Define to allow the user to overwrite serial and ethaddr */
 263 #define CONFIG_ENV_OVERWRITE
 264
 265 /* What should the console's baud rate be? */
 266 #ifdef CONFIG_SYS_EP8260_H2
 267 #define CONFIG_BAUDRATE         9600
 268 #else
 269 #define CONFIG_BAUDRATE         115200
 270 #endif
 271
 272 /* Ethernet MAC address */
 273 #define CONFIG_ETHADDR          00:10:EC:00:30:8C
 274
 275 #define CONFIG_IPADDR           192.168.254.130
 276 #define CONFIG_SERVERIP         192.168.254.49
 277
 278 /* Set to a positive value to delay for running BOOTCOMMAND */
 279 #define CONFIG_BOOTDELAY        -1
 280
 281 /* undef this to save memory */
 282 #define CONFIG_SYS_LONGHELP
 283
 284 /* Monitor Command Prompt       */
 285 #define CONFIG_SYS_PROMPT              "=> "
 286
 287 /* Define this variable to enable the "hush" shell (from
 288    Busybox) as command line interpreter, thus enabling
 289    powerful command line syntax like
 290    if...then...else...fi conditionals or `&&' and '||'
 291    constructs ("shell scripts").
 292    If undefined, you get the old, much simpler behaviour
 293    with a somewhat smapper memory footprint.
 294 */
 295 #define CONFIG_SYS_HUSH_PARSER
 296
 297
 298 /*
 299  * BOOTP options
 300  */
 301 #define CONFIG_BOOTP_BOOTFILESIZE
 302 #define CONFIG_BOOTP_BOOTPATH
 303 #define CONFIG_BOOTP_GATEWAY
 304 #define CONFIG_BOOTP_HOSTNAME
 305
 306
 307 /*
 308  * Command line configuration.
 309  */
 310 #include <config_cmd_default.h>
 311
 312 #define CONFIG_CMD_ASKENV
 313 #define CONFIG_CMD_BEDBUG
 314 #define CONFIG_CMD_CACHE
 315 #define CONFIG_CMD_CDP
 316 #define CONFIG_CMD_DATE
 317 #define CONFIG_CMD_DIAG
 318 #define CONFIG_CMD_ELF
 319 #define CONFIG_CMD_FAT
 320 #define CONFIG_CMD_I2C
 321 #define CONFIG_CMD_IMMAP
 322 #define CONFIG_CMD_IRQ
 323 #define CONFIG_CMD_PING
 324 #define CONFIG_CMD_PORTIO
 325 #define CONFIG_CMD_REGINFO
 326 #define CONFIG_CMD_SAVES
 327 #define CONFIG_CMD_SDRAM
 328 #define CONFIG_CMD_SNTP
 329
 330 #undef CONFIG_CMD_XIMG
 331
 332 /* Where do the internal registers live? */
 333 #define CONFIG_SYS_IMMR               0xF0000000
 334 #define CONFIG_SYS_DEFAULT_IMMR       0x00010000
 335
 336 /* Where do the on board registers (CS4) live? */
 337 #define CONFIG_SYS_REGS_BASE          0xFA000000
 338
 339 /*****************************************************************************
 340  *
 341  * You should not have to modify any of the following settings
 342  *
 343  *****************************************************************************/
 344
 345 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
 346 #define CONFIG_EP8260           11      /* on an Embedded Planet EP8260 Board, Rev. 11 */
 347
 348 #define CONFIG_BOARD_EARLY_INIT_F 1         /* Call board_early_init_f  */
 349
 350 /*
 351  * Miscellaneous configurable options
 352  */
 353 #if defined(CONFIG_CMD_KGDB)
 354 #  define CONFIG_SYS_CBSIZE              1024       /* Console I/O Buffer Size      */
 355 #else
 356 #  define CONFIG_SYS_CBSIZE              256        /* Console I/O Buffer Size      */
 357 #endif
 358
 359 /* Print Buffer Size */
 360 #define CONFIG_SYS_PBSIZE        (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
 361
 362 #define CONFIG_SYS_MAXARGS       8            /* max number of command args   */
 363
 364 #define CONFIG_SYS_BARGSIZE      CONFIG_SYS_CBSIZE   /* Boot Argument Buffer Size    */
 365
 366 #ifdef CONFIG_SYS_LSDRAM
 367   #define CONFIG_SYS_MEMTEST_START 0x04000000   /* memtest works on  */
 368   #define CONFIG_SYS_MEMTEST_END   0x06000000   /* 64-96 MB in SDRAM */
 369 #else
 370   #define CONFIG_SYS_MEMTEST_START 0x00000000   /* memtest works on  */
 371   #define CONFIG_SYS_MEMTEST_END   0x02000000   /* 0-32 MB in SDRAM */
 372 #endif /* CONFIG_SYS_LSDRAM */
 373
 374 #define CONFIG_CLOCKS_IN_MHZ    1      /* clocks passsed to Linux in MHz */
 375
 376 #define CONFIG_SYS_LOAD_ADDR     0x00100000   /* default load address */
 377
 378 #define CONFIG_SYS_HZ            1000         /* decrementer freq: 1 ms ticks */
 379
 380 /*
 381  * Low Level Configuration Settings
 382  * (address mappings, register initial values, etc.)
 383  * You should know what you are doing if you make changes here.
 384  */
 385
 386 #define CONFIG_SYS_FLASH_BASE    CONFIG_SYS_FLASH0_BASE
 387 #define CONFIG_SYS_SDRAM_BASE    CONFIG_SYS_SDRAM0_BASE
 388
 389 /*-----------------------------------------------------------------------
 390  * Hard Reset Configuration Words
 391  */
 392
 393 #if defined(CONFIG_SYS_SBC_BOOT_LOW)
 394 #  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 395 #else
 396 #  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (0x00000000)
 397 #endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
 398
 399 #ifdef CONFIG_SYS_EP8260_H2
 400 /* get the HRCW ISB field from CONFIG_SYS_DEFAULT_IMMR */
 401 #define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_DEFAULT_IMMR & 0x10000000) >> 10) |\
 402                             ((CONFIG_SYS_DEFAULT_IMMR & 0x01000000) >> 7)  |\
 403                             ((CONFIG_SYS_DEFAULT_IMMR & 0x00100000) >> 4) )
 404
 405 #define CONFIG_SYS_HRCW_MASTER (HRCW_EBM                |\
 406                          HRCW_L2CPC01            |\
 407                          CONFIG_SYS_SBC_HRCW_IMMR       |\
 408                          HRCW_APPC10             |\
 409                          HRCW_CS10PC01           |\
 410                          CONFIG_SYS_SBC_MODCK_H  |\
 411                          CONFIG_SYS_SBC_HRCW_BOOT_FLAGS)
 412 #else
 413 #define CONFIG_SYS_HRCW_MASTER 0x10400245
 414 #endif
 415
 416 /* no slaves */
 417 #define CONFIG_SYS_HRCW_SLAVE1 0
 418 #define CONFIG_SYS_HRCW_SLAVE2 0
 419 #define CONFIG_SYS_HRCW_SLAVE3 0
 420 #define CONFIG_SYS_HRCW_SLAVE4 0
 421 #define CONFIG_SYS_HRCW_SLAVE5 0
 422 #define CONFIG_SYS_HRCW_SLAVE6 0
 423 #define CONFIG_SYS_HRCW_SLAVE7 0
 424
 425 /*-----------------------------------------------------------------------
 426  * Definitions for initial stack pointer and data area (in DPRAM)
 427  */
 428 #define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_IMMR
 429 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM    */
 430 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 431 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 432
 433 /*-----------------------------------------------------------------------
 434  * Start addresses for the final memory configuration
 435  * (Set up by the startup code)
 436  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 437  * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
 438  */
 439 #define CONFIG_SYS_MONITOR_BASE          CONFIG_SYS_TEXT_BASE
 440
 441
 442 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 443 #  define CONFIG_SYS_RAMBOOT
 444 #endif
 445
 446 #define CONFIG_SYS_MONITOR_LEN      (256 << 10)     /* Reserve 256 kB for Monitor   */
 447 #define CONFIG_SYS_MALLOC_LEN       (128 << 10)     /* Reserve 128 kB for malloc()  */
 448
 449 /*
 450  * For booting Linux, the board info and command line data
 451  * have to be in the first 8 MB of memory, since this is
 452  * the maximum mapped by the Linux kernel during initialization.
 453  */
 454 #define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 455
 456 /*-----------------------------------------------------------------------
 457  * FLASH and environment organization
 458  */
 459 #define CONFIG_SYS_MAX_FLASH_BANKS   1       /* max number of memory banks         */
 460 #ifdef CONFIG_SYS_EP8260_H2
 461 #define CONFIG_SYS_MAX_FLASH_SECT    128      /* max number of sectors on one chip  */
 462 #else
 463 #define CONFIG_SYS_MAX_FLASH_SECT    71      /* max number of sectors on one chip  */
 464 #endif
 465
 466 #ifdef CONFIG_SYS_EP8260_H2
 467 #define CONFIG_SYS_FLASH_ERASE_TOUT  240000  /* Timeout for Flash Erase (in ms)    */
 468 #define CONFIG_SYS_FLASH_WRITE_TOUT  500     /* Timeout for Flash Write (in ms)    */
 469 #else
 470 #define CONFIG_SYS_FLASH_ERASE_TOUT  8000    /* Timeout for Flash Erase (in ms)    */
 471 #define CONFIG_SYS_FLASH_WRITE_TOUT  1       /* Timeout for Flash Write (in ms)    */
 472 #endif
 473
 474 #ifndef CONFIG_SYS_RAMBOOT
 475 #  define CONFIG_ENV_IS_IN_FLASH  1
 476
 477 #  ifdef CONFIG_ENV_IN_OWN_SECT
 478 #    define CONFIG_ENV_ADDR       (CONFIG_SYS_MONITOR_BASE + 0x40000)
 479 #    define CONFIG_ENV_SECT_SIZE  0x40000
 480 #  else
 481 #    define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
 482 #    define CONFIG_ENV_SIZE       0x1000  /* Total Size of Environment Sector */
 483 #    define CONFIG_ENV_SECT_SIZE  0x10000 /* see README - env sect real size */
 484 #  endif /* CONFIG_ENV_IN_OWN_SECT */
 485 #else
 486 #  define CONFIG_ENV_IS_IN_NVRAM  1
 487 #  define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 488 #  define CONFIG_ENV_SIZE         0x200
 489 #endif /* CONFIG_SYS_RAMBOOT */
 490
 491 /*-----------------------------------------------------------------------
 492  * Cache Configuration
 493  */
 494 #define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU */
 495
 496 #if defined(CONFIG_CMD_KGDB)
 497 #  define CONFIG_SYS_CACHELINE_SHIFT     5     /* log base 2 of the above value */
 498 #endif
 499
 500 /*-----------------------------------------------------------------------
 501  * HIDx - Hardware Implementation-dependent Registers                    2-11
 502  *-----------------------------------------------------------------------
 503  * HID0 also contains cache control - initially enable both caches and
 504  * invalidate contents, then the final state leaves only the instruction
 505  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 506  * but Soft reset does not.
 507  *
 508  * HID1 has only read-only information - nothing to set.
 509  */
 510 #define CONFIG_SYS_HID0_INIT   (HID0_ICE  |\
 511                          HID0_DCE  |\
 512                          HID0_ICFI |\
 513                          HID0_DCI  |\
 514                          HID0_IFEM |\
 515                          HID0_ABE)
 516 #ifdef CONFIG_SYS_LSDRAM
 517 /* 8260 local bus is NOT cacheable */
 518 #define CONFIG_SYS_HID0_FINAL  (/*HID0_ICE  |*/\
 519                          HID0_IFEM |\
 520                          HID0_ABE  |\
 521                          HID0_EMCP)
 522 #else /* !CONFIG_SYS_LSDRAM */
 523 #define CONFIG_SYS_HID0_FINAL  (HID0_ICE  |\
 524                          HID0_IFEM |\
 525                          HID0_ABE  |\
 526                          HID0_EMCP)
 527 #endif /* CONFIG_SYS_LSDRAM */
 528
 529 #define CONFIG_SYS_HID2        0
 530
 531 /*-----------------------------------------------------------------------
 532  * RMR - Reset Mode Register
 533  *-----------------------------------------------------------------------
 534  */
 535 #define CONFIG_SYS_RMR         0
 536
 537 /*-----------------------------------------------------------------------
 538  * BCR - Bus Configuration                                       4-25
 539  *-----------------------------------------------------------------------
 540  */
 541 #define CONFIG_SYS_BCR         (BCR_EBM   |\
 542                          BCR_PLDP  |\
 543                          BCR_EAV   |\
 544                          BCR_NPQM0)
 545
 546 /*-----------------------------------------------------------------------
 547  * SIUMCR - SIU Module Configuration                             4-31
 548  *-----------------------------------------------------------------------
 549  */
 550 #define CONFIG_SYS_SIUMCR      (SIUMCR_L2CPC01 |\
 551                          SIUMCR_APPC10  |\
 552                          SIUMCR_CS10PC01)
 553
 554 /*-----------------------------------------------------------------------
 555  * SYPCR - System Protection Control                            11-9
 556  * SYPCR can only be written once after reset!
 557  *-----------------------------------------------------------------------
 558  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 559  */
 560 #ifdef CONFIG_SYS_EP8260_H2
 561 /* TBD: Find out why setting the BMT to 0xff causes the FCC to
 562  * generate TX buffer underrun errors for large packets under
 563  * Linux
 564  */
 565 #define CONFIG_SYS_SYPCR_BMT    0x00000600
 566 #else
 567 #define CONFIG_SYS_SYPCR_BMT    SYPCR_BMT
 568 #endif
 569
 570 #ifdef CONFIG_SYS_LSDRAM
 571 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC |\
 572                          CONFIG_SYS_SYPCR_BMT  |\
 573                          SYPCR_PBME |\
 574                          SYPCR_LBME |\
 575                          SYPCR_SWP)
 576 #else
 577 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC |\
 578                          CONFIG_SYS_SYPCR_BMT  |\
 579                          SYPCR_PBME |\
 580                          SYPCR_SWP)
 581 #endif
 582
 583 /*-----------------------------------------------------------------------
 584  * TMCNTSC - Time Counter Status and Control                     4-40
 585  *-----------------------------------------------------------------------
 586  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 587  * and enable Time Counter
 588  */
 589 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC |\
 590                          TMCNTSC_ALR |\
 591                          TMCNTSC_TCF |\
 592                          TMCNTSC_TCE)
 593
 594 /*-----------------------------------------------------------------------
 595  * PISCR - Periodic Interrupt Status and Control                 4-42
 596  *-----------------------------------------------------------------------
 597  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 598  * Periodic timer
 599  */
 600 #ifdef CONFIG_SYS_EP8260_H2
 601 #define CONFIG_SYS_PISCR       (PISCR_PS  |\
 602                          PISCR_PTF |\
 603                          PISCR_PTE)
 604 #else
 605 #define CONFIG_SYS_PISCR        0
 606 #endif
 607
 608 /*-----------------------------------------------------------------------
 609  * SCCR - System Clock Control                                   9-8
 610  *-----------------------------------------------------------------------
 611  */
 612 #ifdef CONFIG_SYS_EP8260_H2
 613 #define CONFIG_SYS_SCCR        (SCCR_DFBRG00)
 614 #else
 615 #define CONFIG_SYS_SCCR        (SCCR_DFBRG01)
 616 #endif
 617
 618 /*-----------------------------------------------------------------------
 619  * RCCR - RISC Controller Configuration                         13-7
 620  *-----------------------------------------------------------------------
 621  */
 622 #define CONFIG_SYS_RCCR        0
 623
 624 /*-----------------------------------------------------------------------
 625  * MPTPR - Memory Refresh Timer Prescale Register               10-32
 626  *-----------------------------------------------------------------------
 627  */
 628 #define CONFIG_SYS_MPTPR        (0x0A00 & MPTPR_PTP_MSK)
 629
 630 /*
 631  * Init Memory Controller:
 632  *
 633  * Bank Bus     Machine PortSz  Device
 634  * ---- ---     ------- ------  ------
 635  *  0   60x     GPCM    64 bit  FLASH (BGA - 16MB AMD AM29DL323DB90WDI)
 636  *  1   60x     SDRAM   64 bit  SDRAM (BGA - 64MB Micron 48LC8M16A2TG)
 637  *  2   Local   SDRAM   32 bit  SDRAM (BGA - 32MB Micron 48LC8M16A2TG)
 638  *  3   unused
 639  *  4   60x     GPCM     8 bit  Board Regs, NVRTC
 640  *  5   unused
 641  *  6   unused
 642  *  7   unused
 643  *  8   PCMCIA
 644  *  9   unused
 645  * 10   unused
 646  * 11   unused
 647 */
 648
 649 /*-----------------------------------------------------------------------
 650  * BRx - Base Register
 651  *     Ref: Section 10.3.1 on page 10-14
 652  * ORx - Option Register
 653  *     Ref: Section 10.3.2 on page 10-18
 654  *-----------------------------------------------------------------------
 655  */
 656
 657 /* Bank 0 - FLASH
 658  *
 659  */
 660 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
 661                          BRx_PS_64                      |\
 662                          BRx_DECC_NONE                  |\
 663                          BRx_MS_GPCM_P                  |\
 664                          BRx_V)
 665
 666 #define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE)     |\
 667                          ORxG_CSNT                      |\
 668                          ORxG_ACS_DIV1                  |\
 669                          ORxG_SCY_8_CLK                 |\
 670                          ORxG_EHTR)
 671
 672 /* Bank 1 - SDRAM
 673  * PSDRAM
 674  */
 675 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
 676                          BRx_PS_64                      |\
 677                          BRx_MS_SDRAM_P                 |\
 678                          BRx_V)
 679
 680 #define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE)     |\
 681                          ORxS_BPD_4                     |\
 682                          ORxS_ROWST_PBI1_A6             |\
 683                          ORxS_NUMR_12)
 684
 685 #ifdef CONFIG_SYS_EP8260_H2
 686 #define CONFIG_SYS_PSDMR       0xC34E246E
 687 #else
 688 #define CONFIG_SYS_PSDMR       0xC34E2462
 689 #endif
 690
 691 #define CONFIG_SYS_PSRT 0x64
 692
 693 #ifdef CONFIG_SYS_LSDRAM
 694 /* Bank 2 - SDRAM
 695  * LSDRAM
 696  */
 697
 698   #define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
 699                            BRx_PS_32                      |\
 700                            BRx_MS_SDRAM_L                 |\
 701                            BRx_V)
 702
 703   #define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE)     |\
 704                            ORxS_BPD_4                     |\
 705                            ORxS_ROWST_PBI0_A9             |\
 706                            ORxS_NUMR_12)
 707
 708   #define CONFIG_SYS_LSDMR      0x416A2562
 709   #define CONFIG_SYS_LSRT       0x64
 710 #else
 711   #define CONFIG_SYS_LSRT       0x0
 712 #endif /* CONFIG_SYS_LSDRAM */
 713
 714 /* Bank 4 - On board registers
 715  * NVRTC and BCSR
 716  */
 717 #define CONFIG_SYS_BR4_PRELIM   ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK)  |\
 718                            BRx_PS_8                     |\
 719                            BRx_MS_GPCM_P                |\
 720                            BRx_V)
 721 /*
 722 #define CONFIG_SYS_OR4_PRELIM    (ORxG_AM_MSK                 |\
 723                            ORxG_CSNT                   |\
 724                            ORxG_ACS_DIV1               |\
 725                            ORxG_SCY_10_CLK              |\
 726                            ORxG_TRLX)
 727 */
 728 #define CONFIG_SYS_OR4_PRELIM 0xfff00854
 729
 730 #ifdef _NOT_USED_SINCE_NOT_WORKING_
 731 /* Bank 8 - On board registers
 732  * PCMCIA (currently not working!)
 733  */
 734 #define CONFIG_SYS_BR8_PRELIM   ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK)  |\
 735                            BRx_PS_16                     |\
 736                            BRx_MS_GPCM_P                |\
 737                            BRx_V)
 738
 739 #define CONFIG_SYS_OR8_PRELIM    (ORxG_AM_MSK                 |\
 740                            ORxG_CSNT                   |\
 741                            ORxG_ACS_DIV1               |\
 742                            ORxG_SETA                   |\
 743                            ORxG_SCY_10_CLK)
 744 #endif
 745
 746 /*
 747  * JFFS2 partitions
 748  *
 749  */
 750 /* No command line, one static partition, whole device */
 751 #undef CONFIG_CMD_MTDPARTS
 752 #define CONFIG_JFFS2_DEV                "nor0"
 753 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 754 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 755
 756 /* mtdparts command line support */
 757 /* Note: fake mtd_id used, no linux mtd map file */
 758 /*
 759 #define CONFIG_CMD_MTDPARTS
 760 #define MTDIDS_DEFAULT          ""
 761 #define MTDPARTS_DEFAULT        ""
 762 */
 763
 764 #endif  /* __CONFIG_H */