include/configs/ep82xxm.h

   1 /*
   2  * Copyright (C) 2006 Embedded Planet, LLC.
   3  *
   4  * U-Boot configuration for Embedded Planet EP82xxM boards.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #define CONFIG_MPC8260
  13 #define CPU_ID_STR              "MPC8270"
  14
  15 #define CONFIG_EP82XXM  /* Embedded Planet EP82xxM H 1.0 board */
  16                         /* 256MB SDRAM / 64MB FLASH */
  17
  18 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  19
  20 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f */
  21
  22 /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
  23 #define CONFIG_ENV_OVERWRITE
  24
  25 /*
  26  * Select serial console configuration
  27  *
  28  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  29  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  30  * for SCC).
  31  */
  32 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
  33 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
  34 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
  35 #define CONFIG_CONS_INDEX       1       /* SMC1 is used for console  */
  36
  37 #define CONFIG_SYS_BCSR         0xFA000000
  38
  39 /*
  40  * Select ethernet configuration
  41  *
  42  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
  43  * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
  44  * SCC, 1-3 for FCC)
  45  *
  46  * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
  47  * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
  48  * must be unset.
  49  */
  50 #undef  CONFIG_ETHER_ON_SCC             /* Ethernet is not on SCC */
  51 #define CONFIG_ETHER_ON_FCC             /* Ethernet is on FCC     */
  52 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
  53
  54
  55 #define CONFIG_ETHER_ON_FCC2
  56 #define CONFIG_ETHER_ON_FCC3
  57
  58 #define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
  59 #define CONFIG_SYS_CMXFCR_VALUE3        (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16)
  60 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  61 #define CONFIG_SYS_CMXFCR_VALUE2        (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  62
  63 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
  64 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
  65
  66 #define CONFIG_MII                      /* MII PHY management        */
  67 #define CONFIG_BITBANGMII               /* Bit-banged MDIO interface */
  68
  69 /*
  70  * GPIO pins used for bit-banged MII communications
  71  */
  72 #define MDIO_PORT               0       /* Not used - implemented in BCSR */
  73
  74 #define MDIO_ACTIVE             (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
  75 #define MDIO_TRISTATE           (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
  76 #define MDIO_READ               (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
  77
  78 #define MDIO(bit)               if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
  79                                 else    *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE
  80
  81 #define MDC(bit)                if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
  82                                 else    *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD
  83
  84 #define MIIDELAY                udelay(1)
  85
  86
  87 #ifndef CONFIG_8260_CLKIN
  88 #define CONFIG_8260_CLKIN       66000000 /* in Hz */
  89 #endif
  90
  91 #define CONFIG_BAUDRATE         115200
  92
  93 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */
  94
  95
  96 /*
  97  * BOOTP options
  98  */
  99 #define CONFIG_BOOTP_BOOTFILESIZE
 100 #define CONFIG_BOOTP_BOOTPATH
 101 #define CONFIG_BOOTP_GATEWAY
 102 #define CONFIG_BOOTP_HOSTNAME
 103
 104
 105 /*
 106  * Command line configuration.
 107  */
 108 #include <config_cmd_default.h>
 109
 110
 111 #define CONFIG_CMD_DHCP
 112 #define CONFIG_CMD_ECHO
 113 #define CONFIG_CMD_I2C
 114 #define CONFIG_CMD_IMMAP
 115 #define CONFIG_CMD_MII
 116 #define CONFIG_CMD_PING
 117 #define CONFIG_CMD_DATE
 118 #define CONFIG_CMD_DTT
 119 #define CONFIG_CMD_EEPROM
 120 #define CONFIG_CMD_PCI
 121 #define CONFIG_CMD_DIAG
 122
 123
 124 #define CONFIG_ETHADDR          00:10:EC:00:88:65
 125 #define CONFIG_HAS_ETH1
 126 #define CONFIG_ETH1ADDR         00:10:EC:80:88:65
 127 #define CONFIG_IPADDR           10.0.0.245
 128 #define CONFIG_HOSTNAME         EP82xxM
 129 #define CONFIG_SERVERIP         10.0.0.26
 130 #define CONFIG_GATEWAYIP        10.0.0.1
 131 #define CONFIG_NETMASK          255.255.255.0
 132 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 133 #define CONFIG_ENV_IN_OWN_SECT  1
 134 #define CONFIG_AUTO_COMPLETE    1
 135 #define CONFIG_EXTRA_ENV_SETTINGS       "ethprime=FCC3"
 136
 137 #if defined(CONFIG_CMD_KGDB)
 138 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 139 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 140 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 141 #define CONFIG_KGDB_INDEX       1       /* which serial channel for kgdb */
 142 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 143 #endif
 144
 145 #define CONFIG_BZIP2    /* include support for bzip2 compressed images */
 146 #undef  CONFIG_WATCHDOG                 /* disable platform specific watchdog */
 147
 148 /*
 149  * Miscellaneous configurable options
 150  */
 151 #define CONFIG_SYS_HUSH_PARSER
 152 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 153 #define CONFIG_SYS_PROMPT               "ep82xxm=> "    /* Monitor Command Prompt   */
 154 #if defined(CONFIG_CMD_KGDB)
 155 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 156 #else
 157 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 158 #endif
 159 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size  */
 160 #define CONFIG_SYS_MAXARGS              16              /* max number of command args */
 161 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size  */
 162
 163 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 164 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 165
 166 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 167
 168 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 169
 170 /*-----------------------------------------------------------------------
 171  * Environment
 172  *----------------------------------------------------------------------*/
 173 /*
 174  * Define here the location of the environment variables (FLASH or EEPROM).
 175  * Note: DENX encourages to use redundant environment in FLASH.
 176  */
 177 #if 1
 178 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
 179 #else
 180 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars      */
 181 #endif
 182
 183 /*-----------------------------------------------------------------------
 184  * FLASH related
 185  *----------------------------------------------------------------------*/
 186 #define CONFIG_SYS_FLASH_BASE           0xFC000000
 187 #define CONFIG_SYS_FLASH_CFI
 188 #define CONFIG_FLASH_CFI_DRIVER
 189 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks       */
 190 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sects on one chip */
 191 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector in flinfo */
 192
 193 #ifdef CONFIG_ENV_IS_IN_FLASH
 194 #define CONFIG_ENV_SECT_SIZE    0x20000
 195 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 196 #endif /* CONFIG_ENV_IS_IN_FLASH */
 197
 198 /*-----------------------------------------------------------------------
 199  * I2C
 200  *----------------------------------------------------------------------*/
 201 /* EEPROM Configuration */
 202 #define CONFIG_SYS_EEPROM_SIZE  0x1000
 203 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x54
 204 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 205 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 206 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 207
 208 #ifdef CONFIG_ENV_IS_IN_EEPROM
 209 #define CONFIG_ENV_SIZE         0x200       /* Size of Environment vars */
 210 #define CONFIG_ENV_OFFSET               0x0
 211 #endif /* CONFIG_ENV_IS_IN_EEPROM */
 212
 213 /* RTC Configuration */
 214 #define CONFIG_RTC_M41T11       1       /* uses a M41T81 */
 215 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 216 #define CONFIG_M41T11_BASE_YEAR 1900
 217
 218 /* I2C SYSMON (LM75) */
 219 #define CONFIG_DTT_LM75         1
 220 #define CONFIG_DTT_SENSORS      {0}
 221 #define CONFIG_SYS_DTT_MAX_TEMP 70
 222 #define CONFIG_SYS_DTT_LOW_TEMP -30
 223 #define CONFIG_SYS_DTT_HYSTERESIS       3
 224
 225 /*-----------------------------------------------------------------------
 226  * NVRAM Configuration
 227  *-----------------------------------------------------------------------
 228  */
 229 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xFA080000
 230 #define CONFIG_SYS_NVRAM_SIZE           (128*1024)-16
 231
 232
 233 /*-----------------------------------------------------------------------
 234  * PCI stuff
 235  *-----------------------------------------------------------------------
 236  */
 237 /* General PCI */
 238 #define CONFIG_PCI                      /* include pci support          */
 239 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 240 #define CONFIG_PCI_PNP                  /* do pci plug-and-play   */
 241 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 242 #define CONFIG_PCI_BOOTDELAY    0
 243
 244 /* PCI Memory map (if different from default map */
 245 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE           /* Local base */
 246 #define CONFIG_SYS_PCI_SLV_MEM_BUS              0x00000000      /* PCI base */
 247 #define CONFIG_SYS_PICMR0_MASK_ATTRIB   (PICMR_MASK_512MB | PICMR_ENABLE | \
 248                                  PICMR_PREFETCH_EN)
 249
 250 /*
 251  * These are the windows that allow the CPU to access PCI address space.
 252  * All three PCI master windows, which allow the CPU to access PCI
 253  * prefetch, non prefetch, and IO space (see below), must all fit within
 254  * these windows.
 255  */
 256
 257 /*
 258  * Master window that allows the CPU to access PCI Memory (prefetch).
 259  * This window will be setup with the second set of Outbound ATU registers
 260  * in the bridge.
 261  */
 262
 263 #define CONFIG_SYS_PCI_MSTR_MEM_LOCAL   0x80000000          /* Local base */
 264 #define CONFIG_SYS_PCI_MSTR_MEM_BUS     0x80000000          /* PCI base   */
 265 #define CONFIG_SYS_CPU_PCI_MEM_START    PCI_MSTR_MEM_LOCAL
 266 #define CONFIG_SYS_PCI_MSTR_MEM_SIZE    0x20000000          /* 512MB */
 267 #define CONFIG_SYS_POCMR0_MASK_ATTRIB   (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
 268
 269 /*
 270  * Master window that allows the CPU to access PCI Memory (non-prefetch).
 271  * This window will be setup with the second set of Outbound ATU registers
 272  * in the bridge.
 273  */
 274
 275 #define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
 276 #define CONFIG_SYS_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
 277 #define CONFIG_SYS_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
 278 #define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
 279 #define CONFIG_SYS_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
 280
 281 /*
 282  * Master window that allows the CPU to access PCI IO space.
 283  * This window will be setup with the first set of Outbound ATU registers
 284  * in the bridge.
 285  */
 286
 287 #define CONFIG_SYS_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
 288 #define CONFIG_SYS_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
 289 #define CONFIG_SYS_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
 290 #define CONFIG_SYS_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
 291 #define CONFIG_SYS_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
 292
 293
 294 /* PCIBR0 - for PCI IO*/
 295 #define CONFIG_SYS_PCI_MSTR0_LOCAL              CONFIG_SYS_PCI_MSTR_IO_LOCAL            /* Local base */
 296 #define CONFIG_SYS_PCIMSK0_MASK         ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U)     /* Size of window */
 297 /* PCIBR1 - prefetch and non-prefetch regions joined together */
 298 #define CONFIG_SYS_PCI_MSTR1_LOCAL              CONFIG_SYS_PCI_MSTR_MEM_LOCAL
 299 #define CONFIG_SYS_PCIMSK1_MASK         ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
 300
 301
 302 #define CONFIG_SYS_DIRECT_FLASH_TFTP
 303
 304 #if defined(CONFIG_CMD_JFFS2)
 305 #define CONFIG_SYS_JFFS2_FIRST_BANK     0
 306 #define CONFIG_SYS_JFFS2_NUM_BANKS      CONFIG_SYS_MAX_FLASH_BANKS
 307 #define CONFIG_SYS_JFFS2_FIRST_SECTOR  0
 308 #define CONFIG_SYS_JFFS2_LAST_SECTOR   62
 309 #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
 310 #define CONFIG_SYS_JFFS_CUSTOM_PART
 311 #endif
 312
 313 #if defined(CONFIG_CMD_I2C)
 314 #define CONFIG_HARD_I2C         1       /* To enable I2C support        */
 315 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed                    */
 316 #define CONFIG_SYS_I2C_SLAVE            0x7F    /* I2C slave address            */
 317 #endif
 318
 319 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 320 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 321 #define CONFIG_SYS_RAMBOOT
 322 #endif
 323
 324 #define CONFIG_SYS_MONITOR_LEN          (512 << 10)     /* Reserve 256KB for Monitor */
 325
 326 #define CONFIG_SYS_DEFAULT_IMMR 0x00010000
 327 #define CONFIG_SYS_IMMR         0xF0000000
 328
 329 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 330 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000  /* Size of used area in DPRAM   */
 331 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 332 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 333
 334
 335 /* Hard reset configuration word */
 336 #define CONFIG_SYS_HRCW_MASTER          0 /*0x1C800641*/  /* Not used - provided by CPLD */
 337 /* No slaves */
 338 #define CONFIG_SYS_HRCW_SLAVE1          0
 339 #define CONFIG_SYS_HRCW_SLAVE2          0
 340 #define CONFIG_SYS_HRCW_SLAVE3          0
 341 #define CONFIG_SYS_HRCW_SLAVE4          0
 342 #define CONFIG_SYS_HRCW_SLAVE5          0
 343 #define CONFIG_SYS_HRCW_SLAVE6          0
 344 #define CONFIG_SYS_HRCW_SLAVE7          0
 345
 346 #define CONFIG_SYS_MALLOC_LEN           (4096 << 10)    /* Reserve 4 MB for malloc()    */
 347 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 348
 349 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPUs */
 350 #if defined(CONFIG_CMD_KGDB)
 351 #define CONFIG_SYS_CACHELINE_SHIFT      5       /* log base 2 of the above value */
 352 #endif
 353
 354 #define CONFIG_SYS_HID0_INIT            0
 355 #define CONFIG_SYS_HID0_FINAL           0
 356
 357 #define CONFIG_SYS_HID2         0
 358
 359 #define CONFIG_SYS_SIUMCR               0x02610000
 360 #define CONFIG_SYS_SYPCR                0xFFFF0689
 361 #define CONFIG_SYS_BCR                  0x8080E000
 362 #define CONFIG_SYS_SCCR         0x00000001
 363
 364 #define CONFIG_SYS_RMR                  0
 365 #define CONFIG_SYS_TMCNTSC              0x000000C3
 366 #define CONFIG_SYS_PISCR                0x00000083
 367 #define CONFIG_SYS_RCCR         0
 368
 369 #define CONFIG_SYS_MPTPR                0x0A00
 370 #define CONFIG_SYS_PSDMR                0xC432246E
 371 #define CONFIG_SYS_PSRT         0x32
 372
 373 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 374 #define CONFIG_SYS_SDRAM_BR             (CONFIG_SYS_SDRAM_BASE | 0x00000041)
 375 #define CONFIG_SYS_SDRAM_OR             0xF0002900
 376
 377 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | 0x00001801)
 378 #define CONFIG_SYS_OR0_PRELIM           0xFC000882
 379 #define CONFIG_SYS_BR4_PRELIM           (CONFIG_SYS_BCSR | 0x00001001)
 380 #define CONFIG_SYS_OR4_PRELIM           0xFFF00050
 381
 382 #define CONFIG_SYS_RESET_ADDRESS        0xFFF00100
 383
 384 #endif /* __CONFIG_H */