include/configs/ep82xxm.h

   1 /*
   2  * Copyright (C) 2006 Embedded Planet, LLC.
   3  *
   4  * U-Boot configuration for Embedded Planet EP82xxM boards.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef __CONFIG_H
  26 #define __CONFIG_H
  27
  28 #define CONFIG_MPC8260
  29 #define CPU_ID_STR              "MPC8270"
  30
  31 #define CONFIG_EP82XXM  /* Embedded Planet EP82xxM H 1.0 board */
  32                         /* 256MB SDRAM / 64MB FLASH */
  33
  34 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f */
  35
  36 /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
  37 #define CONFIG_ENV_OVERWRITE
  38
  39 /*
  40  * Select serial console configuration
  41  *
  42  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  43  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  44  * for SCC).
  45  */
  46 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
  47 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
  48 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
  49 #define CONFIG_CONS_INDEX       1       /* SMC1 is used for console  */
  50
  51 #define CONFIG_SYS_BCSR         0xFA000000
  52
  53 /*
  54  * Select ethernet configuration
  55  *
  56  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
  57  * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
  58  * SCC, 1-3 for FCC)
  59  *
  60  * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
  61  * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
  62  * must be unset.
  63  */
  64 #undef  CONFIG_ETHER_ON_SCC             /* Ethernet is not on SCC */
  65 #define CONFIG_ETHER_ON_FCC             /* Ethernet is on FCC     */
  66 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
  67
  68 #define CONFIG_NET_MULTI
  69
  70 #define CONFIG_ETHER_ON_FCC2
  71 #define CONFIG_ETHER_ON_FCC3
  72
  73 #define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
  74 #define CONFIG_SYS_CMXFCR_VALUE3        (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16)
  75 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  76 #define CONFIG_SYS_CMXFCR_VALUE2        (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  77
  78 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
  79 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
  80
  81 #define CONFIG_MII                      /* MII PHY management        */
  82 #define CONFIG_BITBANGMII               /* Bit-banged MDIO interface */
  83
  84 /*
  85  * GPIO pins used for bit-banged MII communications
  86  */
  87 #define MDIO_PORT               0       /* Not used - implemented in BCSR */
  88
  89 #define MDIO_ACTIVE             (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
  90 #define MDIO_TRISTATE           (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
  91 #define MDIO_READ               (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
  92
  93 #define MDIO(bit)               if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
  94                                 else    *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE
  95
  96 #define MDC(bit)                if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
  97                                 else    *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD
  98
  99 #define MIIDELAY                udelay(1)
 100
 101
 102 #ifndef CONFIG_8260_CLKIN
 103 #define CONFIG_8260_CLKIN       66000000 /* in Hz */
 104 #endif
 105
 106 #define CONFIG_BAUDRATE         115200
 107
 108 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */
 109
 110
 111 /*
 112  * BOOTP options
 113  */
 114 #define CONFIG_BOOTP_BOOTFILESIZE
 115 #define CONFIG_BOOTP_BOOTPATH
 116 #define CONFIG_BOOTP_GATEWAY
 117 #define CONFIG_BOOTP_HOSTNAME
 118
 119
 120 /*
 121  * Command line configuration.
 122  */
 123 #include <config_cmd_default.h>
 124
 125
 126 #define CONFIG_CMD_DHCP
 127 #define CONFIG_CMD_ECHO
 128 #define CONFIG_CMD_I2C
 129 #define CONFIG_CMD_IMMAP
 130 #define CONFIG_CMD_MII
 131 #define CONFIG_CMD_PING
 132 #define CONFIG_CMD_DATE
 133 #define CONFIG_CMD_DTT
 134 #define CONFIG_CMD_EEPROM
 135 #define CONFIG_CMD_PCI
 136 #define CONFIG_CMD_DIAG
 137
 138
 139 #define CONFIG_ETHADDR          00:10:EC:00:88:65
 140 #define CONFIG_HAS_ETH1
 141 #define CONFIG_ETH1ADDR         00:10:EC:80:88:65
 142 #define CONFIG_IPADDR           10.0.0.245
 143 #define CONFIG_HOSTNAME         EP82xxM
 144 #define CONFIG_SERVERIP         10.0.0.26
 145 #define CONFIG_GATEWAYIP        10.0.0.1
 146 #define CONFIG_NETMASK          255.255.255.0
 147 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 148 #define CONFIG_ENV_IN_OWN_SECT  1
 149 #define CONFIG_AUTO_COMPLETE    1
 150 #define CONFIG_EXTRA_ENV_SETTINGS       "ethprime=FCC3 ETHERNET"
 151
 152 #if defined(CONFIG_CMD_KGDB)
 153 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 154 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 155 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 156 #define CONFIG_KGDB_INDEX       1       /* which serial channel for kgdb */
 157 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 158 #endif
 159
 160 #define CONFIG_BZIP2    /* include support for bzip2 compressed images */
 161 #undef  CONFIG_WATCHDOG                 /* disable platform specific watchdog */
 162
 163 /*
 164  * Miscellaneous configurable options
 165  */
 166 #define CONFIG_SYS_HUSH_PARSER
 167 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 168 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 169 #define CONFIG_SYS_PROMPT               "ep82xxm=> "    /* Monitor Command Prompt   */
 170 #if defined(CONFIG_CMD_KGDB)
 171 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 172 #else
 173 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 174 #endif
 175 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size  */
 176 #define CONFIG_SYS_MAXARGS              16              /* max number of command args */
 177 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size  */
 178
 179 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 180 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 181
 182 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 183
 184 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 185
 186 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 187
 188 /*-----------------------------------------------------------------------
 189  * Environment
 190  *----------------------------------------------------------------------*/
 191 /*
 192  * Define here the location of the environment variables (FLASH or EEPROM).
 193  * Note: DENX encourages to use redundant environment in FLASH.
 194  */
 195 #if 1
 196 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
 197 #else
 198 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars      */
 199 #endif
 200
 201 /*-----------------------------------------------------------------------
 202  * FLASH related
 203  *----------------------------------------------------------------------*/
 204 #define CONFIG_SYS_FLASH_BASE           0xFC000000
 205 #define CONFIG_SYS_FLASH_CFI
 206 #define CONFIG_FLASH_CFI_DRIVER
 207 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks       */
 208 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sects on one chip */
 209 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector in flinfo */
 210
 211 #ifdef CONFIG_ENV_IS_IN_FLASH
 212 #define CONFIG_ENV_SECT_SIZE    0x20000
 213 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 214 #endif /* CONFIG_ENV_IS_IN_FLASH */
 215
 216 /*-----------------------------------------------------------------------
 217  * I2C
 218  *----------------------------------------------------------------------*/
 219 /* EEPROM Configuration */
 220 #define CONFIG_SYS_EEPROM_SIZE  0x1000
 221 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x54
 222 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 223 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 224 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 225
 226 #ifdef CONFIG_ENV_IS_IN_EEPROM
 227 #define CONFIG_ENV_SIZE         0x200       /* Size of Environment vars */
 228 #define CONFIG_ENV_OFFSET               0x0
 229 #endif /* CONFIG_ENV_IS_IN_EEPROM */
 230
 231 /* RTC Configuration */
 232 #define CONFIG_RTC_M41T11       1       /* uses a M41T81 */
 233 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 234 #define CONFIG_M41T11_BASE_YEAR 1900
 235
 236 /* I2C SYSMON (LM75) */
 237 #define CONFIG_DTT_LM75         1
 238 #define CONFIG_DTT_SENSORS      {0}
 239 #define CONFIG_SYS_DTT_MAX_TEMP 70
 240 #define CONFIG_SYS_DTT_LOW_TEMP -30
 241 #define CONFIG_SYS_DTT_HYSTERESIS       3
 242
 243 /*-----------------------------------------------------------------------
 244  * NVRAM Configuration
 245  *-----------------------------------------------------------------------
 246  */
 247 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xFA080000
 248 #define CONFIG_SYS_NVRAM_SIZE           (128*1024)-16
 249
 250
 251 /*-----------------------------------------------------------------------
 252  * PCI stuff
 253  *-----------------------------------------------------------------------
 254  */
 255 /* General PCI */
 256 #define CONFIG_PCI                      /* include pci support          */
 257 #define CONFIG_PCI_PNP                  /* do pci plug-and-play   */
 258 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 259 #define CONFIG_PCI_BOOTDELAY    0
 260
 261 /* PCI Memory map (if different from default map */
 262 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE           /* Local base */
 263 #define CONFIG_SYS_PCI_SLV_MEM_BUS              0x00000000      /* PCI base */
 264 #define CONFIG_SYS_PICMR0_MASK_ATTRIB   (PICMR_MASK_512MB | PICMR_ENABLE | \
 265                                  PICMR_PREFETCH_EN)
 266
 267 /*
 268  * These are the windows that allow the CPU to access PCI address space.
 269  * All three PCI master windows, which allow the CPU to access PCI
 270  * prefetch, non prefetch, and IO space (see below), must all fit within
 271  * these windows.
 272  */
 273
 274 /*
 275  * Master window that allows the CPU to access PCI Memory (prefetch).
 276  * This window will be setup with the second set of Outbound ATU registers
 277  * in the bridge.
 278  */
 279
 280 #define CONFIG_SYS_PCI_MSTR_MEM_LOCAL   0x80000000          /* Local base */
 281 #define CONFIG_SYS_PCI_MSTR_MEM_BUS     0x80000000          /* PCI base   */
 282 #define CONFIG_SYS_CPU_PCI_MEM_START    PCI_MSTR_MEM_LOCAL
 283 #define CONFIG_SYS_PCI_MSTR_MEM_SIZE    0x20000000          /* 512MB */
 284 #define CONFIG_SYS_POCMR0_MASK_ATTRIB   (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
 285
 286 /*
 287  * Master window that allows the CPU to access PCI Memory (non-prefetch).
 288  * This window will be setup with the second set of Outbound ATU registers
 289  * in the bridge.
 290  */
 291
 292 #define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
 293 #define CONFIG_SYS_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
 294 #define CONFIG_SYS_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
 295 #define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
 296 #define CONFIG_SYS_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
 297
 298 /*
 299  * Master window that allows the CPU to access PCI IO space.
 300  * This window will be setup with the first set of Outbound ATU registers
 301  * in the bridge.
 302  */
 303
 304 #define CONFIG_SYS_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
 305 #define CONFIG_SYS_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
 306 #define CONFIG_SYS_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
 307 #define CONFIG_SYS_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
 308 #define CONFIG_SYS_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
 309
 310
 311 /* PCIBR0 - for PCI IO*/
 312 #define CONFIG_SYS_PCI_MSTR0_LOCAL              CONFIG_SYS_PCI_MSTR_IO_LOCAL            /* Local base */
 313 #define CONFIG_SYS_PCIMSK0_MASK         ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U)     /* Size of window */
 314 /* PCIBR1 - prefetch and non-prefetch regions joined together */
 315 #define CONFIG_SYS_PCI_MSTR1_LOCAL              CONFIG_SYS_PCI_MSTR_MEM_LOCAL
 316 #define CONFIG_SYS_PCIMSK1_MASK         ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
 317
 318
 319 #define CONFIG_SYS_DIRECT_FLASH_TFTP
 320
 321 #if defined(CONFIG_CMD_JFFS2)
 322 #define CONFIG_SYS_JFFS2_FIRST_BANK     0
 323 #define CONFIG_SYS_JFFS2_NUM_BANKS      CONFIG_SYS_MAX_FLASH_BANKS
 324 #define CONFIG_SYS_JFFS2_FIRST_SECTOR  0
 325 #define CONFIG_SYS_JFFS2_LAST_SECTOR   62
 326 #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
 327 #define CONFIG_SYS_JFFS_CUSTOM_PART
 328 #endif
 329
 330 #if defined(CONFIG_CMD_I2C)
 331 #define CONFIG_HARD_I2C         1       /* To enable I2C support        */
 332 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed                    */
 333 #define CONFIG_SYS_I2C_SLAVE            0x7F    /* I2C slave address            */
 334 #endif
 335
 336 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
 337 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 338 #define CONFIG_SYS_RAMBOOT
 339 #endif
 340
 341 #define CONFIG_SYS_MONITOR_LEN          (512 << 10)     /* Reserve 256KB for Monitor */
 342
 343 #define CONFIG_SYS_DEFAULT_IMMR 0x00010000
 344 #define CONFIG_SYS_IMMR         0xF0000000
 345
 346 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 347 #define CONFIG_SYS_INIT_RAM_END 0x2000  /* End of used area in DPRAM    */
 348 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* size in bytes reserved for initial data */
 349 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 350 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 351
 352
 353 /* Hard reset configuration word */
 354 #define CONFIG_SYS_HRCW_MASTER          0 /*0x1C800641*/  /* Not used - provided by CPLD */
 355 /* No slaves */
 356 #define CONFIG_SYS_HRCW_SLAVE1          0
 357 #define CONFIG_SYS_HRCW_SLAVE2          0
 358 #define CONFIG_SYS_HRCW_SLAVE3          0
 359 #define CONFIG_SYS_HRCW_SLAVE4          0
 360 #define CONFIG_SYS_HRCW_SLAVE5          0
 361 #define CONFIG_SYS_HRCW_SLAVE6          0
 362 #define CONFIG_SYS_HRCW_SLAVE7          0
 363
 364 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
 365 #define BOOTFLAG_WARM           0x02    /* Software reboot                  */
 366
 367 #define CONFIG_SYS_MALLOC_LEN           (4096 << 10)    /* Reserve 4 MB for malloc()    */
 368 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 369
 370 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPUs */
 371 #if defined(CONFIG_CMD_KGDB)
 372 #define CONFIG_SYS_CACHELINE_SHIFT      5       /* log base 2 of the above value */
 373 #endif
 374
 375 #define CONFIG_SYS_HID0_INIT            0
 376 #define CONFIG_SYS_HID0_FINAL           0
 377
 378 #define CONFIG_SYS_HID2         0
 379
 380 #define CONFIG_SYS_SIUMCR               0x02610000
 381 #define CONFIG_SYS_SYPCR                0xFFFF0689
 382 #define CONFIG_SYS_BCR                  0x8080E000
 383 #define CONFIG_SYS_SCCR         0x00000001
 384
 385 #define CONFIG_SYS_RMR                  0
 386 #define CONFIG_SYS_TMCNTSC              0x000000C3
 387 #define CONFIG_SYS_PISCR                0x00000083
 388 #define CONFIG_SYS_RCCR         0
 389
 390 #define CONFIG_SYS_MPTPR                0x0A00
 391 #define CONFIG_SYS_PSDMR                0xC432246E
 392 #define CONFIG_SYS_PSRT         0x32
 393
 394 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 395 #define CONFIG_SYS_SDRAM_BR             (CONFIG_SYS_SDRAM_BASE | 0x00000041)
 396 #define CONFIG_SYS_SDRAM_OR             0xF0002900
 397
 398 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | 0x00001801)
 399 #define CONFIG_SYS_OR0_PRELIM           0xFC000882
 400 #define CONFIG_SYS_BR4_PRELIM           (CONFIG_SYS_BCSR | 0x00001001)
 401 #define CONFIG_SYS_OR4_PRELIM           0xFFF00050
 402
 403 #define CONFIG_SYS_RESET_ADDRESS        0xFFF00100
 404
 405 #endif /* __CONFIG_H */