include/configs/espt.h

   1 /*
   2  * Configuation settings for the ESPT-GIGA board
   3  *
   4  * Copyright (C) 2008 Renesas Solutions Corp.
   5  * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __ESPT_H
  11 #define __ESPT_H
  12
  13 #define CONFIG_CPU_SH7763       1
  14 #define CONFIG_ESPT     1
  15 #define __LITTLE_ENDIAN         1
  16
  17 #define CONFIG_ENV_OVERWRITE    1
  18
  19 #define CONFIG_DISPLAY_BOARDINFO
  20 #undef  CONFIG_SHOW_BOOT_PROGRESS
  21
  22 /* SCIF */
  23 #define CONFIG_CONS_SCIF0               1
  24
  25 #define CONFIG_SYS_TEXT_BASE    0x8FFC0000
  26 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
  27 #define CONFIG_SYS_CBSIZE               256     /* Buffer size for input from the Console */
  28 #define CONFIG_SYS_PBSIZE               256     /* Buffer size for Console output */
  29 #define CONFIG_SYS_MAXARGS              16      /* max args accepted for monitor commands */
  30 #define CONFIG_SYS_BARGSIZE     512     /* Buffer size for Boot Arguments
  31                                                                 passed to kernel */
  32 #define CONFIG_SYS_BAUDRATE_TABLE       { 115200 }      /* List of legal baudrate
  33                                                                                                 settings for this board */
  34
  35 /* SDRAM */
  36 #define CONFIG_SYS_SDRAM_BASE           (0x8C000000)
  37 #define CONFIG_SYS_SDRAM_SIZE           (64 * 1024 * 1024)
  38 #define CONFIG_SYS_MEMTEST_START        (CONFIG_SYS_SDRAM_BASE)
  39 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
  40
  41 /* Flash(NOR) S29JL064H */
  42 #define CONFIG_SYS_FLASH_BASE           (0xA0000000)
  43 #define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
  44 #define CONFIG_SYS_MAX_FLASH_BANKS (1)
  45 #define CONFIG_SYS_MAX_FLASH_SECT  (150)
  46
  47 /* U-Boot setting */
  48 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
  49 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
  50 #define CONFIG_SYS_MONITOR_LEN          (128 * 1024)
  51 /* Size of DRAM reserved for malloc() use */
  52 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
  53 #define CONFIG_SYS_BOOTMAPSZ            (8 * 1024 * 1024)
  54
  55 #define CONFIG_SYS_FLASH_CFI
  56 #define CONFIG_FLASH_CFI_DRIVER
  57 #undef  CONFIG_SYS_FLASH_QUIET_TEST
  58 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* print 'E' for empty sector on flinfo */
  59 /* Timeout for Flash erase operations (in ms) */
  60 #define CONFIG_SYS_FLASH_ERASE_TOUT     (3 * 1000)
  61 /* Timeout for Flash write operations (in ms) */
  62 #define CONFIG_SYS_FLASH_WRITE_TOUT     (3 * 1000)
  63 /* Timeout for Flash set sector lock bit operations (in ms) */
  64 #define CONFIG_SYS_FLASH_LOCK_TOUT              (3 * 1000)
  65 /* Timeout for Flash clear lock bit operations (in ms) */
  66 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (3 * 1000)
  67 /* Use hardware flash sectors protection instead of U-Boot software protection */
  68 #undef  CONFIG_SYS_FLASH_PROTECTION
  69 #undef  CONFIG_SYS_DIRECT_FLASH_TFTP
  70 #define CONFIG_ENV_SECT_SIZE    (128 * 1024)
  71 #define CONFIG_ENV_SIZE         (CONFIG_ENV_SECT_SIZE)
  72 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
  73 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
  74 #define CONFIG_ENV_OFFSET               (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
  75 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SECT_SIZE)
  76 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
  77
  78 /* Clock */
  79 #define CONFIG_SYS_CLK_FREQ     66666666
  80 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
  81 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
  82 #define CONFIG_SYS_TMU_CLK_DIV      4
  83
  84 /* Ether */
  85 #define CONFIG_SH_ETHER 1
  86 #define CONFIG_SH_ETHER_USE_PORT (1)
  87 #define CONFIG_SH_ETHER_PHY_ADDR (0x00)
  88 #define CONFIG_BITBANGMII
  89 #define CONFIG_BITBANGMII_MULTI
  90 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
  91
  92 #endif /* __SH7763RDP_H */