include/configs/galaxy5200.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2006
   6  * Eric Schumann, Phytec Messatechnik GmbH
   7  *
   8  * (C) Copyright 2009
   9  * Jon Smirl <jonsmirl@gmail.com>
  10  *
  11  * (C) Copyright 2009
  12  * Eric Millbrandt, DEKA Research and Development Corporation
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0+
  15  */
  16
  17 #ifndef __CONFIG_H
  18 #define __CONFIG_H
  19
  20 #define CONFIG_BOARDINFO         "galaxy5200"
  21
  22 /*
  23  * High Level Configuration Options
  24  * (easy to change)
  25  */
  26 #define CONFIG_MPC5200          1       /* This is an MPC5200 CPU */
  27 #define CONFIG_SYS_MPC5XXX_CLKIN 33333333       /* ... running at 33.333333MHz */
  28
  29 /*
  30  * Valid values for CONFIG_SYS_TEXT_BASE are:
  31  * 0xFFF00000   boot high (standard configuration)
  32  * 0xFE000000   boot low
  33  * 0x00100000   boot from RAM (for testing only) does not work
  34  */
  35 #ifdef CONFIG_galaxy5200_LOWBOOT
  36 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  37 #endif
  38
  39 #ifndef CONFIG_SYS_TEXT_BASE
  40 #define CONFIG_SYS_TEXT_BASE    0xFFF00000      /* Standard: boot high */
  41 #endif
  42
  43 /*
  44  * Serial console configuration
  45  */
  46 #define CONFIG_PSC_CONSOLE      4       /* console is on PSC4 -> */
  47                                         /* define gps port conf. */
  48                                         /* register later on to  */
  49                                         /* enable UART function! */
  50 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  51 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
  52
  53 /*
  54  * Command line configuration.
  55  */
  56 #include <config_cmd_default.h>
  57
  58 #define CONFIG_CMD_DATE
  59 #define CONFIG_CMD_DHCP
  60 #define CONFIG_CMD_EEPROM
  61 #define CONFIG_CMD_I2C
  62 #define CONFIG_CMD_JFFS2
  63 #define CONFIG_CMD_MII
  64 #define CONFIG_CMD_NFS
  65 #define CONFIG_CMD_SNTP
  66 #define CONFIG_CMD_PING
  67 #define CONFIG_CMD_ASKENV
  68 #define CONFIG_CMD_USB
  69 #define CONFIG_CMD_CACHE
  70 #define CONFIG_CMD_FAT
  71
  72 #define CONFIG_TIMESTAMP        1       /* Print image info with timestamp */
  73
  74 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000)                /* Boot low */
  75 #define CONFIG_SYS_LOWBOOT 1
  76 #endif
  77 /* RAMBOOT will be defined automatically in memory section */
  78
  79 #define MTDIDS_DEFAULT          "nor0=physmap-flash.0"
  80 #define MTDPARTS_DEFAULT        "mtdparts=physmap-flash.0:256k(ubootl)," \
  81         "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
  82
  83 /*
  84  * Autobooting
  85  */
  86 #define CONFIG_BOOTDELAY        10      /* autoboot after 10 seconds */
  87 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* allow stopping of boot process */
  88                                         /* even with bootdelay=0 */
  89 #define CONFIG_BOOT_RETRY_TIME 120      /* Reset if no command is entered  */
  90 #define CONFIG_RESET_TO_RETRY
  91
  92 #define CONFIG_PREBOOT  "echo;" \
  93         "echo Welcome to U-Boot;"\
  94         "echo"
  95
  96 #define CONFIG_BOOTCOMMAND     "go ff300004 0; go ff300004 2 2;" \
  97         "bootm ff040000 ff900000 fffc0000"
  98 #define CONFIG_BOOTARGS        "console=ttyPSC0,115200"
  99 #define CONFIG_EXTRA_ENV_SETTINGS "epson=yes\0"
 100
 101 /*
 102  * IPB Bus clocking configuration.
 103  */
 104 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
 105 #define CONFIG_SYS_XLB_PIPELINING       1
 106
 107 /*
 108  * I2C configuration
 109  */
 110 #define CONFIG_HARD_I2C 1               /* I2C with hardware support */
 111 #define CONFIG_SYS_I2C_MODULE 2         /* Select I2C module #1 or #2 */
 112 #define CONFIG_SYS_I2C_SPEED 100000     /* 100 kHz */
 113 #define CONFIG_SYS_I2C_SLAVE 0x7F
 114 #define CONFIG_SYS_I2C_INIT_MPC5XXX     /* Reset devices on i2c bus */
 115
 116 /*
 117  * EEPROM CAT24WC32 configuration
 118  */
 119 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52    /* 1010100x */
 120 #define CONFIG_SYS_I2C_FACT_ADDR        0x52    /* EEPROM CAT24WC32 */
 121 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2       /* Bytes of address */
 122 #define CONFIG_SYS_EEPROM_SIZE          4096
 123 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 124 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
 125
 126 /*
 127  * RTC configuration
 128  */
 129 #define RTC
 130 #define CONFIG_RTC_DS3231               1
 131 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 132
 133 /*
 134  * Flash configuration
 135  */
 136
 137 #define CONFIG_SYS_FLASH_BASE           0xfe000000
 138 /*
 139  * The flash size is autoconfigured, but arch/powerpc/cpu/mpc5xxx/cpu_init.c needs this
 140  * variable defined
 141  */
 142 #define CONFIG_SYS_FLASH_SIZE           0x02000000
 143 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 144
 145 #define CONFIG_SYS_FLASH_CFI 1          /* Flash is CFI conformant */
 146 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 147 #define CONFIG_SYS_FLASH_EMPTY_INFO
 148 #define CONFIG_SYS_MAX_FLASH_SECT 259   /* max num of sects on one chip */
 149 #define CONFIG_SYS_MAX_FLASH_BANKS 1    /* max num of flash banks */
 150                                         /* (= chip selects) */
 151 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 152
 153 /*
 154  * Use hardware protection. This seems required, as the BDI uses hardware
 155  * protection. Without this, U-Boot can't work with this sectors as its
 156  * protection is software only by default.
 157  */
 158 #define CONFIG_SYS_FLASH_PROTECTION     1
 159
 160 /*
 161  * Environment settings
 162  */
 163
 164 #define CONFIG_ENV_IS_IN_EEPROM 1
 165 #define CONFIG_ENV_OFFSET       0x00    /* environment starts at the */
 166                                         /* beginning of the EEPROM */
 167 #define CONFIG_ENV_SIZE         CONFIG_SYS_EEPROM_SIZE
 168
 169 #define CONFIG_ENV_OVERWRITE    1
 170
 171 /*
 172  * SDRAM configuration
 173  */
 174 #define SDRAM_DDR       1
 175 #define SDRAM_MODE      0x018D0000
 176 #define SDRAM_EMODE     0x40090000
 177 #define SDRAM_CONTROL   0x71500F00
 178 #define SDRAM_CONFIG1   0x73711930
 179 #define SDRAM_CONFIG2   0x47770000
 180
 181 /*
 182  * Memory map
 183  */
 184 #define CONFIG_SYS_MBAR 0xF0000000      /* MBAR has to be switched by other */
 185                                         /* bootloader or debugger config */
 186 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 187 #define CONFIG_SYS_DEFAULT_MBAR         0x80000000
 188
 189 /* Use SRAM until RAM will be available */
 190 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 191
 192 /* End of used area in SPRAM */
 193 #define CONFIG_SYS_INIT_RAM_SIZE                MPC5XXX_SRAM_SIZE
 194
 195 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 196                                                 GENERATED_GBL_DATA_SIZE)
 197 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 198
 199 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 200 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 201 #       define CONFIG_SYS_RAMBOOT               1
 202 #endif
 203
 204 #define CONFIG_SYS_MONITOR_LEN (192 << 10)      /* Reserve 192 kB for Monitor */
 205 #define CONFIG_SYS_MALLOC_LEN (128 << 10)       /* Reserve 128 kB for malloc() */
 206 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)  /* Initial Memory map for Linux */
 207
 208 /* Chip Select configuration for NAND flash */
 209 #define CONFIG_SYS_CS1_START            0x20000000
 210 #define CONFIG_SYS_CS1_SIZE             0x90000
 211 #define CONFIG_SYS_CS1_CFG              0x00025b00
 212
 213 /* Chip Select configuration for Epson S1D13513 */
 214 #define CONFIG_SYS_CS3_START            0x10000000
 215 #define CONFIG_SYS_CS3_SIZE             0x400000
 216 #define CONFIG_SYS_CS3_CFG              0xffff3d10
 217
 218 /*
 219  * Ethernet configuration
 220  */
 221 #define CONFIG_MPC5xxx_FEC              1
 222 #define CONFIG_MPC5xxx_FEC_MII100
 223 #define CONFIG_PHY_ADDR                 0x01
 224 #define CONFIG_NO_AUTOLOAD              1
 225
 226 /*
 227  * GPIO configuration
 228  *
 229  * GPS port configuration
 230  *
 231  * [29:31] = 01x
 232  * AC97 on PSC1
 233  * PSC1_0 -> AC97 SDATA out
 234  * PSC1_1 -> AC97 SDTA in
 235  * PSC1_2 -> AC97 SYNC out
 236  * PSC1_3 -> AC97 bitclock out
 237  * PSC1_4 -> AC97 reset out
 238  *
 239  * [28] = Reserved
 240  *
 241  * [25:27] = 110
 242  * SPI on PSC2
 243  * PSC2_0 -> MOSI
 244  * PSC2_1 -> MISO
 245  * PSC2_2 -> n/a
 246  * PSC2_3 -> CLK
 247  * PSC2_4 -> SS
 248  *
 249  * [24] = Reserved
 250  *
 251  * [20:23] = 0001
 252  * USB on PSC3
 253  * PSC3_0 -> USB_OE OE out
 254  * PSC3_1 -> USB_TXN Tx- out
 255  * PSC3_2 -> USB_TXP Tx+ out
 256  * PSC3_3 -> USB_TXD
 257  * PSC3_4 -> USB_RXP Rx+ in
 258  * PSC3_5 -> USB_RXN Rx- in
 259  * PSC3_6 -> USB_PWR PortPower out
 260  * PSC3_7 -> USB_SPEED speed out
 261  * PSC3_8 -> USB_SUSPEND suspend
 262  * PSC3_9 -> USB_OVRCURNT overcurrent in
 263  *
 264  * [18:19] = 10
 265  * Two UARTs
 266  *
 267  * [17] = 0
 268  * USB differential mode
 269  *
 270  * [16] = 1
 271  * PCI disabled
 272  *
 273  * [12:15] = 0101
 274  * Ethernet 100Mbit with MD
 275  * ETH_0 -> ETH Txen
 276  * ETH_1 -> ETH TxD0
 277  * ETH_2 -> ETH TxD1
 278  * ETH_3 -> ETH TxD2
 279  * ETH_4 -> ETH TxD3
 280  * ETH_5 -> ETH Txerr
 281  * ETH_6 -> ETH MDC
 282  * ETH_7 -> ETH MDIO
 283  * ETH_8 -> ETH RxDv
 284  * ETH_9 -> ETH RxCLK
 285  * ETH_10 -> ETH Collision
 286  * ETH_11 -> ETH TxD
 287  * ETH_12 -> ETH RxD0
 288  * ETH_13 -> ETH RxD1
 289  * ETH_14 -> ETH RxD2
 290  * ETH_15 -> ETH RxD3
 291  * ETH_16 -> ETH Rxerr
 292  * ETH_17 -> ETH CRS
 293  *
 294  * [9:11] = 111
 295  * SPI on PSC6
 296  * PSC6_0 -> MISO
 297  * PSC6_1 -> SS#
 298  * PSC6_2 -> MOSI
 299  * PSC6_3 -> CLK
 300  *
 301  * [8] = 0
 302  * IrDA/USB 48MHz clock generated internally
 303  *
 304  * [6:7] = 01
 305  * ATA chip selects on csb_4/5
 306  * CSB_4 -> ATA_CS0 out
 307  * CSB_5 -> ATA_CS1 out
 308  *
 309  * [5] = 1
 310  * PSC3_4 is used as CS6
 311  *
 312  * [4] = 1
 313  * PSC3_5 is used as CS7
 314  *
 315  * [2:3] = 00
 316  * No Alternatives
 317  *
 318  * [1] = 0
 319  * gpio_wkup_7 is GPIO
 320  *
 321  * [0] = 0
 322  * gpio_wkup_6 is GPIO
 323  *
 324  */
 325 #define CONFIG_SYS_GPS_PORT_CONFIG      0x0d75a162
 326
 327 /*
 328  * Miscellaneous configurable options
 329  */
 330 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 331 #define CONFIG_SYS_PROMPT "uboot> "             /* Monitor Command Prompt */
 332
 333 #define CONFIG_CMDLINE_EDITING 1                /* add command line history */
 334
 335 #define CONFIG_SYS_CACHELINE_SIZE 32            /* For MPC5xxx CPUs */
 336 #if defined(CONFIG_CMD_KGDB)
 337 #define CONFIG_SYS_CACHELINE_SHIFT 5            /* log base 2 of the above value */
 338 #endif
 339
 340 #if defined(CONFIG_CMD_KGDB)
 341 #define CONFIG_SYS_CBSIZE 1024                  /* Console I/O Buffer Size */
 342 #else
 343 #define CONFIG_SYS_CBSIZE 512                   /* Console I/O Buffer Size */
 344 #endif
 345 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 346                                                 /* Print Buffer Size */
 347 #define CONFIG_SYS_MAXARGS 32                   /* max number of command args */
 348 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE   /* Boot Argument Buffer Size */
 349
 350 #define CONFIG_SYS_MEMTEST_START 0x00100000     /* memtest works on */
 351 #define CONFIG_SYS_MEMTEST_END 0x00f00000       /* 1 ... 15 MB in DRAM */
 352
 353 #define CONFIG_SYS_LOAD_ADDR 0x400000           /* default load address */
 354
 355 #define CONFIG_DISPLAY_BOARDINFO 1
 356
 357 #define CONFIG_SYS_HUSH_PARSER 1
 358
 359 #define CONFIG_CRC32_VERIFY  1
 360
 361 #define CONFIG_BOOTP_DNS
 362 #define CONFIG_BOOTP_DNS2
 363 #define CONFIG_BOOTP_SEND_HOSTNAME
 364
 365 #define CONFIG_VERSION_VARIABLE 1
 366
 367 /*
 368  * Various low-level settings
 369  */
 370 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 371 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 372
 373 /* no burst access on the LPB */
 374 #define CONFIG_SYS_CS_BURST             0x00000000
 375 /* one deadcycle for the 33MHz statemachine */
 376 #define CONFIG_SYS_CS_DEADCYCLE         0x33333331
 377
 378 #define CONFIG_SYS_BOOTCS_CFG           0x0002d900
 379 #define CONFIG_SYS_BOOTCS_START         CONFIG_SYS_FLASH_BASE
 380 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 381
 382 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 383
 384 /*
 385  * USB settings
 386  */
 387 #define CONFIG_USB_CLOCK                0x0001bbbb
 388 /* USB is on PSC3 */
 389 #define CONFIG_PSC3_USB
 390 #define CONFIG_USB_CONFIG               0x00000100
 391 #define CONFIG_USB_OHCI
 392 #define CONFIG_USB_STORAGE
 393
 394 /*
 395  * IDE/ATA stuff Supports IDE harddisk
 396  */
 397 #undef  CONFIG_IDE_8xx_PCCARD   /* Use IDE with PC Card Adapter */
 398 #undef  CONFIG_IDE_8xx_DIRECT   /* Direct IDE not supported */
 399 #undef  CONFIG_IDE_LED          /* LED for ide not supported */
 400
 401 #define CONFIG_IDE_RESET 1      /* reset for ide supported */
 402 #define CONFIG_IDE_PREINIT
 403 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
 404 #define CONFIG_SYS_IDE_MAXDEVICE 2      /* max. 2 drives per IDE bus */
 405 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 406 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 407 /* Offset for data I/O                  */
 408 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 409 /* Offset for normal register accesses  */
 410 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 411 /* Offset for alternate registers       */
 412 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 413 /* Interval between registers */
 414 #define CONFIG_SYS_ATA_STRIDE           4
 415 #define CONFIG_ATAPI                    1
 416
 417 /* we enable IDE and FAT support, so we also need partition support */
 418 #define CONFIG_DOS_PARTITION 1
 419
 420 /*
 421  * Open Firmware flat tree
 422  */
 423 #define CONFIG_OF_LIBFDT                1
 424 #define CONFIG_OF_BOARD_SETUP           1
 425
 426 #define OF_CPU                          "PowerPC,5200@0"
 427 #define OF_TBCLK                        CONFIG_SYS_MPC5XXX_CLKIN
 428 #define OF_SOC                          "soc5200@f0000000"
 429 #define OF_STDOUT_PATH                  "/soc5200@f0000000/serial@2600"
 430
 431 #endif /* __CONFIG_H */