include/configs/gw8260.h

   1 /*
   2  * (C) Copyright 2000
   3  * Murray Jensen <Murray.Jensen@cmst.csiro.au>
   4  *
   5  * (C) Copyright 2000
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * (C) Copyright 2001
  10  * Advent Networks, Inc. <http://www.adventnetworks.com>
  11  * Jay Monkman <jmonkman@adventnetworks.com>
  12  *
  13  * (C) Copyright 2001
  14  * Advent Networks, Inc. <http://www.adventnetworks.com>
  15  * Oliver Brown <obrown@adventnetworks.com>
  16  *
  17  * See file CREDITS for list of people who contributed to this
  18  * project.
  19  *
  20  * This program is free software; you can redistribute it and/or
  21  * modify it under the terms of the GNU General Public License as
  22  * published by the Free Software Foundation; either version 2 of
  23  * the License, or (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33  * MA 02111-1307 USA
  34  */
  35
  36 /*********************************************************************/
  37 /* DESCRIPTION:
  38  *   This file contains the board configuartion for the GW8260 board.
  39  *
  40  * MODULE DEPENDENCY:
  41  *   None
  42  *
  43  * RESTRICTIONS/LIMITATIONS:
  44  *   None
  45  *
  46  * Copyright (c) 2001, Advent Networks, Inc.
  47  */
  48 /*********************************************************************/
  49
  50 #ifndef __CONFIG_H
  51 #define __CONFIG_H
  52
  53 #define CONFIG_SYS_TEXT_BASE    0x40000000
  54
  55 /* Enable debug prints */
  56 #undef DEBUG_BOOTP_EXT        /* Debug received vendor fields */
  57
  58 /* What is the oscillator's (UX2) frequency in Hz? */
  59 #define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
  60
  61 /*-----------------------------------------------------------------------
  62  * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
  63  *-----------------------------------------------------------------------
  64  * What should MODCK_H be? It is dependent on the oscillator
  65  * frequency, MODCK[1-3], and desired CPM and core frequencies.
  66  * Here are some example values (all frequencies are in MHz):
  67  *
  68  * MODCK_H   MODCK[1-3]  Osc    CPM    Core  S2-6   S2-7   S2-8
  69  * -------   ----------  ---    ---    ----  -----  -----  -----
  70  * 0x5       0x5     66 133     133    Open  Close  Open
  71  * 0x5       0x6     66 133     166    Open  Open   Close
  72  * 0x5       0x7     66 133     200    Open  Open   Open
  73  * 0x6       0x0     66 133     233    Close Close  Close
  74  * 0x6       0x1     66 133     266    Close Close  Open
  75  * 0x6       0x2     66 133     300    Close Open   Close
  76  */
  77 #define CONFIG_SYS_SBC_MODCK_H 0x05
  78
  79 /* Define this if you want to boot from 0x00000100. If you don't define
  80  * this, you will need to program the bootloader to 0xfff00000, and
  81  * get the hardware reset config words at 0xfe000000. The simplest
  82  * way to do that is to program the bootloader at both addresses.
  83  * It is suggested that you just let U-Boot live at 0x00000000.
  84  */
  85 #define CONFIG_SYS_SBC_BOOT_LOW 1
  86
  87 /* What should the base address of the main FLASH be and how big is
  88  * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/sbc8260/config.mk
  89  * The main FLASH is whichever is connected to *CS0. U-Boot expects
  90  * this to be the SIMM.
  91  */
  92 #define CONFIG_SYS_FLASH0_BASE 0x40000000
  93 #define CONFIG_SYS_FLASH0_SIZE 8
  94
  95 /* Define CONFIG_SYS_FLASH_CHECKSUM to enable flash checksum during boot.
  96  * Note: the 'flashchecksum' environment variable must also be set to 'y'.
  97  */
  98 #define CONFIG_SYS_FLASH_CHECKSUM
  99
 100 /* What should be the base address of SDRAM DIMM and how big is
 101  * it (in Mbytes)?
 102  */
 103 #define CONFIG_SYS_SDRAM0_BASE 0x00000000
 104 #define CONFIG_SYS_SDRAM0_SIZE 64
 105
 106 /*
 107  * DRAM tests
 108  *   CONFIG_SYS_DRAM_TEST - enables the following tests.
 109  *
 110  *   CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
 111  *                        Environment variable 'test_dram_data' must be
 112  *                        set to 'y'.
 113  *   CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
 114  *                        addressable. Environment variable
 115  *                        'test_dram_address' must be set to 'y'.
 116  *   CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
 117  *                        This test takes about 6 minutes to test 64 MB.
 118  *                        Environment variable 'test_dram_walk' must be
 119  *                        set to 'y'.
 120  */
 121 #define CONFIG_SYS_DRAM_TEST
 122 #if defined(CONFIG_SYS_DRAM_TEST)
 123 #define CONFIG_SYS_DRAM_TEST_DATA
 124 #define CONFIG_SYS_DRAM_TEST_ADDRESS
 125 #define CONFIG_SYS_DRAM_TEST_WALK
 126 #endif /* CONFIG_SYS_DRAM_TEST */
 127
 128 /*
 129  * GW8260 with 16 MB DIMM:
 130  *
 131  *     0x0000 0000     Exception Vector code, 8k
 132  *           :
 133  *     0x0000 1FFF
 134  *     0x0000 2000     Free for Application Use
 135  *           :
 136  *           :
 137  *
 138  *           :
 139  *           :
 140  *     0x00F5 FF30     Monitor Stack (Growing downward)
 141  *                     Monitor Stack Buffer (0x80)
 142  *     0x00F5 FFB0     Board Info Data
 143  *     0x00F6 0000     Malloc Arena
 144  *           :          CONFIG_ENV_SECT_SIZE, 256k
 145  *           :          CONFIG_SYS_MALLOC_LEN,    128k
 146  *     0x00FC 0000     RAM Copy of Monitor Code
 147  *           :              CONFIG_SYS_MONITOR_LEN,   256k
 148  *     0x00FF FFFF     [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
 149  */
 150
 151 /*
 152  * GW8260 with 64 MB DIMM:
 153  *
 154  *     0x0000 0000     Exception Vector code, 8k
 155  *           :
 156  *     0x0000 1FFF
 157  *     0x0000 2000     Free for Application Use
 158  *           :
 159  *           :
 160  *
 161  *           :
 162  *           :
 163  *     0x03F5 FF30     Monitor Stack (Growing downward)
 164  *                     Monitor Stack Buffer (0x80)
 165  *     0x03F5 FFB0     Board Info Data
 166  *     0x03F6 0000     Malloc Arena
 167  *           :          CONFIG_ENV_SECT_SIZE, 256k
 168  *           :          CONFIG_SYS_MALLOC_LEN,    128k
 169  *     0x03FC 0000     RAM Copy of Monitor Code
 170  *           :              CONFIG_SYS_MONITOR_LEN,   256k
 171  *     0x03FF FFFF     [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
 172  */
 173
 174
 175 /*
 176  * select serial console configuration
 177  *
 178  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 179  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 180  * for SCC).
 181  *
 182  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 183  * defined elsewhere.
 184  */
 185 #define CONFIG_CONS_ON_SMC  1   /* define if console on SMC */
 186 #undef  CONFIG_CONS_ON_SCC      /* define if console on SCC */
 187 #undef  CONFIG_CONS_NONE        /* define if console on neither */
 188 #define CONFIG_CONS_INDEX   1   /* which SMC/SCC channel for console */
 189
 190 /*
 191  * select ethernet configuration
 192  *
 193  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 194  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 195  * for FCC)
 196  *
 197  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 198  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 199  */
 200
 201 #undef  CONFIG_ETHER_ON_SCC
 202 #define CONFIG_ETHER_ON_FCC
 203 #undef  CONFIG_ETHER_NONE       /* define if ethernet on neither */
 204
 205 #ifdef  CONFIG_ETHER_ON_SCC
 206 #define CONFIG_ETHER_INDEX  1   /* which SCC/FCC channel for ethernet */
 207 #endif  /* CONFIG_ETHER_ON_SCC */
 208
 209 #ifdef  CONFIG_ETHER_ON_FCC
 210 #define CONFIG_ETHER_INDEX  2   /* which SCC/FCC channel for ethernet */
 211 #define CONFIG_MII              /* MII PHY management           */
 212 #define CONFIG_BITBANGMII       /* bit-bang MII PHY management  */
 213 /*
 214  * Port pins used for bit-banged MII communictions (if applicable).
 215  */
 216 #define MDIO_PORT   2       /* Port C */
 217
 218 #define MDIO_DECLARE    volatile ioport_t *iop = ioport_addr ( \
 219                                 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 220 #define MDC_DECLARE     MDIO_DECLARE
 221
 222 #define MDIO_ACTIVE    (iop->pdir |=  0x00400000)
 223 #define MDIO_TRISTATE  (iop->pdir &= ~0x00400000)
 224 #define MDIO_READ     ((iop->pdat &  0x00400000) != 0)
 225
 226 #define MDIO(bit)   if(bit) iop->pdat |=  0x00400000; \
 227             else            iop->pdat &= ~0x00400000
 228
 229 #define MDC(bit)    if(bit) iop->pdat |=  0x00200000; \
 230             else    iop->pdat &= ~0x00200000
 231
 232 #define MIIDELAY    udelay(1)
 233 #endif  /* CONFIG_ETHER_ON_FCC */
 234
 235 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 236
 237 /*
 238  * - Rx-CLK is CLK13
 239  * - Tx-CLK is CLK14
 240  * - Select bus for bd/buffers (see 28-13)
 241  * - Enable Full Duplex in FSMR
 242  */
 243 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 244 # define CONFIG_SYS_CMXFCR_VALUE        (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 245 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
 246 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
 247
 248 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
 249
 250 /*
 251  * - Rx-CLK is CLK15
 252  * - Tx-CLK is CLK16
 253  * - Select bus for bd/buffers (see 28-13)
 254  * - Enable Full Duplex in FSMR
 255  */
 256 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
 257 # define CONFIG_SYS_CMXFCR_VALUE        (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
 258 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
 259 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
 260
 261 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 262
 263 /* Define this to reserve an entire FLASH sector (256 KB) for
 264  * environment variables. Otherwise, the environment will be
 265  * put in the same sector as U-Boot, and changing variables
 266  * will erase U-Boot temporarily
 267  */
 268 #define CONFIG_ENV_IN_OWN_SECT
 269
 270 /* Define to allow the user to overwrite serial and ethaddr */
 271 #define CONFIG_ENV_OVERWRITE
 272
 273 /* What should the console's baud rate be? */
 274 #define CONFIG_BAUDRATE     115200
 275
 276 /* Ethernet MAC address - This is set to all zeros to force an
 277  *                        an error if we use BOOTP without setting
 278  *                        the MAC address
 279  */
 280 #define CONFIG_ETHADDR      00:00:00:00:00:00
 281
 282 /* Set to a positive value to delay for running BOOTCOMMAND */
 283 #define CONFIG_BOOTDELAY    5   /* autoboot after 5 seconds */
 284
 285 /* Be selective on what keys can delay or stop the autoboot process
 286  *     To stop  use: " "
 287  */
 288 #define CONFIG_AUTOBOOT_KEYED
 289 #define CONFIG_AUTOBOOT_PROMPT  \
 290         "Autobooting in %d seconds, press \" \" to stop\n", bootdelay
 291 #define CONFIG_AUTOBOOT_STOP_STR    " "
 292 #undef  CONFIG_AUTOBOOT_DELAY_STR
 293 #define DEBUG_BOOTKEYS      0
 294
 295 /*
 296  * BOOTP options
 297  */
 298 #define CONFIG_BOOTP_SUBNETMASK
 299 #define CONFIG_BOOTP_GATEWAY
 300 #define CONFIG_BOOTP_HOSTNAME
 301 #define CONFIG_BOOTP_BOOTPATH
 302
 303 #define CONFIG_BOOTP_BOOTFILESIZE
 304 #define CONFIG_BOOTP_DNS
 305
 306 /* undef this to save memory */
 307 #define CONFIG_SYS_LONGHELP
 308
 309 /* Monitor Command Prompt */
 310 #define CONFIG_SYS_PROMPT      "=> "
 311
 312
 313 /*
 314  * Command line configuration.
 315  */
 316 #include <config_cmd_default.h>
 317
 318 #define CONFIG_CMD_BEDBUG
 319 #define CONFIG_CMD_ELF
 320 #define CONFIG_CMD_ASKENV
 321 #define CONFIG_CMD_REGINFO
 322 #define CONFIG_CMD_IMMAP
 323 #define CONFIG_CMD_MII
 324
 325 #undef CONFIG_CMD_KGDB
 326
 327
 328 /* Where do the internal registers live? */
 329 #define CONFIG_SYS_IMMR        0xf0000000
 330
 331 /* Use the HUSH parser */
 332 #define CONFIG_SYS_HUSH_PARSER
 333 #ifdef  CONFIG_SYS_HUSH_PARSER
 334 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 335 #endif
 336
 337 /* What is the address of IO controller */
 338 #define CONFIG_SYS_IO_BASE 0xe0000000
 339
 340 /*****************************************************************************
 341  *
 342  * You should not have to modify any of the following settings
 343  *
 344  *****************************************************************************/
 345
 346 #define CONFIG_MPC8260      1   /* This is an MPC8260 CPU   */
 347 #define CONFIG_GW8260       1   /* on an GW8260 Board  */
 348 #define CONFIG_CPM2             1       /* Has a CPM2 */
 349
 350 /*
 351  * Miscellaneous configurable options
 352  */
 353 #if defined(CONFIG_CMD_KGDB)
 354 #  define CONFIG_SYS_CBSIZE        1024    /* Console I/O Buffer Size       */
 355 #else
 356 #  define CONFIG_SYS_CBSIZE        256     /* Console I/O Buffer Size       */
 357 #endif
 358
 359 /* Print Buffer Size */
 360 #define CONFIG_SYS_PBSIZE    (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
 361
 362 #define CONFIG_SYS_MAXARGS     8          /* max number of command args   */
 363
 364 #define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size    */
 365
 366 /* Convert clocks to MHZ when passing board info to kernel.
 367  * This must be defined for eariler 2.4 kernels (~2.4.4).
 368  */
 369 #define CONFIG_CLOCKS_IN_MHZ
 370
 371 #define CONFIG_SYS_LOAD_ADDR   0x100000 /* default load address */
 372 #define CONFIG_SYS_HZ          1000     /* decrementer freq: 1 ms ticks */
 373
 374
 375 /* memtest works from the end of the exception vector table
 376  * to the end of the DRAM less monitor and malloc area
 377  */
 378 #define CONFIG_SYS_MEMTEST_START   0x2000
 379
 380 #define CONFIG_SYS_STACK_USAGE     0x10000 /* Reserve 64k for the stack usage */
 381
 382 #define CONFIG_SYS_MEM_END_USAGE   ( CONFIG_SYS_MONITOR_LEN \
 383                             + CONFIG_SYS_MALLOC_LEN \
 384                             + CONFIG_ENV_SECT_SIZE \
 385                             + CONFIG_SYS_STACK_USAGE )
 386
 387 #define CONFIG_SYS_MEMTEST_END     ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
 388                             - CONFIG_SYS_MEM_END_USAGE )
 389
 390 /* valid baudrates */
 391 #define CONFIG_SYS_BAUDRATE_TABLE  { 9600, 19200, 38400, 57600, 115200 }
 392
 393 /*
 394  * Low Level Configuration Settings
 395  * (address mappings, register initial values, etc.)
 396  * You should know what you are doing if you make changes here.
 397  */
 398
 399 #define CONFIG_SYS_FLASH_BASE  CONFIG_SYS_FLASH0_BASE
 400 #define CONFIG_SYS_FLASH_SIZE  CONFIG_SYS_FLASH0_SIZE
 401 #define CONFIG_SYS_SDRAM_BASE  CONFIG_SYS_SDRAM0_BASE
 402 #define CONFIG_SYS_SDRAM_SIZE  CONFIG_SYS_SDRAM0_SIZE
 403
 404 /*-----------------------------------------------------------------------
 405  * Hard Reset Configuration Words
 406  */
 407 #if defined(CONFIG_SYS_SBC_BOOT_LOW)
 408 #  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 409 #else
 410 #  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (0)
 411 #endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
 412
 413 /* get the HRCW ISB field from CONFIG_SYS_IMMR */
 414 #define CONFIG_SYS_SBC_HRCW_IMMR   ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
 415                   ((CONFIG_SYS_IMMR & 0x01000000) >>  7) | \
 416                   ((CONFIG_SYS_IMMR & 0x00100000) >>  4) )
 417
 418 #define CONFIG_SYS_HRCW_MASTER     ( HRCW_BPS11                | \
 419                   HRCW_DPPC11               | \
 420                   CONFIG_SYS_SBC_HRCW_IMMR         | \
 421                   HRCW_MMR00                | \
 422                   HRCW_LBPC11               | \
 423                   HRCW_APPC10               | \
 424                   HRCW_CS10PC00             | \
 425                   (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111)  | \
 426                   CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
 427
 428 /* no slaves */
 429 #define CONFIG_SYS_HRCW_SLAVE1     0
 430 #define CONFIG_SYS_HRCW_SLAVE2     0
 431 #define CONFIG_SYS_HRCW_SLAVE3     0
 432 #define CONFIG_SYS_HRCW_SLAVE4     0
 433 #define CONFIG_SYS_HRCW_SLAVE5     0
 434 #define CONFIG_SYS_HRCW_SLAVE6     0
 435 #define CONFIG_SYS_HRCW_SLAVE7     0
 436
 437 /*-----------------------------------------------------------------------
 438  * Definitions for initial stack pointer and data area (in DPRAM)
 439  */
 440 #define CONFIG_SYS_INIT_RAM_ADDR    CONFIG_SYS_IMMR
 441 #define CONFIG_SYS_INIT_RAM_SIZE     0x4000  /* Size of used area in DPRAM    */
 442 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 443 #define CONFIG_SYS_INIT_SP_OFFSET   CONFIG_SYS_GBL_DATA_OFFSET
 444
 445 /*-----------------------------------------------------------------------
 446  * Start addresses for the final memory configuration
 447  * (Set up by the startup code)
 448  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 449  * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
 450  */
 451 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_FLASH0_BASE
 452
 453 #define CONFIG_SYS_MONITOR_LEN     (256 * 1024) /* Reserve 256 kB for Monitor   */
 454 #define CONFIG_SYS_MALLOC_LEN      (128 * 1024) /* Reserve 128 kB for malloc()  */
 455
 456 /*
 457  * For booting Linux, the board info and command line data
 458  * have to be in the first 8 MB of memory, since this is
 459  * the maximum mapped by the Linux kernel during initialization.
 460  */
 461 #define CONFIG_SYS_BOOTMAPSZ       (8 * 1024 * 1024) /* Initial Memory map for Linux */
 462
 463 /*-----------------------------------------------------------------------
 464  * FLASH and environment organization
 465  */
 466 #define CONFIG_SYS_MAX_FLASH_BANKS   1    /* max number of memory banks        */
 467 #define CONFIG_SYS_MAX_FLASH_SECT    32   /* max number of sectors on one chip */
 468
 469 #define CONFIG_SYS_FLASH_ERASE_TOUT  8000 /* Timeout for Flash Erase (in ms)   */
 470 #define CONFIG_SYS_FLASH_WRITE_TOUT  1    /* Timeout for Flash Write (in ms)   */
 471
 472 #define CONFIG_ENV_IS_IN_FLASH   1
 473
 474 #ifdef CONFIG_ENV_IN_OWN_SECT
 475 #  define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE +  (256 * 1024))
 476 #  define CONFIG_ENV_SECT_SIZE   (256 * 1024)
 477 #else
 478 #  define CONFIG_ENV_SIZE        (16 * 1024)/* Size of Environment Sector  */
 479 #  define CONFIG_ENV_ADD  ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SIZE)
 480 #  define CONFIG_ENV_SECT_SIZE (256 * 1024)/* see README - env sect real size  */
 481 #endif /* CONFIG_ENV_IN_OWN_SECT */
 482
 483 /*-----------------------------------------------------------------------
 484  * Cache Configuration
 485  */
 486 #define CONFIG_SYS_CACHELINE_SIZE  32      /* For MPC8260 CPU */
 487
 488 #if defined(CONFIG_CMD_KGDB)
 489 # define CONFIG_SYS_CACHELINE_SHIFT    5   /* log base 2 of the above value */
 490 #endif
 491
 492 /*-----------------------------------------------------------------------
 493  * HIDx - Hardware Implementation-dependent Registers            2-11
 494  *-----------------------------------------------------------------------
 495  * HID0 also contains cache control - initially enable both caches and
 496  * invalidate contents, then the final state leaves only the instruction
 497  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 498  * but Soft reset does not.
 499  *
 500  * HID1 has only read-only information - nothing to set.
 501  */
 502 #define CONFIG_SYS_HID0_INIT   (HID0_ICE  |\
 503                          HID0_DCE  |\
 504                          HID0_ICFI |\
 505                          HID0_DCI  |\
 506                          HID0_IFEM |\
 507                          HID0_ABE)
 508
 509 #define CONFIG_SYS_HID0_FINAL  (HID0_ICE  |\
 510                          HID0_IFEM |\
 511                          HID0_ABE  |\
 512                          HID0_EMCP)
 513 #define CONFIG_SYS_HID2    0
 514
 515 /*-----------------------------------------------------------------------
 516  * RMR - Reset Mode Register
 517  *-----------------------------------------------------------------------
 518  */
 519 #define CONFIG_SYS_RMR     0
 520
 521 /*-----------------------------------------------------------------------
 522  * BCR - Bus Configuration                           4-25
 523  *-----------------------------------------------------------------------
 524  */
 525 #define CONFIG_SYS_BCR     (BCR_ETM)
 526
 527 /*-----------------------------------------------------------------------
 528  * SIUMCR - SIU Module Configuration                 4-31
 529  *-----------------------------------------------------------------------
 530  */
 531 #define CONFIG_SYS_SIUMCR  (SIUMCR_DPPC11  |\
 532                      SIUMCR_L2CPC00 |\
 533                      SIUMCR_APPC10  |\
 534                      SIUMCR_MMR00)
 535
 536
 537 /*-----------------------------------------------------------------------
 538  * SYPCR - System Protection Control                11-9
 539  * SYPCR can only be written once after reset!
 540  *-----------------------------------------------------------------------
 541  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 542  */
 543 #define CONFIG_SYS_SYPCR   (SYPCR_SWTC |\
 544                      SYPCR_BMT  |\
 545                      SYPCR_PBME |\
 546                      SYPCR_LBME |\
 547                      SYPCR_SWRI |\
 548                      SYPCR_SWP)
 549
 550 /*-----------------------------------------------------------------------
 551  * TMCNTSC - Time Counter Status and Control             4-40
 552  *-----------------------------------------------------------------------
 553  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 554  * and enable Time Counter
 555  */
 556 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
 557                      TMCNTSC_ALR |\
 558                      TMCNTSC_TCF |\
 559                      TMCNTSC_TCE)
 560
 561 /*-----------------------------------------------------------------------
 562  * PISCR - Periodic Interrupt Status and Control         4-42
 563  *-----------------------------------------------------------------------
 564  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 565  * Periodic timer
 566  */
 567 #define CONFIG_SYS_PISCR   (PISCR_PS  |\
 568                      PISCR_PTF |\
 569                      PISCR_PTE)
 570
 571 /*-----------------------------------------------------------------------
 572  * SCCR - System Clock Control                           9-8
 573  *-----------------------------------------------------------------------
 574  */
 575 #define CONFIG_SYS_SCCR    0
 576
 577 /*-----------------------------------------------------------------------
 578  * RCCR - RISC Controller Configuration                 13-7
 579  *-----------------------------------------------------------------------
 580  */
 581 #define CONFIG_SYS_RCCR    0
 582
 583 /*
 584  * Initialize Memory Controller:
 585  *
 586  * Bank Bus   Machine PortSz  Device
 587  * ---- ---   ------- ------  ------
 588  *  0   60x   GPCM    32 bit  FLASH (SIMM - 4MB)
 589  *  1   60x   GPCM    32 bit  unused
 590  *  2   60x   SDRAM   64 bit  SDRAM (DIMM - 16MB or 64MB)
 591  *  3   60x   SDRAM   64 bit  unused
 592  *  4   Local GPCM     8 bit  IO    (on board - 64k)
 593  *  5   60x   GPCM     8 bit  unused
 594  *  6   60x   GPCM     8 bit  unused
 595  *  7   60x   GPCM     8 bit  unused
 596  *
 597  */
 598
 599 /*-----------------------------------------------------------------------
 600  * BR0 - Base Register
 601  *     Ref: Section 10.3.1 on page 10-14
 602  * OR0 - Option Register
 603  *     Ref: Section 10.3.2 on page 10-18
 604  *-----------------------------------------------------------------------
 605  */
 606
 607 /* Bank 0,1 - FLASH SIMM
 608  *
 609  * This expects the FLASH SIMM to be connected to *CS0
 610  * It consists of 4 AM29F016D parts.
 611  *
 612  * Note: For the 8 MB SIMM, *CS1 is unused.
 613  */
 614
 615 /* BR0 is configured as follows:
 616  *
 617  *     - Base address of 0x40000000
 618  *     - 32 bit port size
 619  *     - Data errors checking is disabled
 620  *     - Read and write access
 621  *     - GPCM 60x bus
 622  *     - Access are handled by the memory controller according to MSEL
 623  *     - Not used for atomic operations
 624  *     - No data pipelining is done
 625  *     - Valid
 626  */
 627 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
 628                           BRx_PS_32                     |\
 629                           BRx_MS_GPCM_P                 |\
 630                           BRx_V)
 631
 632 /* OR0 is configured as follows:
 633  *
 634  *     - 8 MB
 635  *     - *BCTL0 is asserted upon access to the current memory bank
 636  *     - *CW / *WE are negated a quarter of a clock earlier
 637  *     - *CS is output at the same time as the address lines
 638  *     - Uses a clock cycle length of 5
 639  *     - *PSDVAL is generated internally by the memory controller
 640  *       unless *GTA is asserted earlier externally.
 641  *     - Relaxed timing is generated by the GPCM for accesses
 642  *       initiated to this memory region.
 643  *     - One idle clock is inserted between a read access from the
 644  *       current bank and the next access.
 645  */
 646 #define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
 647                          ORxG_CSNT          |\
 648                          ORxG_ACS_DIV1      |\
 649                          ORxG_SCY_5_CLK     |\
 650                          ORxG_TRLX          |\
 651                          ORxG_EHTR)
 652
 653 /*-----------------------------------------------------------------------
 654  * BR2 - Base Register
 655  *     Ref: Section 10.3.1 on page 10-14
 656  * OR2 - Option Register
 657  *     Ref: Section 10.3.2 on page 10-16
 658  *-----------------------------------------------------------------------
 659  */
 660
 661 /* Bank 2 - SDRAM DIMM
 662  *
 663  *     16MB DIMM: P/N
 664  *     64MB DIMM: P/N  1W-8864X8-4-P1-EST or
 665  *                     MT4LSDT864AG-10EB1 (Micron)
 666  *
 667  * Note: *CS3 is unused for this DIMM
 668  */
 669
 670 /* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
 671  *
 672  *     - Base address of 0x00000000
 673  *     - 64 bit port size (60x bus only)
 674  *     - Data errors checking is disabled
 675  *     - Read and write access
 676  *     - SDRAM 60x bus
 677  *     - Access are handled by the memory controller according to MSEL
 678  *     - Not used for atomic operations
 679  *     - No data pipelining is done
 680  *     - Valid
 681  */
 682 #define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
 683                           BRx_PS_64          |\
 684                           BRx_MS_SDRAM_P     |\
 685                           BRx_V)
 686
 687 /* With a 16 MB DIMM, the OR2 is configured as follows:
 688  *
 689  *     - 16 MB
 690  *     - 2 internal banks per device
 691  *     - Row start address bit is A9 with PSDMR[PBI] = 0
 692  *     - 11 row address lines
 693  *     - Back-to-back page mode
 694  *     - Internal bank interleaving within save device enabled
 695  */
 696 #if (CONFIG_SYS_SDRAM0_SIZE == 16)
 697 #define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
 698                          ORxS_BPD_2         |\
 699                          ORxS_ROWST_PBI0_A9 |\
 700                          ORxS_NUMR_11)
 701
 702 /* With a 16 MB DIMM, the PSDMR is configured as follows:
 703  *
 704  *     - Page Based Interleaving,
 705  *     - Refresh Enable,
 706  *     - Address Multiplexing where A5 is output on A14 pin
 707  *       (A6 on A15, and so on),
 708  *     - use address pins A16-A18 as bank select,
 709  *     - A9 is output on SDA10 during an ACTIVATE command,
 710  *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
 711  *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
 712  *       is 3 clocks,
 713  *     - earliest timing for READ/WRITE command after ACTIVATE command is
 714  *       2 clocks,
 715  *     - earliest timing for PRECHARGE after last data was read is 1 clock,
 716  *     - earliest timing for PRECHARGE after last data was written is 1 clock,
 717  *     - CAS Latency is 2.
 718  */
 719
 720 /*-----------------------------------------------------------------------
 721  * PSDMR - 60x Bus SDRAM Mode Register
 722  *     Ref: Section 10.3.3 on page 10-21
 723  *-----------------------------------------------------------------------
 724  */
 725 #define CONFIG_SYS_PSDMR   (PSDMR_RFEN       |\
 726                      PSDMR_SDAM_A14_IS_A5 |\
 727                      PSDMR_BSMA_A16_A18   |\
 728                      PSDMR_SDA10_PBI0_A9  |\
 729                      PSDMR_RFRC_7_CLK     |\
 730                      PSDMR_PRETOACT_3W    |\
 731                      PSDMR_ACTTORW_2W     |\
 732                      PSDMR_LDOTOPRE_1C    |\
 733                      PSDMR_WRC_1C         |\
 734                      PSDMR_CL_2)
 735 #endif /* (CONFIG_SYS_SDRAM0_SIZE == 16) */
 736
 737 /* With a 64 MB DIMM, the OR2 is configured as follows:
 738  *
 739  *     - 64 MB
 740  *     - 4 internal banks per device
 741  *     - Row start address bit is A8 with PSDMR[PBI] = 0
 742  *     - 12 row address lines
 743  *     - Back-to-back page mode
 744  *     - Internal bank interleaving within save device enabled
 745  */
 746 #if (CONFIG_SYS_SDRAM0_SIZE == 64)
 747 #define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
 748              ORxS_BPD_4         |\
 749              ORxS_ROWST_PBI0_A8     |\
 750              ORxS_NUMR_12)
 751
 752 /* With a 64 MB DIMM, the PSDMR is configured as follows:
 753  *
 754  *     - Page Based Interleaving,
 755  *     - Refresh Enable,
 756  *     - Address Multiplexing where A5 is output on A14 pin
 757  *       (A6 on A15, and so on),
 758  *     - use address pins A14-A16 as bank select,
 759  *     - A9 is output on SDA10 during an ACTIVATE command,
 760  *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
 761  *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
 762  *       is 3 clocks,
 763  *     - earliest timing for READ/WRITE command after ACTIVATE command is
 764  *       2 clocks,
 765  *     - earliest timing for PRECHARGE after last data was read is 1 clock,
 766  *     - earliest timing for PRECHARGE after last data was written is 1 clock,
 767  *     - CAS Latency is 2.
 768  */
 769
 770 /*-----------------------------------------------------------------------
 771  * PSDMR - 60x Bus SDRAM Mode Register
 772  *     Ref: Section 10.3.3 on page 10-21
 773  *-----------------------------------------------------------------------
 774  */
 775 #define CONFIG_SYS_PSDMR   (PSDMR_RFEN       |\
 776                      PSDMR_SDAM_A14_IS_A5 |\
 777                      PSDMR_BSMA_A14_A16   |\
 778                      PSDMR_SDA10_PBI0_A9  |\
 779                      PSDMR_RFRC_7_CLK     |\
 780                      PSDMR_PRETOACT_3W    |\
 781                      PSDMR_ACTTORW_2W     |\
 782                      PSDMR_LDOTOPRE_1C    |\
 783                      PSDMR_WRC_1C         |\
 784                      PSDMR_CL_2)
 785 #endif  /* (CONFIG_SYS_SDRAM0_SIZE == 64) */
 786
 787 #define CONFIG_SYS_PSRT    0x0e
 788 #define CONFIG_SYS_MPTPR   MPTPR_PTP_DIV32
 789
 790
 791 /*-----------------------------------------------------------------------
 792  * BR4 - Base Register
 793  *     Ref: Section 10.3.1 on page 10-14
 794  * OR4 - Option Register
 795  *     Ref: Section 10.3.2 on page 10-18
 796  *-----------------------------------------------------------------------
 797  */
 798 /* Bank 4 - Onboard Memory Mapped IO controller
 799  *
 800  * This expects the onboard IO controller to connected to *CS4 and
 801  * the local bus.
 802  *     - Base address of 0xe0000000
 803  *     - 8 bit port size (local bus only)
 804  *     - Read and write access
 805  *     - GPCM local bus
 806  *     - Not used for atomic operations
 807  *     - No data pipelining is done
 808  *     - Valid
 809  *     - extended hold time
 810  *     - 11 wait states
 811  */
 812
 813 #ifdef CONFIG_SYS_IO_BASE
 814 #  define CONFIG_SYS_BR4_PRELIM  ((CONFIG_SYS_IO_BASE & BRx_BA_MSK)  |\
 815                             BRx_PS_8                   |\
 816                             BRx_MS_GPCM_L              |\
 817                             BRx_V)
 818
 819 #  define CONFIG_SYS_OR4_PRELIM   (ORxG_AM_MSK                |\
 820                             ORxG_SCY_11_CLK            |\
 821                             ORxG_EHTR)
 822 #endif /* CONFIG_SYS_IO_BASE */
 823 #endif  /* __CONFIG_H */