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pci: move pcidelay code to new location just before PCI bus scan
[people/ms/u-boot.git] / include / configs / hammerhead.h
1 /*
2 * Copyright (C) 2008 Miromico AG
3 *
4 * Configuration settings for the Miromico Hammerhead AVR32 board
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24 #ifndef __CONFIG_H
25 #define __CONFIG_H
26
27 #define CONFIG_AVR32
28 #define CONFIG_AT32AP
29 #define CONFIG_AT32AP7000
30 #define CONFIG_HAMMERHEAD
31
32 #define CONFIG_SYS_HZ 1000
33
34 /*
35 * Set up the PLL to run at 125 MHz, the CPU to run at the PLL
36 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
37 * and the PBA bus to run at 1/4 the PLL frequency.
38 */
39 #define CONFIG_PLL
40 #define CONFIG_SYS_POWER_MANAGER
41 #define CONFIG_SYS_OSC0_HZ 25000000
42 #define CONFIG_SYS_PLL0_DIV 1
43 #define CONFIG_SYS_PLL0_MUL 5
44 #define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
45 #define CONFIG_SYS_CLKDIV_CPU 0
46 #define CONFIG_SYS_CLKDIV_HSB 1
47 #define CONFIG_SYS_CLKDIV_PBA 2
48 #define CONFIG_SYS_CLKDIV_PBB 1
49
50 /* Reserve VM regions for SDRAM and NOR flash */
51 #define CONFIG_SYS_NR_VM_REGIONS 2
52
53 /*
54 * The PLLOPT register controls the PLL like this:
55 * icp = PLLOPT<2>
56 * ivco = PLLOPT<1:0>
57 *
58 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
59 */
60 #define CONFIG_SYS_PLL0_OPT 0x04
61
62 #define CONFIG_USART_BASE ATMEL_BASE_USART1
63 #define CONFIG_USART_ID 1
64
65 #define CONFIG_HOSTNAME hammerhead
66
67 /* User serviceable stuff */
68 #define CONFIG_DOS_PARTITION
69
70 #define CONFIG_CMDLINE_TAG
71 #define CONFIG_SETUP_MEMORY_TAGS
72 #define CONFIG_INITRD_TAG
73
74 #define CONFIG_STACKSIZE (2048)
75
76 #define CONFIG_BAUDRATE 115200
77 #define CONFIG_BOOTARGS \
78 "console=ttyS0 root=mtd1 rootfstype=jffs2"
79 #define CONFIG_BOOTCOMMAND \
80 "fsload; bootm"
81
82 /*
83 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
84 * data on the serial line may interrupt the boot sequence.
85 */
86 #define CONFIG_BOOTDELAY 1
87 #define CONFIG_AUTOBOOT
88 #define CONFIG_AUTOBOOT_KEYED
89 #define CONFIG_AUTOBOOT_PROMPT \
90 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
91 #define CONFIG_AUTOBOOT_DELAY_STR "d"
92 #define CONFIG_AUTOBOOT_STOP_STR " "
93
94 /*
95 * After booting the board for the first time, new ethernet address
96 * should be generated and assigned to the environment variables
97 * "ethaddr". This is normally done during production.
98 */
99 #define CONFIG_OVERWRITE_ETHADDR_ONCE
100
101 /*
102 * BOOTP/DHCP options
103 */
104 #define CONFIG_BOOTP_SUBNETMASK
105 #define CONFIG_BOOTP_GATEWAY
106
107 /*
108 * Command line configuration.
109 */
110 #include <config_cmd_default.h>
111
112 #define CONFIG_CMD_ASKENV
113 #define CONFIG_CMD_DHCP
114 #define CONFIG_CMD_EXT2
115 #define CONFIG_CMD_FAT
116 #define CONFIG_CMD_JFFS2
117 #define CONFIG_CMD_MMC
118 #undef CONFIG_CMD_FPGA
119 #undef CONFIG_CMD_SETGETDCR
120
121 #define CONFIG_ATMEL_USART
122 #define CONFIG_MACB
123 #define CONFIG_PORTMUX_PIO
124 #define CONFIG_SYS_NR_PIOS 5
125 #define CONFIG_SYS_HSDRAMC
126 #define CONFIG_MMC
127 #define CONFIG_ATMEL_MCI
128
129 #define CONFIG_SYS_DCACHE_LINESZ 32
130 #define CONFIG_SYS_ICACHE_LINESZ 32
131
132 #define CONFIG_NR_DRAM_BANKS 1
133
134 #define CONFIG_SYS_FLASH_CFI
135 #define CONFIG_FLASH_CFI_DRIVER
136
137 #define CONFIG_SYS_FLASH_BASE 0x00000000
138 #define CONFIG_SYS_FLASH_SIZE 0x800000
139 #define CONFIG_SYS_MAX_FLASH_BANKS 1
140 #define CONFIG_SYS_MAX_FLASH_SECT 135
141
142 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
143 #define CONFIG_SYS_TEXT_BASE 0x00000000
144
145 #define CONFIG_SYS_INTRAM_BASE 0x24000000
146 #define CONFIG_SYS_INTRAM_SIZE 0x8000
147
148 #define CONFIG_SYS_SDRAM_BASE 0x10000000
149
150 #define CONFIG_ENV_IS_IN_FLASH
151 #define CONFIG_ENV_SIZE 65536
152 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
153
154 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
155
156 #define CONFIG_SYS_MALLOC_LEN (256*1024)
157
158 #define CONFIG_SYS_DMA_ALLOC_LEN (16384)
159
160 /* Allow 4MB for the kernel run-time image */
161 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00400000)
162 #define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
163
164 /* Other configuration settings that shouldn't have to change all that often */
165 #define CONFIG_SYS_PROMPT "Hammerhead> "
166 #define CONFIG_SYS_CBSIZE 256
167 #define CONFIG_SYS_MAXARGS 16
168 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
169 #define CONFIG_SYS_LONGHELP
170
171 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
172 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
173
174 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
175
176 #endif /* __CONFIG_H */