include/configs/hcu4.h

   1 /*
   2  *(C) Copyright 2005-2007 Netstal Maschinen AG
   3  *    Niklaus Giger (Niklaus.Giger@netstal.com)
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /************************************************************************
  25  * hcu4.h - configuration for HCU4 board (similar to hcu5.h)
  26  ***********************************************************************/
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*-----------------------------------------------------------------------
  32  * High Level Configuration Options
  33  *----------------------------------------------------------------------*/
  34 #define CONFIG_HCU4             1               /* Board is HCU4        */
  35 #define CONFIG_4xx              1               /* ... PPC4xx family    */
  36 #define CONFIG_405GPr 1 /* HCU4 has a 405GPr */
  37 #define CONFIG_405GP 1
  38 #define CONFIG_4xx   1
  39
  40 #define CONFIG_SYS_CLK_FREQ     33333333        /* external freq to pll */
  41
  42 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  43 #define CONFIG_MISC_INIT_R      1               /* Call misc_init_r     */
  44
  45 /*-----------------------------------------------------------------------
  46  * Base addresses -- Note these are effective addresses where the
  47  * actual resources get mapped (not physical addresses)
  48 *----------------------------------------------------------------------*/
  49 #define CFG_MONITOR_LEN (320 * 1024)    /* Reserve 320 kB for Monitor   */
  50 #define CFG_MALLOC_LEN          (256 * 1024) /* Reserve 256 kB for malloc() */
  51
  52
  53 #define CFG_SDRAM_BASE          0x00000000      /* _must_ be 0          */
  54 #define CFG_FLASH_BASE          0xfff80000      /* start of FLASH       */
  55 #define CFG_MONITOR_BASE        TEXT_BASE
  56
  57 /* ... with on-chip memory here (4KBytes) */
  58 #define CFG_OCM_DATA_ADDR 0xF4000000
  59 #define CFG_OCM_DATA_SIZE 0x00001000
  60 /* Do not set up locked dcache as init ram. */
  61 #undef CFG_INIT_DCACHE_CS
  62
  63 /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
  64 #define CFG_TEMP_STACK_OCM 1
  65
  66 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR       /* OCM          */
  67 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE
  68 #define CFG_GBL_DATA_SIZE       256             /* num bytes initial data */
  69 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  70 #define CFG_INIT_SP_OFFSET      CFG_POST_WORD_ADDR
  71
  72 /*-----------------------------------------------------------------------
  73  * Serial Port
  74  *----------------------------------------------------------------------*/
  75 /*
  76  * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  77  * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
  78  * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
  79  * The Linux BASE_BAUD define should match this configuration.
  80  *    baseBaud = cpuClock/(uartDivisor*16)
  81  * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
  82  * set Linux BASE_BAUD to 403200.
  83  */
  84 #undef CFG_EXT_SERIAL_CLOCK            /* external serial clock */
  85 #define CONFIG_SERIAL_MULTI  1
  86 /* needed to be able to define CONFIG_SERIAL_SOFTWARE_FIFO */
  87 #undef  CFG_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
  88 #define CFG_BASE_BAUD       691200
  89
  90 /* Size (bytes) of interrupt driven serial port buffer.
  91  * Set to 0 to use polling instead of interrupts.
  92  * Setting to 0 will also disable RTS/CTS handshaking.
  93  */
  94 #undef CONFIG_SERIAL_SOFTWARE_FIFO
  95
  96 /* Set console baudrate to 9600 */
  97 #define CONFIG_BAUDRATE         9600
  98
  99
 100 #define CFG_BAUDRATE_TABLE                                              \
 101         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 102
 103 /*-----------------------------------------------------------------------
 104  * Flash
 105  *----------------------------------------------------------------------*/
 106
 107 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks */
 108 #define CFG_MAX_FLASH_SECT      8       /* max number of sectors on one chip */
 109
 110 #define CFG_FLASH_EMPTY_INFO    /* print 'E' for empty sector on flinfo */
 111
 112 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 113 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 114
 115 /*-----------------------------------------------------------------------
 116  * Environment
 117  *----------------------------------------------------------------------*/
 118
 119 #undef  CFG_ENV_IS_IN_NVRAM
 120 #define CFG_ENV_IS_IN_FLASH
 121 #undef  CFG_ENV_IS_NOWHERE
 122
 123 #ifdef  CFG_ENV_IS_IN_EEPROM
 124 /* Put the environment after the SDRAM configuration */
 125 #define PROM_SIZE       2048
 126 #define CFG_ENV_OFFSET   512
 127 #define CFG_ENV_SIZE    (PROM_SIZE-CFG_ENV_OFFSET)
 128 #endif
 129
 130 #ifdef CFG_ENV_IS_IN_FLASH
 131 /* Put the environment in Flash */
 132 #define CFG_ENV_SECT_SIZE       0x10000         /* size of one complete sector  */
 133 #define CFG_ENV_ADDR            ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
 134 #define CFG_ENV_SIZE            8*1024  /* 8 KB Environment Sector      */
 135
 136 /* Address and size of Redundant Environment Sector     */
 137 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 138 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 139 #endif
 140
 141 /*-----------------------------------------------------------------------
 142  * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
 143  * the first internal I2C controller of the PPC440EPx
 144  *----------------------------------------------------------------------*/
 145 #define CFG_SPD_BUS_NUM         0
 146
 147 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 148 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 149 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 150 #define CFG_I2C_SLAVE           0x7F
 151
 152 /* This is the 7bit address of the device, not including P. */
 153 #define CFG_I2C_EEPROM_ADDR 0x50
 154 #define CFG_I2C_EEPROM_ADDR_LEN 1
 155
 156 /* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
 157 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 158 #define CFG_EEPROM_PAGE_WRITE_BITS 4
 159 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
 160 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 161 #undef CFG_I2C_MULTI_EEPROMS
 162
 163
 164 #define CONFIG_PREBOOT  "echo;"                                         \
 165         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 166         "echo"
 167
 168 #undef  CONFIG_BOOTARGS
 169
 170 /* Setup some board specific values for the default environment variables */
 171 #define CONFIG_HOSTNAME         hcu4
 172 #define CONFIG_IPADDR           172.25.1.99
 173 #define CONFIG_ETHADDR      00:60:13:00:00:00   /* Netstal Machines AG MAC */
 174 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 175 #define CONFIG_SERVERIP         172.25.1.3
 176
 177 #define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
 178
 179 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 180         "netdev=eth0\0"                                                 \
 181         "loadaddr=0x01000000\0"                                         \
 182         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 183                 "nfsroot=${serverip}:${rootpath}\0"                     \
 184         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 185         "addip=setenv bootargs ${bootargs} "                            \
 186                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 187                 ":${hostname}:${netdev}:off panic=1\0"                  \
 188         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 189         "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"         \
 190                 "bootm\0"                                               \
 191         "rootpath=/home/diagnose/eldk/ppc_4xx\0"                        \
 192         "bootfile=/tftpboot/hcu4/uImage\0"                              \
 193         "load=tftp 100000 hcu4/u-boot.bin\0"                    \
 194         "update=protect off FFFB0000 FFFFFFFF;era FFFC0000 FFFFFFFF;"   \
 195                 "cp.b 100000 FFFB0000 50000\0"                          \
 196         "upd=run load;run update\0"                                     \
 197         "vx=tftp ${loadaddr} hcu4_vx_rom;"                              \
 198         "vx=tftp ${loadaddr} hcu4/hcu4_vx_rom;"                         \
 199         "setenv bootargs emac(0,0)c:hcu4/hcu4_vx_rom e=${ipaddr} "      \
 200         "bootvx ${loadaddr}\0"                                          \
 201         ""
 202 #define CONFIG_BOOTCOMMAND      "run vx"
 203
 204 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 205
 206 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 207 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 208
 209 #define CONFIG_MII              1       /* MII PHY management           */
 210 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
 211
 212 #define CONFIG_PHY_RESET        1       /* reset phy upon startup */
 213
 214 #define CONFIG_HAS_ETH0
 215 #define CFG_RX_ETH_BUFFER       16 /* Number of ethernet rx buffers & desC */
 216
 217 /*
 218  * BOOTP options
 219  */
 220 #define CONFIG_BOOTP_BOOTFILESIZE
 221 #define CONFIG_BOOTP_BOOTPATH
 222 #define CONFIG_BOOTP_GATEWAY
 223 #define CONFIG_BOOTP_HOSTNAME
 224
 225 /*
 226  * Command line configuration.
 227  */
 228 #include <config_cmd_default.h>
 229
 230 #define CONFIG_CMD_ASKENV
 231 #define CONFIG_CMD_CACHE
 232 #define CONFIG_CMD_DHCP
 233 #define CONFIG_CMD_DIAG
 234 #define CONFIG_CMD_EEPROM
 235 #define CONFIG_CMD_ELF
 236 #define CONFIG_CMD_FLASH
 237 #define CONFIG_CMD_I2C
 238 #define CONFIG_CMD_IMMAP
 239 #define CONFIG_CMD_IRQ
 240 #define CONFIG_CMD_MII
 241 #define CONFIG_CMD_NET
 242 #define CONFIG_CMD_PING
 243 #define CONFIG_CMD_REGINFO
 244 #define CONFIG_CMD_SDRAM
 245
 246 /* SPD EEPROM (sdram speed config) disabled */
 247 #define CONFIG_SPD_EEPROM          1
 248 #define SPD_EEPROM_ADDRESS      0x50
 249
 250 /* POST support */
 251 #define CONFIG_POST             (CFG_POST_MEMORY   | \
 252                                  CFG_POST_CPU      | \
 253                                  CFG_POST_UART     | \
 254                                  CFG_POST_I2C      | \
 255                                  CFG_POST_CACHE    | \
 256                                  CFG_POST_ETHER    | \
 257                                  CFG_POST_SPR)
 258
 259 #define CFG_POST_UART_TABLE     {UART0_BASE}
 260 #define CFG_POST_WORD_ADDR      (CFG_GBL_DATA_OFFSET - 0x4)
 261 #undef  CONFIG_LOGBUFFER
 262 #define CFG_POST_CACHE_ADDR     0x00800000 /* free virtual address      */
 263 #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 264
 265 /*-----------------------------------------------------------------------
 266  * Miscellaneous configurable options
 267  *----------------------------------------------------------------------*/
 268 #define CFG_LONGHELP                    /* undef to save memory         */
 269 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 270 #if defined(CONFIG_CMD_KGDB)
 271         #define CFG_CBSIZE      1024            /* Console I/O Buffer Size */
 272 #else
 273         #define CFG_CBSIZE      256             /* Console I/O Buffer Size */
 274 #endif
 275 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 276 #define CFG_MAXARGS     16              /* max number of command args   */
 277 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 278
 279 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 280 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 281
 282
 283 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 284 #define CFG_EXTBDINFO           1       /* To use extended board_into (bd_t) */
 285
 286 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 287
 288 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 289 #define CONFIG_LOOPW            1       /* enable loopw command         */
 290 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 291
 292 /*-----------------------------------------------------------------------
 293  * External Bus Controller (EBC) Setup
 294  */
 295
 296 #define CFG_EBC_CFG     0x98400000
 297
 298 /* Memory Bank 0 (Flash Bank 0) initialization  */
 299 #define CFG_EBC_PB0AP   0x02005400
 300 #define CFG_EBC_PB0CR   0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
 301
 302 #define CFG_EBC_PB1AP   0x03041200
 303 #define CFG_EBC_PB1CR   0x7009A000  /* BAS=,BS=MB,BU=R/W,BW=bit */
 304
 305 #define CFG_EBC_PB2AP   0x02054500
 306 #define CFG_EBC_PB2CR   0x78018000  /* BAS=,BS=MB,BU=R/W,BW=bit */
 307
 308 #define CFG_EBC_PB3AP   0x01840300
 309 #define CFG_EBC_PB3CR   0x7c0ba000  /* BAS=,BS=MB,BU=R/W,BW=bit */
 310
 311 #define CFG_EBC_PB4AP   0x01800300
 312 #define CFG_EBC_PB4CR   0x7e0ba000  /* BAS=,BS=MB,BU=R/W,BW=bit */
 313
 314 #define CFG_GPIO0_OR    0xF27FFFFF  /* GPIO value */
 315 #define CFG_GPIO0_TCR   0x7FFE0000  /* GPIO value */
 316 #define CFG_GPIO0_ODR   0x00E897FC  /* GPIO value */
 317
 318 /*
 319  * For booting Linux, the board info and command line data
 320  * have to be in the first 8 MB of memory, since this is
 321  * the maximum mapped by the Linux kernel during initialization.
 322  */
 323 #define CFG_BOOTMAPSZ           (8 << 20)/* Initial Memory map for Linux */
 324
 325 /* Init Memory Controller:
 326  *
 327  * BR0/1 and OR0/1 (FLASH)
 328  */
 329
 330 #define FLASH_BASE0_PRELIM      CFG_FLASH_BASE  /* FLASH bank #0        */
 331 #define FLASH_BASE1_PRELIM      0               /* FLASH bank #1        */
 332
 333
 334 /* Configuration Port location */
 335 #define CONFIG_PORT_ADDR        0xF0000500
 336
 337
 338 /*
 339  * Internal Definitions
 340  *
 341  * Boot Flags
 342  */
 343 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 344 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 345
 346 #define CFG_HUSH_PARSER                 /* use "hush" command parser    */
 347 #ifdef  CFG_HUSH_PARSER
 348 #define CFG_PROMPT_HUSH_PS2     "> "
 349 #endif
 350
 351 #if defined(CONFIG_CMD_KGDB)
 352 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 353 #define CONFIG_KGDB_SER_INDEX   2           /* which serial port to use */
 354 #endif
 355
 356 /* pass open firmware flat tree */
 357 #define CONFIG_OF_LIBFDT        1
 358 #define CONFIG_OF_BOARD_SETUP   1
 359
 360 #endif  /* __CONFIG_H */