include/configs/hermes.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC860           1       /* This is a MPC860T CPU        */
  37 #define CONFIG_HERMES           1       /* ...on a HERMES-PRO board     */
  38
  39 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  40
  41 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  42 #undef  CONFIG_8xx_CONS_SMC2
  43 #undef  CONFIG_8xx_CONS_NONE
  44 #define CONFIG_BAUDRATE         9600
  45 #if 0
  46 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  47 #else
  48 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  49 #endif
  50
  51 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  52
  53 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  54
  55 #define CONFIG_SHOW_BOOT_PROGRESS 1     /* Show boot progress on LEDs   */
  56
  57 #undef  CONFIG_BOOTARGS
  58 #define CONFIG_BOOTCOMMAND                                                      \
  59         "bootp; "                                                               \
  60         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  61         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
  62         "bootm"
  63
  64 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  65 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  66
  67 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  68
  69
  70 /*
  71  * Command line configuration.
  72  */
  73 #include <config_cmd_default.h>
  74
  75
  76 /*
  77  * BOOTP options
  78  */
  79 #define CONFIG_BOOTP_SUBNETMASK
  80 #define CONFIG_BOOTP_GATEWAY
  81 #define CONFIG_BOOTP_HOSTNAME
  82 #define CONFIG_BOOTP_BOOTPATH
  83
  84
  85 /*
  86  * Miscellaneous configurable options
  87  */
  88 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  89 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
  90 #if defined(CONFIG_CMD_KGDB)
  91 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  92 #else
  93 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  94 #endif
  95 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  96 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  97 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  98
  99 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on     */
 100 #define CONFIG_SYS_MEMTEST_END          0x00F00000      /* 1 ... 15MB in DRAM   */
 101
 102 #define CONFIG_SYS_LOAD_ADDR            0x00100000      /* default load address */
 103
 104 #define CONFIG_SYS_PIO_MODE             0       /* IDE interface in PIO Mode 0  */
 105
 106 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 107
 108 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 109
 110 #define CONFIG_SYS_ALLOC_DPRAM          1       /* use allocation routines      */
 111 /*
 112  * Low Level Configuration Settings
 113  * (address mappings, register initial values, etc.)
 114  * You should know what you are doing if you make changes here.
 115  */
 116 /*-----------------------------------------------------------------------
 117  * Internal Memory Mapped Register
 118  */
 119 #define CONFIG_SYS_IMMR         0xFF000000      /* Non-Standard value!  */
 120
 121 /*-----------------------------------------------------------------------
 122  * Definitions for initial stack pointer and data area (in DPRAM)
 123  */
 124 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 125 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 126 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 127 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 128
 129 /*-----------------------------------------------------------------------
 130  * Start addresses for the final memory configuration
 131  * (Set up by the startup code)
 132  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 133  */
 134 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 135 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 136 #ifdef  DEBUG
 137 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 138 #else
 139 #define CONFIG_SYS_MONITOR_LEN          (128 << 10)     /* Reserve 128 kB for Monitor   */
 140 #endif
 141 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 142 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 143
 144 /*
 145  * For booting Linux, the board info and command line data
 146  * have to be in the first 8 MB of memory, since this is
 147  * the maximum mapped by the Linux kernel during initialization.
 148  */
 149 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 150 /*-----------------------------------------------------------------------
 151  * FLASH organization
 152  */
 153 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 154 #define CONFIG_SYS_MAX_FLASH_SECT       124     /* max number of sectors on one chip    */
 155
 156 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 157 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 158
 159 #define CONFIG_ENV_IS_IN_FLASH  1
 160 #define CONFIG_ENV_OFFSET               0x4000  /*   Offset   of Environment Sector     */
 161 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 162 /*-----------------------------------------------------------------------
 163  * Cache Configuration
 164  */
 165 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 166 #if defined(CONFIG_CMD_KGDB)
 167 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 168 #endif
 169
 170 /*-----------------------------------------------------------------------
 171  * SYPCR - System Protection Control                            11-9
 172  * SYPCR can only be written once after reset!
 173  *-----------------------------------------------------------------------
 174  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 175  * +0x0004
 176  */
 177 #if defined(CONFIG_WATCHDOG)
 178 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 179                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 180 #else
 181 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 182 #endif
 183
 184 /*-----------------------------------------------------------------------
 185  * SIUMCR - SIU Module Configuration                            11-6
 186  *-----------------------------------------------------------------------
 187  * +0x0000 => 0x000000C0
 188  */
 189 #define CONFIG_SYS_SIUMCR       0
 190
 191 /*-----------------------------------------------------------------------
 192  * TBSCR - Time Base Status and Control                         11-26
 193  *-----------------------------------------------------------------------
 194  * Clear Reference Interrupt Status, Timebase freezing enabled
 195  * +0x0200 => 0x00C2
 196  */
 197 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 198
 199 /*-----------------------------------------------------------------------
 200  * PISCR - Periodic Interrupt Status and Control                11-31
 201  *-----------------------------------------------------------------------
 202  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 203  * +0x0240 => 0x0082
 204  */
 205 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 206
 207 /*-----------------------------------------------------------------------
 208  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 209  *-----------------------------------------------------------------------
 210  * Reset PLL lock status sticky bit, timer expired status bit and timer
 211  * interrupt status bit, set PLL multiplication factor !
 212  */
 213 /* +0x0286 => 0x00B0D0C0 */
 214 #define CONFIG_SYS_PLPRCR                                                       \
 215                 (       (11 << PLPRCR_MF_SHIFT) |                       \
 216                         PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |    \
 217                         /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |            \
 218                         PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/   \
 219                 )
 220
 221 /*-----------------------------------------------------------------------
 222  * SCCR - System Clock and reset Control Register               15-27
 223  *-----------------------------------------------------------------------
 224  * Set clock output, timebase and RTC source and divider,
 225  * power management and some other internal clocks
 226  */
 227 #define SCCR_MASK       SCCR_EBDF11
 228 /* +0x0282 => 0x03800000 */
 229 #define CONFIG_SYS_SCCR (SCCR_COM00     |   SCCR_TBS      |     \
 230                          SCCR_RTDIV     |   SCCR_RTSEL    |     \
 231                          /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/       \
 232                          SCCR_EBDF00    |   SCCR_DFSYNC00 |     \
 233                          SCCR_DFBRG00   |   SCCR_DFNL000  |     \
 234                          SCCR_DFNH000)
 235
 236 /*-----------------------------------------------------------------------
 237  * RTCSC - Real-Time Clock Status and Control Register          11-27
 238  *-----------------------------------------------------------------------
 239  */
 240 /* +0x0220 => 0x00C3 */
 241 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 242
 243
 244 /*-----------------------------------------------------------------------
 245  * RCCR - RISC Controller Configuration Register                19-4
 246  *-----------------------------------------------------------------------
 247  */
 248 /* +0x09C4 => TIMEP=1 */
 249 #define CONFIG_SYS_RCCR 0x0100
 250
 251 /*-----------------------------------------------------------------------
 252  * RMDS - RISC Microcode Development Support Control Register
 253  *-----------------------------------------------------------------------
 254  */
 255 #define CONFIG_SYS_RMDS 0
 256
 257 /*-----------------------------------------------------------------------
 258  *
 259  *-----------------------------------------------------------------------
 260  *
 261  */
 262 #define CONFIG_SYS_DER  0
 263
 264 /*
 265  * Init Memory Controller:
 266  *
 267  * BR0 and OR0 (FLASH)
 268  */
 269
 270 #define FLASH_BASE0_PRELIM      0xFE000000      /* FLASH bank #0        */
 271
 272 /* used to re-map FLASH
 273  * restrict access enough to keep SRAM working (if any)
 274  * but not too much to meddle with FLASH accesses
 275  */
 276 /* allow for max 4 MB of Flash */
 277 #define CONFIG_SYS_REMAP_OR_AM          0xFFC00000      /* OR addr mask */
 278 #define CONFIG_SYS_PRELIM_OR_AM 0xFFC00000      /* OR addr mask */
 279
 280 /* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0        */
 281 #define CONFIG_SYS_OR_TIMING_FLASH      ( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \
 282                                  OR_SCY_5_CLK | OR_TRLX)
 283
 284 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 285 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 286 /* 8 bit, bank valid */
 287 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
 288
 289 /*
 290  * BR1/OR1 - SDRAM
 291  *
 292  * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
 293  */
 294 #define SDRAM_BASE_PRELIM       0x00000000      /* SDRAM bank */
 295 #define SDRAM_PRELIM_OR_AM      0xF8000000      /* map max. 128 MB */
 296 #define SDRAM_TIMING            0x00000A00      /* SDRAM-Timing */
 297
 298 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB SDRAM */
 299
 300 #define CONFIG_SYS_OR1_PRELIM   (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
 301 #define CONFIG_SYS_BR1_PRELIM   ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 302
 303 /*
 304  * BR2/OR2 - HPRO2: PEB2256   @ 0xE0000000, 8 Bit wide
 305  */
 306 #define HPRO2_BASE              0xE0000000
 307 #define HPRO2_OR_AM             0xFFFF8000
 308 #define HPRO2_TIMING            0x00000934
 309
 310 #define CONFIG_SYS_OR2 (HPRO2_OR_AM | HPRO2_TIMING)
 311 #define CONFIG_SYS_BR2  ((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 312
 313 /*
 314  * BR3/OR3: not used
 315  * BR4/OR4: not used
 316  * BR5/OR5: not used
 317  * BR6/OR6: not used
 318  * BR7/OR7: not used
 319  */
 320
 321 /*
 322  * MAMR settings for SDRAM
 323  */
 324
 325 /* periodic timer for refresh */
 326 #define CONFIG_SYS_MAMR_PTA     97              /* start with divider for 100 MHz       */
 327
 328 /* 8 column SDRAM */
 329 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 330                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 331                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 332 /* 9 column SDRAM */
 333 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 334                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 335                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 336 #endif  /* __CONFIG_H */