include/configs/hmi1001.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31
  32 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU               */
  33 #define CONFIG_MPC5200          1       /* (more precisely an MPC5200 CPU)      */
  34 #define CONFIG_HMI1001          1       /* HMI1001 board                        */
  35
  36 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz         */
  37
  38 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH     */
  39 #define BOOTFLAG_WARM           0x02    /* Software reboot                      */
  40
  41 #define CONFIG_BOARD_EARLY_INIT_R
  42
  43 #define CONFIG_HIGH_BATS        1       /* High BATs supported                  */
  44
  45 /*
  46  * Serial console configuration
  47  */
  48 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1   */
  49 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps    */
  50 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  51
  52 /* Partitions */
  53 #define CONFIG_DOS_PARTITION
  54
  55
  56 /*
  57  * BOOTP options
  58  */
  59 #define CONFIG_BOOTP_BOOTFILESIZE
  60 #define CONFIG_BOOTP_BOOTPATH
  61 #define CONFIG_BOOTP_GATEWAY
  62 #define CONFIG_BOOTP_HOSTNAME
  63
  64
  65 /*
  66  * Command line configuration.
  67  */
  68 #include <config_cmd_default.h>
  69
  70 #define CONFIG_CMD_DATE
  71 #define CONFIG_CMD_DISPLAY
  72 #define CONFIG_CMD_DHCP
  73 #define CONFIG_CMD_EEPROM
  74 #define CONFIG_CMD_I2C
  75 #define CONFIG_CMD_IDE
  76 #define CONFIG_CMD_NFS
  77 #define CONFIG_CMD_PCI
  78 #define CONFIG_CMD_SNTP
  79
  80
  81 #define CONFIG_TIMESTAMP        1       /* Print image info with timestamp */
  82
  83 #if (TEXT_BASE == 0xFFF00000) /* Boot low */
  84 #   define CONFIG_SYS_LOWBOOT           1
  85 #endif
  86
  87 /*
  88  * Autobooting
  89  */
  90 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
  91
  92 #define CONFIG_PREBOOT  "echo;" \
  93         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  94         "echo"
  95
  96 #undef  CONFIG_BOOTARGS
  97
  98 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  99         "netdev=eth0\0"                                                 \
 100         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 101                 "nfsroot=${serverip}:${rootpath}\0"                     \
 102         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 103         "addip=setenv bootargs ${bootargs} "                            \
 104                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 105                 ":${hostname}:${netdev}:off panic=1\0"                  \
 106         "flash_nfs=run nfsargs addip;"                                  \
 107                 "bootm ${kernel_addr}\0"                                \
 108         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 109         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
 110         ""
 111
 112 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 113
 114 #define CONFIG_MISC_INIT_R      1
 115
 116 /*
 117  * IPB Bus clocking configuration.
 118  */
 119 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK          /* define for 133MHz speed */
 120
 121 /*
 122  * I2C configuration
 123  */
 124 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 125 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #1 or #2 */
 126
 127 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 128 #define CONFIG_SYS_I2C_SLAVE            0x7F
 129
 130 /*
 131  * EEPROM configuration
 132  */
 133 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x58
 134 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 135 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 136 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 137
 138 /*
 139  * RTC configuration
 140  */
 141 #define CONFIG_RTC_PCF8563
 142 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 143
 144 /*
 145  * Flash configuration
 146  */
 147 #define CONFIG_SYS_FLASH_BASE           0xFF800000
 148
 149 #define CONFIG_SYS_FLASH_SIZE           0x00800000 /* 8 MByte */
 150 #define CONFIG_SYS_MAX_FLASH_SECT       67      /* max num of sects on one chip */
 151
 152 #define CONFIG_ENV_ADDR         (TEXT_BASE+0x40000) /* second sector */
 153 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks
 154                                            (= chip selects) */
 155 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 156 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 157
 158 #define CONFIG_FLASH_CFI_DRIVER
 159 #define CONFIG_SYS_FLASH_CFI
 160 #define CONFIG_SYS_FLASH_EMPTY_INFO
 161 #define CONFIG_SYS_FLASH_CFI_AMD_RESET
 162
 163 /*
 164  * Environment settings
 165  */
 166 #define CONFIG_ENV_IS_IN_FLASH  1
 167 #define CONFIG_ENV_SIZE         0x4000
 168 #define CONFIG_ENV_SECT_SIZE    0x20000
 169 #define CONFIG_ENV_OFFSET_REDUND   (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 170 #define CONFIG_ENV_SIZE_REDUND     (CONFIG_ENV_SIZE)
 171
 172 /*
 173  * Memory map
 174  */
 175 #define CONFIG_SYS_MBAR         0xF0000000
 176 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 177 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 178 #define CONFIG_SYS_DISPLAY_BASE 0x80600000
 179 #define CONFIG_SYS_STATUS1_BASE 0x80600200
 180 #define CONFIG_SYS_STATUS2_BASE 0x80600300
 181
 182 /* Settings for XLB = 132 MHz */
 183 #define SDRAM_DDR        1
 184 #define SDRAM_MODE      0x018D0000
 185 #define SDRAM_EMODE     0x40090000
 186 #define SDRAM_CONTROL   0x714f0f00
 187 #define SDRAM_CONFIG1   0x73722930
 188 #define SDRAM_CONFIG2   0x47770000
 189 #define SDRAM_TAPDELAY  0x10000000
 190
 191 /* Use ON-Chip SRAM until RAM will be available */
 192 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 193
 194 /* preserve space for the post_word at end of on-chip SRAM */
 195 #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
 196
 197 #ifdef CONFIG_POST
 198 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
 199 #else
 200 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
 201 #endif
 202
 203 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* size in bytes reserved for initial data */
 204 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 205 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 206
 207 #define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
 208 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 209 #   define CONFIG_SYS_RAMBOOT           1
 210 #endif
 211
 212 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 213 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)     /* Reserve 128 kB for malloc()  */
 214 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 215
 216 /*
 217  * Ethernet configuration
 218  */
 219 #define CONFIG_MPC5xxx_FEC      1
 220 #define CONFIG_MPC5xxx_FEC_MII100
 221 #define CONFIG_PHY_ADDR         0x00
 222 #define CONFIG_MII              1               /* MII PHY management           */
 223
 224 /*
 225  * GPIO configuration
 226  */
 227 #define CONFIG_SYS_GPS_PORT_CONFIG      0x01051004
 228
 229 /*
 230  * Miscellaneous configurable options
 231  */
 232 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 233 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
 234 #if defined(CONFIG_CMD_KGDB)
 235 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 236 #else
 237 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 238 #endif
 239 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 240 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 241 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 242
 243 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs                     */
 244 #if defined(CONFIG_CMD_KGDB)
 245 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 246 #endif
 247
 248 /* Enable an alternate, more extensive memory test */
 249 #define CONFIG_SYS_ALT_MEMTEST
 250
 251 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 252 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 253
 254 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 255
 256 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 257
 258 /*
 259  * Enable loopw command.
 260  */
 261 #define CONFIG_LOOPW
 262
 263 /*
 264  * Various low-level settings
 265  */
 266 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 267 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 268
 269 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 270 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 271 #define CONFIG_SYS_BOOTCS_CFG           0x0004FB00
 272 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 273 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 274
 275 /* 8Mbit SRAM @0x80100000 */
 276 #define CONFIG_SYS_CS1_START            0x80100000
 277 #define CONFIG_SYS_CS1_SIZE             0x00100000
 278 #define CONFIG_SYS_CS1_CFG              0x19B00
 279
 280 /* FRAM 32Kbyte @0x80700000 */
 281 #define CONFIG_SYS_CS2_START            0x80700000
 282 #define CONFIG_SYS_CS2_SIZE             0x00008000
 283 #define CONFIG_SYS_CS2_CFG              0x19800
 284
 285 /* Display H1, Status Inputs, EPLD @0x80600000 */
 286 #define CONFIG_SYS_CS3_START            0x80600000
 287 #define CONFIG_SYS_CS3_SIZE             0x00100000
 288 #define CONFIG_SYS_CS3_CFG              0x00019800
 289
 290 #define CONFIG_SYS_CS_BURST             0x00000000
 291 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 292
 293 /*-----------------------------------------------------------------------
 294  * IDE/ATA stuff Supports IDE harddisk
 295  *-----------------------------------------------------------------------
 296  */
 297
 298 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 299
 300 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 301 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 302
 303 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 304 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 2 drives per IDE bus    */
 305
 306 #define CONFIG_IDE_PREINIT      1
 307
 308 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 309
 310 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 311
 312 /* Offset for data I/O                  */
 313 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 314
 315 /* Offset for normal register accesses  */
 316 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 317
 318 /* Offset for alternate registers       */
 319 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 320
 321 /* Interval between registers                                                */
 322 #define CONFIG_SYS_ATA_STRIDE          4
 323
 324 #define CONFIG_ATAPI            1
 325
 326 #define CONFIG_VIDEO_SMI_LYNXEM
 327 #define CONFIG_CFB_CONSOLE
 328 #define CONFIG_VGA_AS_SINGLE_DEVICE
 329 #define CONFIG_VIDEO_LOGO
 330
 331 /*
 332  * PCI Mapping:
 333  * 0x40000000 - 0x4fffffff - PCI Memory
 334  * 0x50000000 - 0x50ffffff - PCI IO Space
 335  */
 336 #define CONFIG_PCI              1
 337 #define CONFIG_PCI_PNP          1
 338 #define CONFIG_PCI_SCAN_SHOW    1
 339 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
 340
 341 #define CONFIG_PCI_MEM_BUS      0x40000000
 342 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
 343 #define CONFIG_PCI_MEM_SIZE     0x10000000
 344
 345 #define CONFIG_PCI_IO_BUS       0x50000000
 346 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
 347 #define CONFIG_PCI_IO_SIZE      0x01000000
 348
 349 #define CONFIG_SYS_ISA_IO               CONFIG_PCI_IO_BUS
 350
 351 /*---------------------------------------------------------------------*/
 352 /* Display addresses                                                   */
 353 /*---------------------------------------------------------------------*/
 354
 355 #define CONFIG_PDSP188x
 356 #define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
 357 #define CONFIG_SYS_DISP_CWORD           (CONFIG_SYS_DISPLAY_BASE + 0x30)
 358
 359 #endif /* __CONFIG_H */